STL4LN80K5 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 14
Technical content
Datasheet sections
- 1 Electrical ratings
- 2 Electrical characteristics
- 3 Test circuits
- 4 Package information
- 4.1 PowerFLAT™ 5x6 VHV package information
- 4.2 PowerFLAT™ 5x6 packing information
- 5 Revision history
Features
Order code VDS RDS(on) max. ID STL4LN80K5 800 V 2.6 Ω 3 A Industry’s lowest RDS(on) * area Industry’s best FoM (figure of merit) Ultra low-gate charge 100% avalanche tested Zener-protected
Applications
Switching applications
Description
This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code Marking Package Packing STL4LN80K5 4LN80K5 PowerFLAT™ 5x6 VHV Tape and reel 2 3 4 PowerFLAT™ 5x6 VHV 5678 1 2 3 4 Top View D(5, 6, 7, 8) G(4) S(1, 2, 3)
1 Electrical ratings
Table 2: Absolute maximum ratings Symbol Parameter Value Unit VGS Gate-source voltage ± 30 V ID Drain current (continuous) at TC = 25 °C 3 A ID Drain current (continuous) at TC = 100 °C 1.9 A IDM (1) Drain current (pulsed) 12 A PTOT Total dissipation at TC = 25 °C 38 W dv/dt (2) Peak diode recovery voltage slope 15 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 Tj Operating junction temperature - 55 to 150 °C Tstg Storage temperature Notes: (1)Pulse width limited by safe operating area (2)ISD ≤ 3 A, dv/dt ≤ 100 A/μs; VDS peak < V(BR)DSS (3)VDS ≤ 640 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 3.3 °C/W Rthj-pcb (1) Thermal resistance junction-pcb 59 °C/W Notes: (1)When mounted on FR-4 board of 1 inch², 2 oz Cu Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) TBD A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) TBD mJ
2 Electrical characteristics
TC = 25 °C unless otherwise specified Table 5: On/off-state Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA 800 V IDSS Zero gate voltage drain current VGS = 0 V, VDS = 800 V 1 µA VGS = 0 V, VDS = 800 V TC = 125 °C 50 µA IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 3 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 1.2 A 2.1 2.6 Ω Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V - 110 - pF Coss Output capacitance - 9.5 - pF Crss Reverse transfer capacitance - 0.4 - pF Coss(eq) (1) Equivalent output capacitance VDS = 0 to 640 V, VGS = 0 V - TBD - pF Rg Intrinsic gate resistance f = 1 MHz, ID = 0 A - 18 - Ω Qg Total gate charge VDD = 640 V, ID = 2 A VGS= 10 V, see Figure 3: "Gate charge test circuit" - 4 - nC Qgs Gate-source charge - TBD - nC Qgd Gate-drain charge - TBD - nC Notes: (1)Coss eq is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD= 400 V, ID = 1.6 A, RG = 4.7 Ω VGS = 10 V (See Figure 2: "Switching times test circuit for resistive load"and Figure 7: "Switching time waveform") - TBD - ns tr Rise time - TBD - ns td(off) Turn-off delay time - TBD - ns tf Fall time - TBD - ns
Table 8: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current 3 A ISDM (1) Source-drain current (pulsed) 12 A VSD (2) Forward on voltage ISD = 3 A, VGS = 0 V - 1.6 V trr Reverse recovery time ISD = 3 A, di/dt = 100 A/µs, VDD = 60 V, (see Figure 4: "Test circuit for inductive load switching and diode recovery times") - TBD ns Qrr Reverse recovery charge - TBD µC IRRM Reverse recovery current - TBD A trr Reverse recovery time ISD = 3 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (Figure 4: "Test circuit for inductive load switching and diode recovery times") - TBD ns Qrr Reverse recovery charge - TBD µC IRRM Reverse recovery current - TBD A Notes: (1)Pulse width limited by safe operating area (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate source-Zener diode Symbol Parameter Test condition Min. Typ. Max. Unit. V(BR)GS0 Gate-source breakdown voltage IGS= ± 1mA, ID= 0 A 30 - - V The built-in back-to-back Zener diodes have specifically been designed to enhance the device's ESD capability. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components.
3 Test circuits
Figure 2: Switching times test circuit for resistive load Figure 3: Gate charge test circuit Figure 4: Test circuit for inductive load switching and diode recovery times Figure 5: Unclamped inductive load test circuit Figure 6: Unclamped inductive waveform Figure 7: Switching time waveform
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
4.1 PowerFLAT™ 5x6 VHV package information
Figure 8: PowerFLAT™ 5x6 VHV Package outline Bottom view Side view Top view 1 2 3 4 Pin 1 identification 8 7 6 5 8 7 6 5 1 2 3 4Pin 1 identification
Table 10: PowerFLAT™ 5x6 VHV package mechanical data Dim. mm Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 0.25 b 0.30 0.50 D 5.00 5.20 5.40 E 5.95 6.15 6.35 D2 4.30 4.40 4.50 E2 2.40 2.50 2.60 e 1.27 L 0.50 0.55 0.60 K 2.60 2.70 2.80
Figure 9: PowerFLAT™ 5x6 VHV recommended footprint (dimensions are in mm)
4.2 PowerFLAT™ 5x6 packing information
Figure 10: PowerFLAT™ 5x6 tape (dimensions are in mm) Figure 11: PowerFLAT™ 5x6 package orientation in carrier tape
Figure 12: PowerFLAT™ 5x6 reel
5 Revision history
Table 11: Document revision history Date Revision Changes 29-May-2015 1 First release.