STL45N10F7AG STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 15
Technical content
Datasheet sections
- 1 Electrical ratings
- 2 Electrical characteristics
- 2.1 Electrical characteristics (curves)
- 3 Test circuits
- 4 Package information
- 4.1 PowerFLAT™ 5x6 WF type R package information
- 4.2 PowerFLAT™ 5x6 packing information
- 5 Revision history
Features
Order code VDS RDS(on) max ID PTOT STL45N10F7AG 100 V 24 mΩ 18 A 72 W AEC-Q101 qualified Among the lowest RDS(on) on the market Excellent FoM (figure of merit) Low Crss/Ciss ratio for EMI immunity High avalanche ruggedness Wettable flank package
Applications
Switching applications
Description
This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low on- state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. Table 1: Device summary Order code Marking Package Packing STL45N10F7AG 45N10F7 PowerFLAT™ 5x6 Tape and reel
1 Electrical ratings
Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 100 V VGS Gate-source voltage ±20 V ID(1) Drain current (continuous) at TC = 25 °C 18 A ID (1) Drain current (continuous) at TC = 100 °C 18 A IDM(2) Drain current (pulsed) 72 A PTOT Total dissipation at TC = 25 °C 72 W EAS(3) Single pulse avalanche energy 150 mJ TJ Operating junction temperature range -55 to 175 °C Tstg Storage temperature range Notes: (1)Limited by package. (2)Pulse width limited by safe operating area. (3)Starting Tj = 25 °C, ID = 9 A, VDD = 60 V Table 3: Thermal resistance Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 2.08 °C/W Rthj-pcb (1) Thermal resistance junction-pcb 31.3 °C/W Notes: (1)When mounted on FR-4 board of 1inch², 2oz Cu, t < 10 s
2 Electrical characteristics
(TCASE = 25 °C unless otherwise specified) Table 4: On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage VGS= 0 V, ID = 250 µA 100 V IDSS Zero gate voltage drain current VGS = 0 V, VDS = 100 V 1 µA VGS = 0 V, VDS = 100 V; TC = 125 °C(1) 10 IGSS Gate body leakage current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2.5 4.5 V RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 9 A 20 24 mΩ Notes: (1)Defined by design, not subject to production test. Table 5: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance VDS = 50 V, f = 1 MHz, VGS = 0 V - 1450 - pF Coss Output capacitance - 350 - pF Crss Reverse transfer capacitance - 25 - pF Qg Total gate charge VDD = 50 V, ID = 18 A, VGS = 0 to 10 V (see Figure 14: "Test circuit for gate charge behavior") - 19.5 - nC Qgs Gate-source charge - 9.1 - nC Qgd Gate-drain charge - 4.3 - nC Table 6: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 50 V, ID = 9 A, RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform") - 15 - ns tr Rise time - 5.5 - ns td(off) Turn-off delay time - 17 - ns tf Fall time - 5 - ns
Table 7: Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 18 A ISDM(1) Source-drain current (pulsed) - 72 A VSD(2) Forward on voltage ISD = 9 A, VGS = 0 V - 1.2 V trr Reverse recovery time ISD = 18 A, di/dt = 100 A/µs, VDD = 80 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 46 ns Qrr Reverse recovery charge - 46 nC IRRM Reverse recovery current - 2 A Notes: (1)Pulse width limited by safe operating area (2)Pulsed: pulse duration=300 µs, duty cycle 1.5%
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
Test circuits STL45N10F7AG
3 Test circuits
Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
4.1 PowerFLAT™ 5x6 WF type R package information
Figure 19: PowerFLAT™ 5x6 WF type R package outline
Table 8: PowerFLAT™ 5x6 WF type R mechanical data Dim. mm Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 0.25 b 0.30 0.50 C 5.80 6.00 6.10 D 5.00 5.20 5.40 D2 4.15 4.45 D3 4.05 4.20 4.35 D4 4.80 5.00 5.10 D5 0.25 0.4 0.55 D6 0.15 0.3 0.45 e 1.27 E 6.20 6.40 6.60 E2 3.50 3.70 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 E6 0.20 0.325 0.45 E7 0.85 1.00 1.15 E9 4.00 4.20 4.40 E10 3.55 3.70 3.85 K 1.275 1.575 L 0.725 0.825 0.925 L1 0.175 0.275 0.375 ϴ 0° 12°
Figure 20: PowerFLAT™ 5x6 recommended footprint (dimensions are in mm) 8231817_FOOTPRINT_rev14
4.2 PowerFLAT™ 5x6 packing information
Figure 21: PowerFLAT™ 5x6 WF tape (dimensions are in mm) Figure 22: PowerFLAT™ 5x6 package orientation in carrier tape
Figure 23: PowerFLAT™ 5x6 reel (dimensions are in mm)
5 Revision history
Table 9: Document revision history Date Revision Changes 16-Feb-2017 1 First release.