STL40C30H3LL STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 19

Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves) for N-channel
  • 2.2 Electrical characteristics (curves) for P-channel
  • 3 Test circuits for N-channel
  • 4 Test circuits for P-channel
  • 5 Package mechanical data
  • 6 Packaging mechanical data
  • 7 Revision history

Features

  • RDS(on) * Qg industry benchmark
  • Extremely low on-resistance RDS(on)
  • High avalanche ruggedness
  • Low gate drive power losses

Applications

  • Switching applications

Description

This device is a complementary N-channel and P- channel Power MOSFET developed using STripFET™ V (P-channel) and STripFET™ VI DeepGATE™ (N-channel) technologies. The resulting device exhibits low on-state resistance and an FOM among the lowest in its voltage class. Note: For the P-channel MOSFET actual polarity of voltages and current has to be reversed PowerFLAT™5x6 double island AM00623v2 Order code Channel V DS RDS(on) max I D STL40C30H3LL N 30 V 0.021 Ω @ 10 V 10 A P0 . 0 3 Ω @ 10 V 8 A Table 1. Device summary

1 Electrical ratings

Table 2. Absolute maximum ratings

  1. The value is rated according to R thj-c
  2. This value is rated according to R thj-pcb
  3. Pulse width is limited by safe operating area

Table 3. Thermal data

  1. When mounted on 1 inch² FR-4 board, 2 oz. Cu., t ≤ 10 sec

2 Electrical characteristics

Table 4. On/off states Table 5. Dynamic

2.1 Electrical characteristics (curves) for N-channel

Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Normalized V(BR)DSS vs temperature Figure 7. Static drain-source on-resistance

2.2 Electrical characteristics (curves) for P-channel

Figure 13. Safe operating area Figure 14. Thermal impedance Figure 15. Output characteristics Figure 16. Transfer characteristics Figure 17. Gate charge vs gate-source voltage Figure 18. Static drain-source on-resistance

3 Test circuits for N-channel

Figure 24. Switching times test circuit for Figure 25. Gate charge test circuit Figure 26. Test circuit for inductive load Figure 27. Unclamped inductive load test circuit Figure 28. Unclamped inductive waveform Figure 29. Switching time waveform

4 Test circuits for P-channel

Figure 30. Switching times test circuit for Figure 31. Gate charge test circuit Figure 32. Test circuit for diode recovery

5 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

Figure 33. PowerFLAT™ 5x6 - double island type R-B drawing

Table 8. PowerFLAT™ 5x6 - double island type R-B mechanical data

Figure 34. PowerFLAT™ 5x6 - double island type R-B drawing recommended

6 Packaging mechanical data

Figure 35. PowerFLAT™ 5x6 tape (a) Figure 36. PowerFLAT™ 5x6 package orientation in carrier tape. a. All dimensions are in millimeters. hole to centerline of pocket.

Figure 37. PowerFLAT™ 5x6 reel

7 Revision history

Table 9. Revision history 31-Oct-2012 1 First revision.