STL36N55M5 STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 17

Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuits
  • 4 Package mechanical data
  • 5 Packaging mechanical data
  • 6 Revision history

Features

■ 100% avalanche tested ■ Low input capacitance and gate charge ■ Low gate input resistance

Applications

■ Switching applications

Description

This device is an N-channel MDmesh™ V Power MOSFET based on an innovative proprietary vertical process technology, which is combined with STMicroelectronics’ well-known PowerMESH™ horizontal layout structure. The resulting product has extremely low on- resistance, which is unmatched among silicon- based Power MOSFETs, making it especially suitable for applications which require superior power density and outstanding efficiency. Figure 1. Internal schematic diagram

  1. The value is rated according to R thj-case and limited by

Table 1. Device summary

1 Electrical ratings

Table 2. Absolute maximum ratings

  1. The value is rated according to R thj-case and limited by package..
  2. Pulse width limited by safe operating area.
  3. When mounted on FR-4 board of inch², 2oz Cu.

Table 3. Thermal data

  1. When mounted on FR-4 board of inch², 2oz Cu.

2 Electrical characteristics

Table 4. On /off states Table 5. Dynamic

  1. C o(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0
  2. C o(tr) is a constant capacitance value that gives the same charging time as C oss while VDS is rising from 0

Table 6. Switching times Table 7. Source drain diode

  1. The value is rated according to R thj-case and limited by package..
  2. Pulse width limited by safe operating area
  3. Pulsed: pulse duration = 300 µs, duty cycle 1.5%

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Gate charge vs gate-source voltage Figure 7. Static drain-source on-resistance

Figure 8. Capacitance variations Figure 9. Output capacitance stored energy Figure 10. Normalized gate threshold voltage Figure 11. Normalized on-resistance vs Figure 12. Source-drain diode forward Figure 13. Normalized B VDSS vs temperature

2.1 VGS=10V

Figure 14. Switching losses vs gate resistance

  1. Eon including reverse recovery of a SiC diode

3 Test circuits

Figure 15. Switching times test circuit for Figure 16. Gate charge test circuit Figure 17. Test circuit for inductive load Figure 18. Unclamped inductive load test Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

Table 8. PowerFLAT™ 8x8 HV mechanical data

Figure 21. PowerFLAT™ 8x8 HV drawing mechanical data

Figure 22. PowerFLAT™ 8x8 HV recommended footprint

5 Packaging mechanical data

Figure 23. PowerFLAT™ 8x8 HV tape Figure 24. PowerFLAT™ 8x8 HV package orientation in carrier tape.

Figure 25. PowerFLAT™ 8x8 HV reel

6 Revision history

Table 9. Document revision history 14-Dec-2011 1 First release.