STL20NF06LAG STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 14
Technical content
Datasheet sections
- 1 Electrical ratings
- 2 Electrical characteristics
- 2.1 Electrical characteristics (curves)
- 3 Test circuits
- 4 Package information
- 4.1 PowerFLAT™ 5x6 WF type R package information
- 4.2 PowerFLAT™ 5x6 WF packing information
- 5 Revision history
Features
Order code VDS RDS(on) max. ID PTOT STL20NF06LAG 60 V 40 mΩ 20 A 75 W Designed for Automotive applications and AEC-Q101 qualified PowerFLAT™ 5x6 with wettable flanks Logic level VGS(th) Maximum junction temperature: TJ = 175 °C
Applications
Switching applications
Description
This Power MOSFET series realized with STMicroelectronics unique STripFET™ process is specifically designed to minimize input capacitance and gate charge. It is therefore ideal as a primary switch in advanced high-efficiency isolated DC-DC converters for Telecom and Computer applications. It is also suitable for any application with low gate charge drive requirements. Table 1: Device summary Order code Marking Package Packing STL20NF06LAG 20NF06L PowerFLAT™ 5x6 Tape and reel 5678 1 2 3 4 Top View D(5, 6, 7, 8) G(4) S(1, 2, 3)
1 Electrical ratings
Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 60 V VGS Gate-source voltage ±20 V ID(1)(2) Drain current (continuous) at Tcase = 25 °C 20 A Drain current (continuous) at Tcase = 100 °C 20 IDM(1)(3) Drain current (pulsed) 80 A ID(4) Drain current (continuous) at Tpcb = 25 °C 7.4 A Drain current (continuous) at Tpcb = 100 °C 5.2 IDM Drain current (pulsed) 29.6 A PTOT Total dissipation at Tcase = 25 °C 75 W PTOT Total dissipation at Tpcb = 25 °C 4.8 Tstg Storage temperature -55 to 175 °C Tj Operating junction temperature Notes: (1) This value is rated according to Rthj-c. (2) Current limited by package. (3) Pulse width is limited by safe operating area. (4) This value is rated according to Rthj-pcb. Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 2.0 °C/W Rthj-pcb(1) Thermal resistance junction-pcb 31.3 Notes: (1) When mounted on a 1-inch² FR-4, 2 Oz copper board, t < 10 s. Table 4: Avalanche characteristics Symbol Parameter Value Unit IAV Avalanche current, not repetitive 7.4 A EAS(1) Single pulse avalanche energy 210 mJ Notes: (1) starting Tj = 25 °C, ID = IAV.
2 Electrical characteristics
(Tcase = 25 °C unless otherwise specified) Table 5: Static Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 250 µA 60 V IDSS Zero gate voltage drain current VGS = 0 V, VDS = 60 V 1 µA VGS = 0 V, VDS = 60 V, TC = 125 °C 100 µA IGSS Gate-body leakage current VDS = 0 V, VGS = ±20 V ±100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 1 2.5 V RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 4 A 27 40 mΩ VGS = 5 V, ID = 4 A 32 50 Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance VDS = 25 V, f = 1 MHz, VGS = 0 V - 670 - pF Coss Output capacitance - 170 - Crss Reverse transfer capacitance - 56 - Qg Total gate charge VDD = 25 V, ID = 7.4 A, VGS = 10 V (see Figure 15: "Gate charge test circuit") - 22.5 - nC Qgs Gate-source charge - 2.5 - Qgd Gate-drain charge - 7 - Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 30 V, ID = 3.7 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Switching times test circuit for resistive load" and Figure 19: "Switching time waveform") - 7 - ns tr Rise time - 15.4 - td(off) Turn-off delay time - 36.8 - tf Fall time - 7.7 -
Table 8: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current 7.4 A ISDM(1) Source-drain current (pulsed) 29.6 A VSD(2) Forward on voltage VGS = 0 V, ISD = 7.4 A - 1.5 V trr Reverse recovery time ISD = 7.4 A, di/dt = 100 A/µs, VDD = 48 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 28 ns Qrr Reverse recovery charge - 31.6 nC IRRM Reverse recovery current - 2.26 A Notes: (1) Pulse width is limited by safe operating area. (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
Test circuits STL20NF06LAG
3 Test circuits
Figure 14: Switching times test circuit for resistive load Figure 15: Gate charge test circuit Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
4.1 PowerFLAT™ 5x6 WF type R package information
Figure 20: PowerFLAT™ 5x6 WF type R package outline
Table 9: PowerFLAT™ 5x6 WF type R mechanical data Dim. mm Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 0.25 b 0.30 0.50 D 5.00 5.20 5.40 E 6.20 6.40 6.60 D2 4.11 4.31 E2 3.50 3.70 e 1.27 L 0.70 0.90 0.275 K 1.275 1.575 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 Figure 21: PowerFLAT™ 5x6 recommended footprint (dimensions are in mm)
4.2 PowerFLAT™ 5x6 WF packing information
Figure 22: PowerFLAT™ 5x6 WF tape Figure 23: PowerFLAT™ 5x6 package orientation in carrier tape
Figure 24: PowerFLAT™ 5x6 reel
5 Revision history
Table 10: Document revision history Date Revision Changes 28-Sep-2015 1 First release.