STL18N55M5 STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 14

Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuits
  • 4 Package mechanical data
  • 5 Revision history

Features

■ 100% avalanche tested ■ Low input capacitance and gate charge ■ Low gate input resistance Application ■ Switching applications

Description

This device is an N-channel MDmesh™ V Power MOSFET based on an innovative proprietary vertical process technology, which is combined with STMicroelectronics’ well-known PowerMESH™ horizontal layout structure. The resulting product has extremely low on- resistance, which is unmatched among silicon- based Power MOSFETs, making it especially suitable for applications which require superior power density and outstanding efficiency. Figure 1. Internal schematic diagram

  1. The value is rated according to R thj-case

Table 1. Device summary

1 Electrical ratings

Table 2. Absolute maximum ratings

  1. The value is rated according to R thj-case
  2. Pulse width limited by safe operating area
  3. When mounted on FR-4 board of inch², 2oz Cu

Table 3. Thermal data

  1. When mounted on 1inch² FR-4 board, 2 oz Cu

2 Electrical characteristics

Table 4. On /off states Table 5. Dynamic

  1. C oss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss
  2. C oss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as

Table 6. Switching times Table 7. Source drain diode

  1. Pulse width limited by safe operating area
  2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%

2.1 Electrical characteri stics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Gate charge vs gate-source voltage Figure 7. Static drain-source on resistance

3 Test circuits

Figure 14. Switching times test circuit for Figure 15. Gate charge test circuit Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test Figure 18. Unclamped inductive wavefor m Figure 19. Switching time waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

Table 8. PowerFLAT™ 8x8 HV mechanical data

Figure 20. PowerFLAT™ 8x8 HV drawing mechanical data

Figure 21. PowerFLAT™ 8x8 HV recommended footprint

5 Revision history

Table 9. Document revision history