STL15N65M5 STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 16

Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuits
  • 4 Package information
  • 4.1 Power Flat™ 5x6 HV package information
  • 4.2 Power Flat™ 5x6 HV packing information
  • 5 Revision history

Features

Order code V DS @ TJ max. RDS(on) max ID STL15N65M5 710 V 0.375 Ω 10 A  Extremely low RDS(on)  Low gate charge and input capacitance  Excellent switching performance  100% avalanche tested

Applications

 Switching applications

Description

This device is an N-channel Power MOSFET based on the MDmesh™ M5 innovative vertical process technology combined with the well- known PowerMESH™ horizontal layout. The resulting product offers extremely low on- resistance, making it particularly suitable for applications requiring high power and superior efficiency. Table 1: Device summary Order code Marking Package Packing STL15N65M5 15N65M5 PowerFLAT™ 5x6 HV Tape and reel PowerFLAT™ 5x6 HV

1 Electrical ratings

Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 650 V VGS Gate-source voltage ± 25 V ID Drain current (continuous) at TC = 25 °C 10 A ID Drain current (continuous) at TC = 100 °C 5 A IDM (1) Drain current (pulsed) 40 A PTOT Total dissipation at TC = 25 °C 52 W IAR Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) 2.5 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 160 mJ dv/dt (2) Peak diode recovery voltage slope 15 V/ns Tstg Storage temperature range - 55 to 150 Tj Operating junction temperature range °C Notes: (1)Pulse width limited by safe operating area. (2)ISD ≤ 10 A, di/dt ≤ 400 A/µs, VDS(peak) ≤ V(BR)DSS, VDD = 400 V. Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 2.4 °C/W Rthj-pcb(1) Thermal resistance junction-pcb 59 °C/W Notes: (1)When mounted on 1inch² FR-4 board, 2 oz Cu.

2 Electrical characteristics

(TC = 25 °C unless otherwise specified) Table 4: On /off states Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage ID = 1 mA, VGS = 0 V 650 V IDSS Zero gate voltage drain current VDS = 650 V 1 µA VDS = 650 V, TC=125 °C (1), VGS = 0 V 100 µA IGSS Gate-body leakage current VGS = ± 25 V, VDS = 0 ± 100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 3 4 5 V RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 5 A 0.335 0.375 Ω Notes: (1)Defined by design, not subject to production test. Table 5: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V - 816 - pF Coss Output capacitance - 23 - pF Crss Reverse transfer capacitance - 2.6 - pF Co(tr)(1) Equivalent capacitance time related VDS = 0 to 520 V, VGS = 0 V - 70 - pF Co(er)(2) Equivalent capacitance energy related - 21 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 5 - Ω Qg Total gate charge VDD = 520 V, ID = 5.5 A, VGS = 10 V (see Figure 16: "Test circuit for gate charge behavior") - 22 - nC Qgs Gate-source charge - 5.5 - nC Qgd Gate-drain charge - 11 - nC Notes: (1)Coss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80 % VDSS. (2)Coss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80 % VDSS.

Table 6: Switching times Symbol Parameter Test conditions Min. Typ. Max Unit td(V) Voltage delay time VDD = 400 V, ID = 7 A, RG = 4.7 Ω, VGS = 10 V (see Figure 17: "Test circuit for inductive load switching and diode recovery times" and Figure 20: "Switching time waveform") - 30 - ns tr(V) Voltage rise time - 8 - ns tf(I) Current fall time - 11 - ns tc(off) Crossing time - 12.5 - ns Table 7: Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current 10 A ISDM(1) Source-drain current (pulsed) 40 A VSD(2) Forward on voltage ISD = 10 A, VGS = 0 - 1.5 V trr Reverse recovery time ISD = 10 A, di/dt = 100 A/µs VDD = 100 V (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 244 ns Qrr Reverse recovery charge - 2.35 µC IRRM Reverse recovery current - 19.2 A trr Reverse recovery time ISD = 10 A, di/dt = 100 A/µs VDD = 100 V, Tj = 150 °C (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 308 ns Qrr Reverse recovery charge - 2.93 µC IRRM Reverse recovery current - 19 A Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5 %.

2.1 Electrical characteristics (curves)

Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Static drain-source on-resistance Figure 7: Gate charge vs gate-source voltage

Figure 14: Switching energy vs gate resistance(1) Notes: (1)Eon including reverse recovery of a SiC diode.

3 Test circuits

Figure 15: Test circuit for resistive load switching times Figure 16: Test circuit for gate charge behavior Figure 17: Test circuit for inductive load switching and diode recovery times Figure 18: Unclamped inductive load test circuit Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform AM05540v2_for_M5

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

4.1 Power Flat™ 5x6 HV package information

Figure 21: PowerFLAT™ 5x6 HV package outline 8368143_Rev_3

Table 8: PowerFLAT™ 5x6 HV mechanical data Dim. mm Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 0.25 b 0.30 0.50 D 5.10 5.20 5.30 E 6.05 6.15 6.25 E2 3.10 3.20 3.30 D2 4.30 4.40 4.50 e 1.27 L 0.50 0.55 0.60 K 1.90 2.00 2.10 Figure 22: PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm) 8368143_Rev_3_footprint

4.2 Power Flat™ 5x6 HV packing information

Figure 23: PowerFLAT™ 5x6 tape (dimensions are in mm) Figure 24: PowerFLAT™ 5x6 package orientation in carrier tape

Figure 25: PowerFLAT™ 5x6 reel

5 Revision history

Table 9: Document revision history Date Revision Changes 26-Jun-2013 1 First release 05-Dec-2016 2 Updated title, features and description in cover page. Updated Figure 1: "Internal schematic diagram", Table 2: "Absolute maximum ratings" and Section 4: "Package information". Minor text changes.