STL135N8F7AG STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 14
Technical content
Datasheet sections
- 1 Electrical ratings
- 2 Electrical characteristics
- 2.1 Electrical characteristics (curves)
- 3 Test circuits
- 4 Package information
- 4.1 PowerFLAT™ 5x6 WF type C package information
- 4.2 PowerFLAT™ 5x6 WF packing information
- 5 Revision history
Features
Order code VDS RDS(on) max. ID PTOT STL135N8F7AG 80 V 3.6 mΩ 130 A 135 W Designed for automotive applications and AEC-Q101 qualified Among the lowest RDS(on) on the market Excellent figure of merit (FoM) Low Crss/Ciss ratio for EMI immunity High avalanche ruggedness Wettable flank package
Applications
Switching applications
Description
This N-channel Power MOSFET utilizes STripFET™ F7 technology with an enhanced trench gate structure that results in very low on- state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. Table 1: Device summary Order code Marking Package Packing STL135N8F7AG 135N8F7 PowerFLAT™ 5x6 Tape and reel
1 Electrical ratings
Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 80 V VGS Gate-source voltage ±20 V ID(1) Drain current (continuous) at Tcase = 25 °C 130 A Drain current (continuous) at Tcase = 100 °C 93 IDM(1)(2) Drain current (pulsed) 560 A ID(3) Drain current (continuous) at Tpcb = 25 °C 26 A Drain current (continuous) at Tpcb = 100 °C 19 IDM(2)(3) Drain current (pulsed) 104 A PTOT(1) Total dissipation at Tcase = 25 °C 135 W PTOT(3) Total dissipation at Tpcb = 25 °C 4.8 W EAS(4) Single pulse avalanche energy 1.2 J Tstg Storage temperature range -55 to 175 °C Tj Operating junction temperature range Notes: (1) This value is rated according to Rthj-c. (2) Pulse width is limited by safe operating area. (3) This value is rated according to Rthj-pcb (4) Starting Tj = 25 °C, ID = 13 A, VDD = 50 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-pcb(1) Thermal resistance junction-pcb 31.3 °C/W Rthj-case Thermal resistance junction-case 1.1 Notes: (1) When mounted on a 1-inch² FR-4 board, 2oz Cu, t < 10 s
2 Electrical characteristics
(Tcase = 25 °C unless otherwise specified) Table 4: Static Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 250 µA 80 V IDSS Zero gate voltage drain current VGS = 0 V, VDS = 80 V µA VGS = 0 V, VDS = 80 V, Tj = 125 °C IGSS Gate-body leakage current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2.5 4.5 V RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 13 A 3.15 3.6 mΩ Table 5: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance VDS = 40 V, f = 1 MHz, VGS = 0 V - 6800 - pF Coss Output capacitance - 1350 - Crss Reverse transfer capacitance - 95 - Qg Total gate charge VDD = 40 V, ID = 26 A, VGS = 10 V (see Figure 14: "Test circuit for gate charge behavior") - 103 - nC Qgs Gate-source charge - 35 - Qgd Gate-drain charge - 28 - Table 6: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 40 V, ID = 13 A RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Test circuit for resistive load switching times" and Figure 18: "Switching time waveform") - 30 - ns tr Rise time - 28 - td(off) Turn-off delay time - 73 - tf Fall time - 30 -
Table 7: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current 26 A ISDM(1) Source-drain current (pulsed) 104 A VSD(2) Forward on voltage VGS = 0 V, ISD = 26 A - 1.2 V trr Reverse recovery time ISD = 26 A, di/dt = 100 A/µs, VDD = 64 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 47 ns Qrr Reverse recovery charge - 66 nC IRRM Reverse recovery current - 2.8 A Notes: (1) Pulse width is limited by safe operating area. (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%.
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance
Test circuits STL135N8F7AG
3 Test circuits
Figure 13: Test circuit for resistive load switching times Figure 14: Test circuit for gate charge behavior Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform Figure 18: Switching time waveform
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
4.1 PowerFLAT™ 5x6 WF type C package information
Figure 19: PowerFLAT™ 5x6 WF type C package outline 8231817_WF_typeC_r12
Table 8: PowerFLAT™ 5x6 WF type C mechanical data Dim. mm Min. Typ. Max. A 0.80 1.00 A1 0.02 0.05 0.25 b 0.30 0.50 C 5.80 6.00 6.20 D 5.00 5.20 5.40 D2 4.15 4.45 D3 4.05 4.20 4.35 D4 4.80 5.0 5.20 D5 0.25 0.4 0.55 D6 0.15 0.3 0.45 e 1.27 E 6.20 6.40 6.60 E2 3.50 3.70 E3 2.35 2.55 E4 0.40 0.60 E5 0.08 0.28 E6 0.2 0.325 0.450 E7 0.85 1.00 1.15 K 1.05 1.35 L 0.90 1.00 1.10 L1 0.175 0.275 0.375 θ 0° 12°
Figure 20: PowerFLAT™ 5x6 recommended footprint (dimensions are in mm)
4.2 PowerFLAT™ 5x6 WF packing information
Figure 21: PowerFLAT™ 5x6 WF tape 8231817_FOOTPRINT_Rev_12
5 Revision history
Table 9: Document revision history Date Revision Changes 07-Sep-2015 1 First release. 15-Sep-2015 2 Minor text edits. On cover page: - updated Title and Features 26-Jan-2016 3 Updated Table 2: "Absolute maximum ratings" and Section 4.1: "PowerFLAT™ 5x6 WF type C package information".