STL10N60M2 STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 16

Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuits
  • 4 Package mechanical data
  • 5 Packaging mechanical data
  • 6 Revision history

Features

  • Extremely low gate charge
  • Lower RDS(on) x area vs previous generation
  • Low gate input resistance
  • 100% avalanche tested
  • Zener-protected

Applications

  • Switching applications

Description

This device is an N-channel Power MOSFET developed using a new generation of MDmesh™ technology: MDmesh II Plus™ low Qg. This revolutionary Power MOSFET associates a vertical structure to the company's strip layout to yield one of the world's lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. AM15540v3 5678 12 34 Top View D(5, 6, 7, 8) G(4) S(1, 2, 3) PowerFLAT™ 5x6 HV Order code VDS @ TJmax RDS(on) max I D STL10N60M2 650 V 0.660 Ω 5.5 A Table 1. Device summary

1 Electrical ratings

Table 2. Absolute maximum ratings

  1. The value is limited by package
  2. Pulse width limited by safe operating area
  3. I SD ≤ 5.5 A, di/dt ≤ 400 A/µs, VDSpeak ≤ V(BR)DSS, VDD = 80% V(BR)DSS

Table 3. Thermal data

  1. When mounted on 1inch² FR-4 board, 2 oz Cu

2 Electrical characteristics

Table 4. On /off states Table 5. Dynamic

  1. C oss eq. is defined as a constant equivalent capac itance giving the same charging time as C oss when VDS

increases from 0 to 80% VDS. Table 6. Switching times

Table 7. Source drain diode

  1. Pulse width limited by safe operating area.
  2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Gate charge vs gate-source voltage Figure 7. Static drain-source on-resistance

0 Qg(nC)

Figure 8. Capacitance variations Figure 9. Output capacitance stored energy Figure 10. Normalized gate threshold voltage vs Figure 11. Normalized on-resistance vs Figure 12. Normalized V(BR)DSS vs temperature Figure 13. Source-drain diode forward

0 VDS(V)

2.3 VGS= 10 V

3 Test circuits

Figure 14. Switching times test circuit for Figure 15. Gate charge test circuit Figure 16. Test circuit for inductive load Figure 17. Unclamped inductive load test circuit Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

Figure 20. PowerFLAT™ 5x6 HV drawing

Table 8. PowerFLAT™ 5x6 HV mechanical data

Figure 21. PowerFLAT™ 5x6 HV recommended footprint (dimensions are in mm)

5 Packaging mechanical data

Figure 22. PowerFLAT™ 5x6 tape (a) Figure 23. PowerFLAT™ 5x6 package orientation in carrier tape. a. All dimensions are in millimeters. hole to centerline of pocket.

Figure 24. PowerFLAT™ 5x6 reel

6 Revision history

Table 9. Document revision history 28-Oct-2013 1 First release. 26-Mar-2014 2 Document status promoted from preliminary to production data.