STB14NM50N STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuits
  • 4 Package mechanical data
  • 5 Packaging mechanical data
  • 6 Revision history

Features

■ 100% avalanche tested ■ Low input capacitance and gate charge ■ Low gate input resistance

Applications

■ Switching applications

Description

These devices are N-channel Power MOSFET developed using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. Figure 1. Internal schematic diagram Table 1. Device summary

1 Electrical ratings

Table 2. Absolute maximum ratings

  1. Limited by maximum junction temperature
  2. Pulse width limited by safe operating area
  3. I SD ≤ 12 A, di/dt ≤ 400 A/s,VDS peak ≤ V(BR)DSS, VDD = 80% V(BR)DSS

Table 3. Thermal data

  1. When mounted on 1inch² FR-4 board, 2 oz Cu

Table 4. Avalanche data

2 Electrical characteristics

Table 5. On /off states Table 6. Dynamic

  1. C oss eq. is defined as a constant equivalent capac itance giving the same charging time as C oss when VDS

Table 7. Switching times

Table 8. Source drain diode

  1. Pulse width limited by safe operating area
  2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area for D²PAK, Figure 3. Thermal impedance for D²PAK, Figure 4. Safe operating area for DPAK Figure 5. Thermal impedance for DPAK Figure 6. Safe operating area for TO-220FP Figure 7. Thermal impedance for TO-220FP

Figure 8. Output characteristics Figure 9. Transfer characteristics Figure 10. Normalized B VDSS vs temperature Figure 11. Static drain-source on-resistance Figure 12. Capacitance variations Figure 13. Gate charge vs gate-source voltage

0.300 VGS=10V

3 Test circuits

Figure 17. Switching times test circuit for Figure 18. Gate charge test circuit Figure 19. Test circuit for inductive load Figure 20. Unclamped inductive load test Figure 21. Unclamped inductive waveform Figure 22. Switching time waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

Table 9. D²PAK (TO-263) mechanical data

Table 10. DPAK (TO-252) mechanical data

Figure 25. DPAK (TO-252) drawing

Figure 26. DPAK footprint (b)

Table 11. TO-220FP mechanical data

Figure 27. TO-220FP drawing

Table 12. I²PAK (TO-262) mechanical data

Figure 28. I²PAK (TO-262) drawing

Table 13. TO-220 type A mechanical data

Figure 29. TO-220 type A drawing

5 Packaging mechanical data

Table 14. D²PAK (TO-263) tape and reel mechanical data

Table 15. DPAK (TO-252) tape and reel mechanical data

6 Revision history

Table 16. Document revision history 26-Nov-2009 1 First release. 02-Dec-2009 2 Inserted table footnote Table 3: Thermal data. 22-Jul-2010 3 Document status promoted from preliminary data to datasheet. 06-Apr-2011 4 Updated E AS in Table 2. data, Table 5: On /off states. Updated Section 4: Package mechanical data.