STI10NM60N STMICROELECTRONICS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 12

Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuits
  • 4 Package information
  • 4.1 I 2PAK package information
  • 5 Revision history

Features

  • 100% avalanche tested
  • Low input capacitance and gate charge
  • Low gate input resistance

Applications

  • Switching applications

Description

This device is an N-channel Power MOSFET developed using the second generation of MDmesh™ technology. This revolutionary Power MOSFET associates a vertical structure to the company’s strip layout to yield one of the world’s lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. 1 2 3 TAB I2PAK $0Y 7$% Order code VDS @TJmax RDS(on) max. ID PTOT STI10NM60N 650 V < 0.55 Ω 10 A 70 W Table 1. Device summary

1 Electrical ratings

Table 2. Absolute maximum ratings

  1. Pulse width limited by safe operating area.

Table 3. Thermal data Table 4. Avalanche characteristics

2 Electrical characteristics

Table 5. On /off states Table 6. Dynamic

  1. C oss eq. time related is defined as a constant equivalent capacitance giving the same charging time as Coss

when VDS increases from 0 to 80% VDSS.

Table 7. Switching times Table 8. Source-drain diode

  1. Pulse width limited by safe operating area.
  2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area for I²PAK Figure 3. Thermal impedance for I²PAK Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Normalized VDS vs. temperature Figure 7. Static drain-source on-resistance

Figure 8. Gate charge vs. gate-source voltage Figure 9. Capacitance variations Figure 10. Normalized gate threshold voltage Figure 11. Normalized on-resistance vs.

1.9 ID=4A

3 Test circuits

Figure 12. Switching times test circuit for Figure 13. Gate charge test circuit Figure 14. Test circuit for inductive load Figure 15. Unclamped inductive load test circuit Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform

4 Package information

specifications, grade definitions and product status are available at: www.st.com.

4.1 I 2PAK package information

Figure 18. I2PAK (TO-262) package outline

Table 9. I²PAK (TO-262) package mechanical data

5 Revision history

Table 10. Document revision history 18-Jul-2013 7 Updated Section 4: Package mechanical data. STU10NM60N have been moved to a separate datasheet.