STGAP2S STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 23
Technical content
Datasheet sections
- 1 Block diagram
- 2 Pin description and connection diagram
- 3 Electrical data
- 3.1 Absolute maximum ratings
- 3.2 Thermal data
- 3.3 Recommended operating conditions
- 4 Electrical characteristics
- 5 Functional description
- 5.1 Gate driving power supply and UVLO
- 5.2 Power up, power down and 'safe state'
- 5.3 Control inputs
- 5.4 Miller clamp function
- 5.5 Watchdog
- 5.6 Thermal shutdown protection
- 5.7 Standby function
- 6 Typical application diagram
- 7 Layout
- 7.1 Layout guidelines and considerations
- 7.2 Layout example
- 8 Testing and characterization information
- 9 Package information
- 10 Suggested land pattern
- 11 Ordering information
Features
- High voltage rail up to 1700 V
- Driver current capability: 4 A sink/source @25°C
- dV/dt transient immunity ±100 V/ns in full temperature range
- Overall input-output propagation delay: 75 ns
- Separate sink and source option for easy gate driving configuration
- 4 A Miller CLAMP dedicated pin option
- UVLO function
- Gate driving voltage up to 26 V
- 3.3 V, 5 V TTL/CMOS inputs with hysteresis
- Temperature shut-down protection
- Standby function
- Narrow body SO8
- UL 1577 recognized Application
- Motor driver for home appliances, factory automation, industrial drives and fans.
- 600/1200 V inverters
- Battery chargers
- Induction heating
- Welding
- UPS
- Power supply units
- DC-DC converters
- Power Factor Correction
Description
The STGAP2S is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry. The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device is available in two different configurations. The configuration with separated output pins allows to independently optimize turn-on and turn-off by using dedicated gate resistors. The configuration featuring single output pin and Miller CLAMP function prevents gate spikes during fast commutations in half-bridge topologies. Both configurations provide high flexibility and bill of material reduction for external components. The device integrates UVLO and thermal shutdown protection functions to facilitate the design of highly reliable systems. Dual input pins allow the selection of signal polarity control and implementation of HW interlocking protection to avoid cross- conduction in case of controller malfunction. The input to output propagation delay is less than 75 ns, which delivers high PWM control accuracy. A standby mode is available to reduce idle power consumption. Product status link STGAP2S Product label Galvanically isolated 4 A single gate driver STGAP2S Datasheet DS12541 - Rev 3 - July 2022 For further information contact your local STMicroelectronics sales office.
1 Block diagram
Figure 1. Block diagram - separated outputs option Figure 2. Block diagram - single output and Miller clamp option
2 Pin description and connection diagram
Figure 3. Pin connection (top view), separated outputs option Figure 4. Pin connection (top view), single output and Miller clamp option Table 1. Pin description 1 1 VDD Power supply Driver logic supply voltage. 2 2 IN+ Logic input Driver logic input, active high. 4 4 GND Power supply Driver logic ground. 5 5 VH Power supply Gate driving positive voltage supply.
- 6 GOUT Analog output Sink/source output.
- 7 CLAMP Analog output Active Miller clamp.
6 - GON Analog output Source output. 7 - GOFF Analog output Sink output. 8 8 GNDISO Power supply Gate driving Isolated ground.
3 Electrical data
3.1 Absolute maximum ratings
Table 2. Absolute maximum ratings
3.2 Thermal data
Table 3. Thermal data
3.3 Recommended operating conditions
Table 4. Recommended operating conditions
- Actual limit depends on power dissipation and T J.
4 Electrical characteristics
Table 5. Electrical characteristics
Electrical characteristics
Symbol Pin Parameter Test conditions Min. Typ. Max. Unit RGON - Source RDS_ON IGON =100 mA - 1.125 1.5 Ω IGOFF - Sink short-circuit current TJ =25 °C - 4 - A VGOFFL - Sink output low level voltage IGOFF =100 mA - 96 120 mV RGOFF - Sink RDS_ON IGOFF =100 mA - 0.96 1.2 Ω Miller Clampfunction (STGAP2SC only) VCLAMPth - CLAMP voltage threshold VCLAMP vs. GNDISO 1.3 2 2.6 V ICLAMP - CLAMP short-circuit current VCLAMP =15 V TJ =25 °C A- 4 - 2 - 5 VCLAMP_L - CLAMP low level output voltage ICLAMP =100 mA - 96 115 mV RCLAMP - CLAMP RDS_ON ICLAMP =100 mA - 0.96 1.15 Ω Overtemperature protection TSD - Shutdown temperature - 170 - - °C Thys - Temperature hysteresis - - 20 - °C Standby tSTBY - Standby time See Section 5.3 200 280 500 µs tWUP - Wake-up time See Section 5.3 10 20 35 µs tawake - Wake-up delay See Section 5.3 90 140 200 µs tstbyfilt - Standby filter See Section 5.3 200 280 800 ns 1. Characterization data, not tested in production. Table 6. Isolation related package specifications
Table 7. Isolation characteristics
2720 VPEAKVPR = 2720, tm = 10 s
3200 VPEAKVPR = 3200, tm = 1 s
Table 8. UL 1577 isolation voltage ratings Recognized under the UL 1577 Component Recognition Program - file number E362869.
5 Functional description
5.1 Gate driving power supply and UVLO
allows implementation of either unipolar or bipolar gate driving. Figure 5. Power supply configuration for unipolar and bipolar gate driving different values in parallel provides both local storage for impulsive current supply and high-frequency filtering. with value in the range between 1 µF and 10 µF should be placed close to it.
5.2 Power up, power down and 'safe state'
- GOFF = ON state
- GON = high impedance
- CLAMP = ON state (for STGAP2SC) Such conditions are maintained at power up of the isolated side (VH < VHon) and during whole device power down phase (VH < VHoff), regardless of the value of the input pins. The device integrates a structure which clamps the driver output to a voltage not higher than SafeClp when VH voltage is not high enough to actively turn the internal GOFF MOSFET on. If VH positive supply pin is floating or not supplied the GOFF pin is therefore clamped to a voltage smaller than SafeClp. If the supply voltage VDD of the control section of the device is not supplied, the output is put in safestate, and remains in such condition until the VDD voltage returns within operative conditions. After power-up of both isolated and low voltage side the device output state depends on the input pins' status. STGAP2S Functional description DS12541 - Rev 3 page 8/23
5.3 Control inputs
Table 9. Inputs truth table (applicable when device is not in UVLO or “safe state”) possibly present in the application from generating unwanted commutations.
5.4 Miller clamp function
between the switch gate and the GNDISO pin.
5.5 Watchdog
state” until communication link is properly established again.
5.6 Thermal shutdown protection
temperature is lower than TSD - Thys.
5.7 Standby function
IQHSBY respectively, and the output remains in 'safe state' (the output is actively forced low). standby the inputs can change from the “stand-by” value. than tstbyfilt , and then in the “standby” value for a time t such that tWUP<t < tSTBY. inputs state after a time tawake. Figure 6. Standby state sequences
6 Typical application diagram
Figure 7. Typical application diagram - separated outputs Figure 8. Typical application diagram - separated outputs and negative gate driving
7 Layout
7.1 Layout guidelines and considerations
- SMT ceramic capacitors (or different types of low-ESR and low-ESL capacitors) must be placed close to each supply rail pins. A 100 nF capacitor must be placed between VDD and GND and between VH and GNDISO, as close as possible to device pins, in order to filter high-frequency noise and spikes. In order to provide local storage for pulsed current a second capacitor with value in the range between 1 µF and 10 µF should also be placed close to the supply pins.
- As a good practice it is suggested to add filtering capacitors close to logic inputs of the device (IN+, IN-), in particular for fast switching or noisy applications.
- The power transistors must be placed as close as possible to the gate driver, so to minimize the gate loop area and inductance that might bring to noise or ringing.
- To avoid degradation of the isolation between the primary and secondary side of the driver, there should not be any trace or conductive area below the driver.
- If the system has multiple layers, it is recommended to connect the VH and GNDISO pins to internal ground or power planes through multiple vias of adequate size. These vias should be located close to the IC pins to maximize thermal conductivity.
7.2 Layout example
Figure 11 . It is recommended to follow this example for proper positioning and connection of filtering capacitors. Figure 11. Layer traces and copper
8 Testing and characterization information
Figure 12. Timings definition Figure 13. CMTI test circuit
9 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
9.1 SO-8 package information
Figure 14. SO-8 package outline
Package information
DS12541 - Rev 3 page 15/23
Table 10. SO-8 package mechanical data
10 Suggested land pattern
Figure 15. SO-8 suggested land pattern
Table 11. Device summary
Ordering information
DS12541 - Rev 3 page 18/23
Revision history
Table 12. Document revision history 06-Jun-2018 1 Initial release.
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