STGAP1AS STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Block diagram
- 2 Pin connection
- 3 Electrical data
- 3.1 Absolute maximum ratings
- 3.2 Thermal data
- 3.3 Recommended operating conditions
- 4 Electrical characteristi cs
- 4.1 AC operation
- 4.2 DC operation
- 5 Isolation
- 6 Logic supply management
- 6.1 Low voltage section voltage regulator
- 6.2 High voltage section voltage regulator
- 6.3 Power-up, power-down and “safe state”
- 6.4 Standby function
- 7 Functional description
- 7.1 Inputs and outputs
- 7.2 Deadtime and interlocking
- 7.3 Hardware RESET
- 7.4 Power supply UVLO and OVLO
- 7.5 Thermal warning and shutdown protection
- 7.6 Desaturation protection
- 7.8 SENSE overcurrent protection
- 7.9 Miller clamp function
- 7.10.1 Always
Datasheet sections
- 10 Typical application diagram
- 11 Package information
- 11.1 SO24W package information
- 12 Ordering information
- 13 Revision history
Features
Qualified for automotive applications according to AEC-Q100 High voltage rail up to 1500 V Driver current capability: 5 A sink/source current at 25 °C dV/dt transient immunity ± 50 V/ns in full temperature range Overall input/output propagation delay: 100 ns Separate sink and source for easy gate driving configuration Negative gate drive ability Active Miller clamp Desaturation detection SENSE input VCE active clamping Output 2-level turn-off Diagnostic status output UVLO and OVLO functions Programmable input deglitch filter Asynchronous stop command Programmable deadtime, with violation error SPI interface for parameters programming Temperature warning and shutdown protection Self-diagnostic routines for protection features Full effective fault protection
Applications
600/1200 V inverters Inverters for EV\\HEV EV charging stations Industrial drives UPS equipment DC/DC converters Solar inverters
Description
The STGAP1AS gapDRIVE™ is a galvanically isolated single gate driver for N-channel MOSFETs and IGBTs with advanced protection, configuration and diagnostic features. The architecture of the STGAP1AS isolates the channel from the control and the low voltage interface circuitry through true galvanic isolation. The gate driver is characterized by 5 A capability, making the device also suitable for high power inverter applications such as motor drivers in hybrid and electric vehicles and in industrial drives. The output driver section provides a rail- to-rail output with the possibility to use a negative gate driver supply. The input to output propagation delay results contained within 100 ns, providing high PWM control accuracy. Protection functions such as the Miller clamp, desaturation detection, dedicated sense pin for overcurrent detection, output 2-level turn-off, VCE overvoltage protection, UVLO and OVLO are included to easily design high reliability systems. Open drain diagnostic outputs are present and detailed device conditions can be monitored through the SPI. Each function's parameter can be programmed via the SPI, making the device very flexible and allowing it to fit in a wide range of applications. Separate sink and source outputs provide high flexibility and bill of material reduction for external components. SO24W
Table 5. AC operation electrical characteristics Table 6. DC operation electrical characteristics Table 27. SD
1 Block diagram
Figure 1. Block diagram
2 Pin connection
Figure 2. Pin connection (top view) Table 1. Pin description
7 VDD Power supply Power supply for low voltage section and
11 SD Logic input Shutdown input (active low)
9 IN+ Logic input Gate command input
8 IN-/DIAG2 Logic input/open drain output Gate command input /open drain diagnostic
10 DIAG1 Open drain output Open drain diagnostic output
5 CK Logic input SPI clock
3 SDI Logic input SPI serial data input
2 SDO Logic output SPI serial data output
19 VCECLAMP Analog input V
18 DESAT Analog input/output Desaturation protection
15 VREGISO Power supply Internal regul ator output pin for decoupling
17 VH Power supply Positive power supply for high voltage
20 GON Analog output Gate source output
21 GOFF Analog output Gate sink output
22 CLAMP Analog output Miller clamp
13 GNDISO Ground High voltage section (isolated) ground
16 SENSE Analog input Sense input for overcurrent protection
24 ASC Analog input Asynchronous stop command
Table 1. Pin description (continued)
3 Electrical data
3.1 Absolute maximum ratings
Table 2. Absolute maximum ratings
3.2 Thermal data
3.3 Recommended operating conditions
Table 3. Thermal data
- The STGAP1AS mounted on the EVALSTGAP1AS rev 2.0 board (two-layer FR4 PCB).
Table 4. Recommended operating conditions
- When UVLO is enabled this value is VH on,max.
- When UVLO is enabled this value is VL on,min.
- When VDD is connected to the VREG pin (refer to Section 6 on page 22).
- Actual limit depends on powe r dissipation constraints.
4 Electrical characteristics
4.1 AC operation
21 Deadtime
4.2 DC operation
22 GOFF active clamp
- Characterization data, not tested in production.
- The actual waiting time depends on the gate charge size.
- See Table 22 on page 52 and Section 9.1.3 on page 50.
5 Isolation
Table 7. Isolation and safety-related specifications Table 8. IEC 60747-5-2 isolation characteristics
2400 V PEAK
2815 V PEAK
- For three-phase systems the values in t he table refer to the line-to-neutral voltage.
Table 9. Isolation voltage as per UL 1577
6 Logic supply management
6.1 Low voltage sectio n voltage regulator
Figure 3. Low voltage section 3.3 V voltage regulator Undervoltage protection is available on the VDD supply pin (disabled by default). Overvoltage protection is available on the VDD supply pin.
6.2 High voltage section voltage regulator
the 3.3 V logic core supply voltage from an external supply voltage connected to the VH pin. Figure 4. High voltage section 3.3 V voltage regulator causes the logic reset, the REGERRR bit in the STATUS2 register is set high.
6.3 Power-up, power-do wn and “safe state”
and VL > VLoff), whatever the value of the input pins. set to zero as soon as the isolated side power-up is completed.
Logic supply management STGAP1AS
6.4 Standby function
The device can be put in standby mode to reduce the power consumption on VDD via the SPI command “Sleep” (refer to Section 9.1.5 on page 51). The proper sequence is: 1. Pull-down the SD pin: the driver section will be put in “safe state” 2. Send a Sleep command 3. After a t sleep time the device can be considered actually in the sleep mode. To exit from the sleep mode it is necessary to set the SD high for at least tawake while keeping IN+ low. After a tawake time the device can accept new commands and the REGERRR bit is set to indicate that the device needs to be reprogrammed. If the SD pin is raised while tsleep is still not expired, the device returns to the operation mode within a tawake time.
7 Functional description
7.1 Inputs and outputs
IN-/DIAG2: driver input or diagnostic open drain output. device is designed to work with VDD supply voltages of 5 V or 3.3 V. negative, shorter than the programmed tdeglitch value is neglected by internal logic. Deglitch time can be programmed as listed in Table 30 on page 54. out both positive and negative pulses at the IN+, IN- and SD pins. Table 10. Inputs true table (device NOT in “safe state”)
- The IN-/DIAG2 pin is used as the open drain output for diagnostic signaling (refer to Section 7.11 on page
7.2 Deadtime and interlocking
Figure 5. HW cross conduction prevention in half-bridge configuration with two can be programmed through the SPI interface as shown in Table 29 on page 54. same leg is at the beginning of a turn-off (refer to Figure 6). controller tries to force the turn-on (inputs set to < IN- = '0' and IN+ = '1' >). soon as a turn-on command is present at the input pins, and no extra delay is added.
Figure 6. Transitions causing the DT generation
STGAP1AS Functional description
7.3 Hardware RESET
The device can be reset by forcing the VREG pin to ground through an external switch. The internal regulator is designed to stand this condition. The maximum current required to force the VREG pin to ground is indicated by the parameter I REG.
7.4 Power supply UVLO and OVLO
Undervoltage protection is available on both VH and VL supply pins. The turn-on threshold can be programmed through the SPI writing the CFG4 register. A fixed 1 V hysteresis will set the respective turn-off threshold. Both UVLO protections can be independently disabled by setting the proper value in the CFG4 register. When VH voltage goes below the VHoff threshold the output buffer goes in “safe state” and the UVLOH status flag is forced high. If the UVLOlatch bit in the CFG4 register is set low (default), the UVLOH status flag is released when VH voltage reaches the VHon threshold and the device returns to normal operation. Otherwise the UVLOH flag is latched and the device remains in “safe state” until the VH voltage reaches the VHon threshold and the flag is released. See Section 7.11 on page 35 for indication on how the failure flags can be released. When VL voltage goes over the VLoff threshold the output buffer goes in “safe state” and the UVLOL status flag is forced high. If the UVLOlatch bit in the CFG4 register is set low (default), the UVLOL status flag is released when VL voltage goes below the VLon threshold and the device returns to normal operation. Otherwise the UVLOL flag is latched and the device remains in “safe state” until the VL voltage goes below the VLon threshold and the flag is released. See Section 7.11 for indication on how the failure flags can be released. Overvoltage protection is available on both VH and VL supply pins. Both OVLO protections can be disabled by setting the proper value in the CFG4 register. When the VH voltage goes over the OVVHoff threshold the output buffer goes in “safe state” and the OVLOH status flag is forced high. The OVLOH flag is latched and the device remains in “safe state” until VH voltage goes below the overvoltage threshold and the flag is released. See Section 7.11 for indication on how the failure flags can be released. When VL voltage goes over the OVVLoff threshold the output buffer goes in “safe state” and the OVLOL status flag is forced high. The OVLOL flag is latched and the device remains in “safe state” until VH voltage goes below the overvoltage threshold and the flag is released. See Section 7.11 for indication on how the failure flags can be released.
Functional description STGAP1AS
7.5 Thermal warning and shutdown protection
The device provides a thermal warning and a thermal shutdown protection. When junction temperature reaches the TWN temperature threshold the TWN flag in the STATUS1 register is forced high. The TWN flag is released as soon as the junction temperature is lower than TWN - Thys. When junction temperature reaches the TSD temperature threshold, the device is forced in “safe state” and the TSD flag in the STATUS1 register is forced high. The device operation is restored and the TSD flag is released as soon as the junction temperature is lower than T SD - Thys.
7.6 Desaturation protection
This feature allows implementing an overload protection for the IGBT. The DESAT pin monitors the VCE voltage of the IGBT while it is on, and if the protection threshold is reached, the IGBT is turned off. When the IGBT is off (GOFF output is activated) the DESAT pin is kept low internally and the external blanking capacitor connected to the DESAT pin is discharged (the internal current generator is fully switched off and the switch between DESAT and GNDISO pins is turned on). When the GON output is activated the switch between DESAT and GNDISO pins is turned off and an internal programmable current generator (IDESAT) starts charging the external blanking capacitor after a fixed blanking time tBLK. If a desaturation event occurs the VCE voltage increases and the voltage at the DESAT pin reaches the desaturation threshold VDESATth: the DESAT comparator output is set, the device is forced in “safe state” and the DESAT flag is forced high and latched. The DESAT comparator is not active when the external IGBT is off or after desaturation detection (see Figure 11). Both the VDESATth threshold and the IDESAT blanking current are programmable through the SPI.
Figure 11. DESAT protection timing diagram shorter than tDESfilter value shall not trigger the protection.
7.7 V CE active clamping protection
collector (or drain) within safe limits. reached and the IC actively slows down the power switch turn-off to keep a safe condition. through the TVS, thus preventing it from operating in overstressing conditions.
STGAP1AS Functional description
7.8 SENSE overcurrent protection
This function is suitable in applications in which it is possible to measure the load current through the use of a shunt resistor, or in applications that use IGBTs with the current sense pin available. The load current (or a fraction of it in case SenseFETs are used) is converted to voltage by an external shunt resistor and is fed to the SENSE pin (comparator input). When an overcurrent event occurs the sense voltage reaches the V SENSEth threshold, the device is forced in “safe state” and the SENSE status flag is forced high and latched. The VSENSEth threshold is programmable through the SPI (refer to Section 9.2.2 on page 55).
7.9 Miller clamp function
The Miller clamp function allows the control of the Miller current during the power stage switching in half-bridge configurations. When the external power transistor is in the OFF state, the driver operates to avoid the induced turn-on phenomenon that may occur when the other switch in the same leg is being turned on, due to the Cgc capacitance. During the turn-off period the gate of the external switch is monitored through the CLAMP pin. The CLAMP switch is activated when gate voltage goes below the voltage threshold VCLAMPth, thus creating a low impedance path between the switch gate and the VL pin. This function can be disabled setting low the CLAMP_EN bit in the CFG5 register (high by default). 7.10 2-level turn-off function If an overcurrent event happens, a large voltage overshoot exceeding VCE absolute ratings may occur across the power switch during the turn-off, due to the parasitic stray inductances. The 2-level turn-off function (2LTO) allows the reduction of the stressing overvoltage experienced by the power component in overcurrent condition by switching off the external power in two phases. In the first phase the GOFF voltage is actively forced to a programmable value V2LTOth; after a programmable delay t2LTOtime the GOFF is forced to VL to complete the gate turn-off. This allows to slow down the critical part of the turn-off transient, that may induce the overvoltage spikes. The voltage level V2LTOth and duration t2LTOtime of the intermediate off-level are programmable through the SPI. It is possible to program when this feature takes place, refer to the following paragraphs.
7.10.1 Always
The 2LTO is performed at each turn-off transition (2LTO_EN = '1'). represents the condition: < IN+ = 'H' and IN- = 'L' >. t2LTOtime will determine a delay in the turn-on equal to t2LTOtime (see Figure 14). Figure 14. Example of short turn-on pulses when 2LTO occurs at each cycle Figure 15. Example of short turn-off pulse when 2LTO occurs at each cycle state” generates a driver switch off performing a 2LTO sequence.
7.10.2 Fault
Section 7.11 for indication on how the failure flags can be released.
Figure 16. Example of operation with 2LTO in “Fault” mode
7.10.3 Never
7.11 Failure management
bit as described in Section 7.1 on page 25. information as listed in respective paragraphs. kept high even if the triggering condition is expired. of the command’s execution time. cleared by direct intervention of the MCU.
Functional description STGAP1AS All flags in the StatusRegisters are released after a tdesCS time following the rise of the SPI CS. Forcing low the SD pin for at least trelease All the flags are released at the rising edge of the SD. This mode is enabled at device’s power-on, but it can be disabled by setting the SD_FLAG configuration bit low during the configuration phase, and by doing this any possibility to clear a FLAG without direct intervention of the MCU is prevented. Even if the SD_FLAG is set high, status registers are not cleared after the rising edge of the SD if a configuration sequence is executed (StartConfig, StopConfig). This is done to avoid clearing errors that may have been generated during the configuration procedure. Using HW reset (see Section 7.3 on page 29) In this case the device behaves as after power-up sequence. In any case, if the failure condition is still present, the respective flag is not released. Selected failures force the device in “safe state”; the device remains in this state until the relative status flags are released. Refer to Table 49 on page 61, Table 51 on page 62 and Table 53 on page 63 for details. The possibility to clear status registers by setting the SD low allows operating the device also without using the SPI interface. In order to avoid an unintended clear of fault conditions it is recommended to disable this functionality by setting the SD_FLAG = '0'.
7.12 Asynchronous stop command
The ASC pin allows to turn-on the GON output acting directly on the isolated driver logic and regardless of the status of the input pins IN+, IN- and SD. This pin is active high. The status of this pin is mirrored in the ASC bit present in the STATUS2 register. The power supply of the isolated section must be present (VH > VHon). In case UVLO on VH is not enabled, ASC function works for VH values within the recommended operating values. This function works even if the VDD voltage is not available or is in UVLO condition. The priority of such command is lower than that of DESAT and SENSE pins, so the ASC command is ignored in case of a desaturation or overcurrent fault. After such events the gate can be turned on again with a low-to-high transition of the ASC pin, or by clearing the fault condition (see Section 7.11).
7.13 Watchdog and echo
The isolated side provides a watchdog function in order to identify when it is no more able to communicate with the LV side. In this case the driver is automatically forced in “safe state” and the REGERRR flag is set. When the LV side is in the standby mode, turned off or in hardware reset condition, the isolated side watchdog is still operative and the REGERRR flag is set. The low voltage side provides a watchdog function in order to identify when it is no more able to communicate with the isolated side. In this case the REGERRL flag is set and the device is forced in “safe state”.
STGAP1AS Functional description An echo function is implemented in order to check that input commands toward the gate are correctly propagated to the driver's output. In case something should prevent the correct propagation of the command, the driver is able to detect this condition and will start a new communication (echo) in order to set the desired output state. This process has typical duration of 4 µs.
7.14 Security check functions
The device allows verifying the gate and sense resistor connections and the functionality of SENSE and DESAT. This can be achieved through the following security checks: GON to gate path GOFF to gate path SENSE comparator SENSE resistor DESAT comparator The check modes are enabled through a dedicated configuration register TEST1 (refer to Section 9.2.9 on page 63) and thus require entering in configuration mode. Only one check mode at a time must be enabled. At the end of security check procedure, the TEST1 register must be set to 0x00 before running the device in normal mode. It is recommended to clear the status register with the ResetStatus command before and after each check. To prevent the SD from clearing the STATUS flags, set the SD_FLAG = '0' as described in Section 7.11.
7.14.1 GON to gate path check
The purpose of this security check is to verify the path integrity including the driver's GON output, the GON (turn-on) gate resistor, the power switch gate and the CLAMP pin (see Figure 17). To perform this test, the following procedure has to be followed: Set SD = low Send StartConfig command Set GONCHK = '1' Send StopConfig command Wait tGchk Read TSD flag –T S D = ' 0 ' → OK (VCLAMP > VGchk) –T S D = ' 1 ' → FAIL (VCLAMP < VGchk) Please note that during all the time the check is enabled the gate will be forced high (GON turned on) regardless the SD pin level. The user test routine has to take into account this behavior. In any case, when GONCHK = '1', the protections SENSE and DESAT, if enabled, will continue to operate protecting the power switch regardless the SD pin.
Functional description STGAP1AS
7.14.2 GOFF to gate path check
The purpose of this security check is to verify the path integrity including the driver's GOFF output, the GOFF (turn-off) gate resistor, the power switch gate and the CLAMP pin (see Figure 17). To perform this test, the following procedure has to be followed: Set SD = low Send StartConfig command Set GOFFCHK = '1' Send StopConfig command Wait tGchk + tGATE_GOFFchk Read DESAT flag – DESAT = '0' → OK (VCLAMP < VCLAMPth) – DESAT = '1' → FAIL (VCLAMP > VCLAMPth) During the check a small current IGOFFchk will be sourced from the CLAMP pin while GOFF is on keeping the gate low through the turn-off gate resistor. To ensure the check result, some applicative conditions have to be verified: – The bleeding resistor, sometimes present between the gate and source in the power switch, shall be higher than 8.2 k. – During the test, the power switch gate shall have the time to be charged up to VCLAMPth by IGOFFchk. In case no bleeding resistor is present, this time can be roughly computed as: tGATE_GOFFchk ≈ CGATE * (VCLAMPth - VL) / IGOFFchk If a bleeding resistor is present or an additional push-pull circuit has been added, the time has to be computed with the adequate corrective factors. If the check fails due to the lack of the GOFF resistor, the power switch gate will gradually rise up to VH with no protections of SENSE nor DESAT. The user test routine shall consider this behavior.
Figure 17. Gate paths check circuitry
7.14.3 SENSE comparator check
The purpose of this security check is to verify the functionality of the sense comparator. To enable this check, it is required to set SNSCHK = '1' and SENSE_EN = '1'. SENSE comparator operation is compromised. The SENSE fault generated by this test is latched and shall be cleared accordingly. Figure 18. SENSE comparator and resistor check circuitry
STGAP1AS Functional description
7.14.4 SENSE resistor check
The purpose of this security check is to verify the connection between the device and the sense shunt resistor and to verify the optional sense resistor filter network is not open. To perform this test, the following procedure has to be followed: Set SD = low Send StartConfig command Set SENSE_EN = '1' Set SNSCHK = '1' Send StopConfig command Wait tRchk + tSENSERchk Read SENSE flag – SENSE = '0' → OK (VSENSE < VSENSEth) – SENSE = '1' → FAIL (VSENSE > VSENSEth) During the check a small current ISENSERchk is sourced from the SENSE pin (see Figure 18). If the sense resistor is not present or floating, SENSE pin voltage will rise and once VSENSEth is exceeded, a SENSE fault will be reported in the STATUS1 register within tRchk. To ensure the check result, the following condition has to be verified: – The SENSE flag read has to be delayed of t SENSERchk, which is the time the customer filtering network and/or the power switch gate takes to reach VSENSEth by the ISENSERchk current.
7.14.5 DESAT comparator check
the test should fail, the output remains on as long as the input signal remains high. At the end of the check the DESAT fault remains set (it is latched), and it has to be cleared. Figure 19. DESAT comparator check circuitry
STGAP1AS Functional description
7.15 Register corruption protection
All the configuration registers are protected against content corruption. If the value of a local register is changed without a proper command is received (WriteReg, ResetStatus or GlobalReset), the REGERRL flag is set low and the device is forced in “safe state”. If the value of a remote register is changed without a proper command is received (WriteReg or GlobalReset), the REGERRR flag is set low and the device is forced in “safe state”.
8 SPI interface
set the device parameters and for advanced diagnostic. tdesCS parameter in Table 6 on page 14 for required wait time after each command. SDO: serial data output (MISO). CK signal must be low) as shown in Figure 20. Figure 20. SPI timings The SPI interface can work up to 5 Mbps and provides the daisy chain feature. registers of each device. An example of daisy chain configuration is shown in Figure 21.
Figure 23. Block diagram of the CRC generator discarded. Some examples are listed in Table 12. Table 11. CRC byte examples (from host to device) StopConfig 0x3A 0xAA N.A. N.A. ResetStatus 0xD0 0x32 N.A. N.A. ReadReg(CFG3) 0xBE 0x3F N.A. N.A.
Table 12. CRC byte examples (from device to host)
9 Programming manual
9.1 SPI commands
The commands summary is given in Table 13.
9.1.1 StartConfig and StopConfig commands
(CFGx and DIAGxCFG), which is only possible by entering in configuration mode. received and interpreted, the IC registers writing is enabled. configuration are undone and the previous configuration is restored. Table 13. SPI commands Table 14. StartConfig command synopsis
- The CRC byte of the command, if the CRC check is disabled this byte is ignored.
Table 15. StopConfig command synopsis
- The CRC byte of the command, if the CRC check is disabled this byte is ignored.
configuration mode and make all changes effective. or VH) is removed and then restored. registers after that the proper VDD level is restored. the device at the end of the configuration sequence. Figure 24. STGAP1AS recommended configuration flow
9.1.2 WriteReg command
Table 16. WriteReg command synopsis
- The command byte where AAAAA is the address of the target register.
- The CRC byte of the command, if the CRC check is disabled this byte is ignored.
- Data to be written into the target register.
- The CRC byte of the command and data, if t he CRC check is disabled this byte is ignored.
and the SPI_ERR flag is forced low. to Section : CRC protection on page 46).
9.1.3 ReadReg command
device, the register value and the respective CRC code is prepared for the transmission. register is located. The reading of a local register (low voltage side) is available in 800 ns. the two sides of the device, is available in 30 µs. purpose, including a NOP or the ReadReg command for the next register to be read. Table 17. ReadReg command synopsis
- Proper time have to be waited in order to allow the device to prepare the data.
- The command byte where AAAAA is the address of the target register.
- The CRC byte of the command, if the C RC check is disabled this byte is ignored.
- The CRC byte of the NOP command.
- Data read from the target register.
- The CRC byte of the data.
9.1.4 ResetStatus and GlobalReset commands
otherwise the SPI_ERR flag is forced low. the command is ignored and the SPI_ERR flag is forced low.
9.1.5 Sleep command
ignored and the SPI_ERR flag is forced low. Refer to Section 6.4 on page 24 for the description of the standby mode.
9.1.6 NOP command
The command does not modify the device status and does not generate any answer. Table 18. ResetStatus command synopsis
- The CRC byte of the command, if the CRC check is disabled this byte is ignored.
Table 19. GlobalReset command synopsis
- The CRC byte of the command, if the CRC check is disabled this byte is ignored.
Table 20. Sleep command synopsis
- The CRC byte of the command, if the CRC check is disabled this byte is ignored.
Table 21. NOP command synopsis
- The CRC byte of the command, if the CRC check is disabled this byte is ignored.
9.2 Registers and flags description
All device features can be configured through a set of 8-bit long registers. the two copies is kept synchronized. A map of the user registers is shown in Table 22. Table 22. Registers map
- R: remote (isolated side), L: local (low voltage side).
9.2.1 CFG1 register (low voltage side)
The CFG1 register has the structure of Table 24. The CRC_SPI bit enables the CRC check on the SPI communication protocol. The UVLOD_EN bit enables the UVLO protection on VDD supply voltage. Table 23. Registers access Table 24. CFG1 register Table 25. CRC enable
0 Disabled
1 Enabled
Table 26. VDD supply voltage UVLO enable
causes all the latched flags of the status registers to be released at the next SD rising edge. according to Table 28. Refer to Section 7.1 on page 25 for details. The DTset bits set the deadtime value. The INfilter bits set the input deglitch time tdeglitch for the SD, IN- and IN+ pins. Table 27. SD pin FAULT management Table 28. IN-/DIAG2 pin functionality
0 The IN-/DIAG2 pin work as input
Table 29. Deadtime
00 D i s a b l e d
Table 30. Input deglitch time
9.2.2 CFG2 register (isolated side)
The CFG2 register has the structure of Table 31. Section 7.8 on page 33 for details. and the DESATth parameter sets the DESAT comparator threshold according to Table 34. Refer to Section 7.6 on page 30 for details. Table 31. CFG2 register Table 32. SENSE threshold Table 33. DESAT current
9.2.3 CFG3 register (isolated side)
The CFG3 register has the structure of Table 35. off sequence (refer to Section 7.10 on page 33 for details). Table 34. DESAT threshold Table 35. CFG3 register
Table 36. 2LTOth
9.2.4 CFG4 register (isolated side)
The CFG4 register has the structure of Table 38. Table 37. 2-level turn-off time value
0000 D i s a b l e d
Table 38. CFG4 register Table 39. VH and VL supply voltages OVLO enable
Setting the parameter to zero disables the UVLO protection of the VL supply. Setting the parameter to zero disables the UVLO protection of the VH supply.
9.2.5 CFG5 register (isolated side)
The CFG5 register has the structure of Table 43. Table 40. UVLO protection management
0 UVLO protection is not latched
1 UVLO protection is latched
Table 41. VL negative supply voltage UVLO threshold Table 42. VH positive supply voltage UVLO threshold Table 43. CFG5 register
Section 7.10 on page 33 for details. 2-level turn-off time according to Table 37. Section 7.8 on page 33 for details). Table 44. 2LTO mode Table 45. SENSE comparator enabling
0 SENSE comparator disabled
1 SENSE comparator enabled
Table 46. DESAT comparator enabling
0 DESAT comparator disabled
1 DESAT comparator enabled
Table 47. Miller clamp feature enabling
0 Miller clamp feature disabled
1 Miller clamp feature enabled
9.2.6 STATUS1 register (low voltage side)
The STATUS1 is a read only register that reports some device failure flags. has the structure of Table 48. A description of the STATUS1 register bits is provided in Table 49. Table 48. STATUS1 register
- Default value of the local copy of the register. The value will be updated according to the actual information from the
Table 49. STATUS1 register description voltage reach VDESATth threshold. voltage reach VSENSEth threshold. Thermal shutdown protection flag.
9.2.7 STATUS2 register (low voltage side)
The STATUS2 is a read only register. The STATUS2 register has the structure of Table 50. A description of the STATUS2 register bits is provided in Table 51.
9.2.8 STATUS3 register (low voltage side)
The STATUS3 is a read only register. The STATUS3 register has the structure of Table 52. Table 50. STATUS2 register
- Default value of the local copy of the register. The value will be updated according to the actual information from the
Table 51. STATUS2 register description Register or communication error on isolated side. – Isolated interface communication fails. one of the remote registers. Table 52. STATUS3 register
- The default is forced at the device power-up, when the regi sters are reset all the flags are forced low (no failures).
A description of the STATUS3 register bits is provided in Table 53.
9.2.9 TEST1 register (isolated side)
The TEST1 register has the structure of Table 54. Setting an one check bit of the register enables the respective check mode. Table 53. STATUS3 register description SPI communication error flag. – Wrong number of CK rising edges. – Isolated interface communication fails. occurs in one of the remote registers. It is latched at power-up/reset also. Table 54. TEST1 register
9.2.10 DIAG1CFG and DIAG2CFG registers (low voltage side)
The DIAG1CFG register has the structure of Table 56. The DIAG2CFG register has the structure of Table 57. drain connected to the DIAG1 pin forcing the output low. fault events turn on the open drain connected to the DIAG2 pin forcing the output low. Table 55. Check mode Table 56. DIAG1CFG register Table 57. DIAG2CFG register
Table 58. Relation between DIAGxCFG bits and failure conditions
0 Thermal warning TWN
1 Thermal shutdown TSD
2 ASC feedback ASC, DT_ERR
3 Desaturation and sense detection DESAT, SENSE
4 Overvoltage failure OVLOH, OVLOL
5 Undervoltage failure UVLOH, UVLOL
6 VDD power supply failure UVLOD, OVLOD
7 SPI communication error or register failure SPI_ERR, REGERRL, REGERRR
10 Typical application diagram
Figure 25. Typical application diagram in half-bridge configuration
specifications, grade definitions and product status are available at: www.st.com.
11.1 SO24W package information
Figure 26. SO24W package outline
Figure 27. SO24W suggested land pattern Table 59. SO24W package mechanical data
- Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm per side.
Table 60. Device summary
- Qualified and characterized according to AEC Q100 and Q003 or equivalent, advanced screening
according to AEC Q001 and Q002 or equivalent. Table 61. Document revision history 10-Jun-2016 1 Initial release. Updated main title on page 1. Updated Figure 1 on page 8 (replaced by new figure). Updated “VREG” values in Table 4 on page 12. Minor modifications throughout document.