STG5682 STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 16

Technical content

Datasheet sections

  • 1 Pin settings
  • 1.1 Pin connection
  • 1.2 Pin description
  • 2 Device summary
  • 3 Maximum rating
  • 3.1 Recommended operating conditions
  • 4 Electrical characteristics
  • 5 Package mechanical data
  • 6 Revision history

Features

■ Distortion-free negative signal throughput down to VCC-5.5V ■ Wide operating voltage range: V CC (Opr) = 1.65V to 4.5V single supply ■ Ultra low power dissipation: I CC = 0.2µA (Max.) at tA = 85°C ■ Low "ON" resistance VIN = 0V: RON = 0.5Ω (max. tA = 25°C) at VCC = 4.3V ■ 4.3V tolerant and 1.8V compatible threshold on digital control input at VCC = 1.65 to 3.0V ■ Latch-up performance exceeds 300mA (JESD 17) ■ ESD performance exceeds JESD22 ■ 2000-V human-body model (A114-A)

Description

The STG5682 is a high-speed CMOS low voltage dual analog S.P .D.T. (Single Pole Dual Throw) SWITCH or 2:1 Multiplexer /Demultiplexer Switch fabricated in silicon gate C 2MOS technology. It is designed to operate from 1.65V to 4.5V, making this device ideal for portable applications. Additional key features are fast switching speed, Break Before Make Delay Time and Ultra Low Power Consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. QFN16L (2.6mm x 1.8mm) Order code Part number Package Packaging STG5682QTR QFN16L (2.6mm x 1.8mm) Tape and reel

1 Pin settings

1.1 Pin connection

Figure 1. Pin connection (top through view)

1.2 Pin description

Table 1. Pin description

7 VCC Positive supply voltage

8 GND Ground (0V)

2 Device summary

Figure 2. Input equivalent circuit Table 2. Truth table

3 Maximum rating

Program and other relevant quality documents. Table 3. Absolute maximum ratings

  1. Derate above 70ºC by 18.5mW/C

3.1 Recommended operating conditions

Table 4. Recommended operating conditions

  1. Truth Table guaranteed: 1.2V to 4.3V

4 Electrical characteristics

Table 5. DC specifications

4.3 VS = Open

  1. Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the

specified analog signal ranges. Table 5. DC specifications (continued)

Table 6. AC electrical characteristics (CL = 35pF , RL = 50Ω, tr = tf ≤ 5ns)

Table 7. Analog switch characteristics (CL = 5pF , RL = 50Ω, TA = 25°C)

  1. Off Isolation = 20Log10 (V D/VS), VD = output. VS = input to off switch.

5 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com

Note: 1 VFQFPN - Standard for thermally enhanced vey fine pitch quad flat package no leads. 2 The leads size is comprehensive of the thickness of the leads finishing material. 3 Dimensions do not include mold protusion. 4 Package outline exclusive of metal burrs dimensions.

5 Shipping media tape and reel units: 3000

Figure 3. Foot print recommendation Table 8. QFN16L (2.6x1.8mm) mechanical data

Figure 4. Package information

Figure 5. QFN16L (2.6mmx1.8mm) tape & reel

6 Revision history

Table 9. Revision history