STG3682 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 19
Technical content
Datasheet sections
- 1 Pin settings
- 1.1 Pin connection
- 1.2 Pin description
- 2 Device summary
- 3 Maximum rating
- 3.1 Recommended operating conditions
- 4 Electrical characteristics
- 5 Test circuits
- 6 Package mechanical data
- 7 Revision history
Features
■ Ultra low power dissipation: –I CC = 0.2µA (Max.) at TA = 85°C ■ Low “ON” resistance: –R ON = 4.6Ω (TA = 25°C) at VCC = 4.3V –R ON = 5.8Ω (TA = 25°C) at VCC = 3.0V ■ Wide operating voltage range: –V CC (Opr) = 1.65V to 4.3V single supply ■ 4.3V tolerant and 1.8V compatible threshold on digital control input at VCC = 2.3V to 3.0V ■ Typical bandwidth (-3dB) at 800MHz on all channels ■ Latch-up performance exceeds 100mA per JESD 78, Class II ■ ESD performance exceeds JESD22 – 2000-V Human body model (A114-A) ■ USB (2.0) High speed (480Mbps) signal switching compliant
Description
The STG3682 is a high-speed CMOS low voltage dual analog S.P .D.T. (Single Pole Dual Throw) Switch or 2:1 Multiplexer /Demultiplexer Switch fabricated in silicon gate C 2MOS technology. It is designed to operate from 1.65V to 4.3V, making this device ideal for portable applications. The nSEL inputs are provided to control the switch. The switch S1 is ON (they are connected to common Ports Dn) when the nSEL input is held high and OFF (high impedance state exists between the two ports) when SEL is held low; the switch S2 is ON (it is connected to common Port D) when the nSEL input is held low and OFF (high impedance state exists between the two ports) when nSEL is held high. Additional key features are fast switching speed, Break Before Make Delay Time and Ultra Low Power Consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. QFN10 (1.8mm x 1.4mm) Order codes Part number Package Packaging STG3682QTR QFN10 (1.8mm x 1.4mm) Tape and reel
1 Pin settings
1.1 Pin connection
Figure 1. Pin connection (top through view)
1.2 Pin description
Note: Exposed pad must be soldered to a floating plane. Do NOT connect to power or ground. Table 1. Pin description
9 VCC Possitive supply voltage
5 GND Ground (0V)
2 Device summary
Figure 2. Input equivalent circuit Table 2. Truth table
3 Maximum rating
Program and other relevant quality documents.
3.1 Recommended operating conditions
Table 3. Absolute maximum ratings
- Derate above 70ºC by 18.5mW/C
Table 4. Recommended operating conditions
- Truth Table guaranteed: 1.2V to 4.3V
4 Electrical characteristics
Table 5. DC specifications
- Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
specified analog signal ranges.
Table 6. AC electrical characteristics (CL = 35pF , RL = 50Ω, tr = tf ≤ 5ns)
Table 7. Analog switch characteristics (CL = 5pF , RL = 50Ω, TA = 25°C)
- Off Isolation = 20Log10 (V D/VS), VD = output. VS = input to off switch.
Table 8. USB related AC electrical characteristics
5 Test circuits
Figure 3. ON-Resistance Figure 4. Bandwidth Figure 5. OFF Leakage Figure 6. Channel to channel crosstalk Figure 7. OFF Isolation
Figure 8. Test circuit
6 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com
Figure 12. Package dimension Table 9. QFN10L(1.8x1.4) Mechical data
Figure 15. QFN10L(1.8x1.4) Reel information
Figure 16. QFN10L(1.8x1.4) Reel information
7 Revision history
Table 10. Revision history