STG3155 STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 18

Technical content

Datasheet sections

  • 1 Pin connections and functions
  • 2 Electrical ratings
  • 3 Electrical characteristics
  • 3.1 DC Electrical characteristics
  • 3.2 AC Electrical characteristics
  • 3.3 Analog switch characteristics
  • 3.4 Truth table
  • 4 Typical application circuit
  • 5 Test circuit
  • 6 Package mechanical data
  • 7 Revision history

Features

■ High speed: –t PD = 1.5ns (Typ.) at VCC = 3.0V –t PD = 1.5ns (Typ.) at VCC = 2.3V ■ Ultra low power dissipation: CC = 0.2µA (Max.) at TA = 85°C ■ Low "ON" resistance: ON = 0.5Ω (TA = 25ºC) at VCC = 4.3V –R ON = 0.6Ω (TA = 25ºC) at VCC = 3.0V –R ON = 1.0Ω (TA = 25ºC) at VCC = 1.8V ■ Wide operating voltage range: –V CC (OPR) = 1.65V to 4.3V single supply ■ 4.3V Tolerant and 1.8V compatible threshold on digital control input at VCC = 2.3V to 3.0V ■ Latch-up performance exceeds 300mA (JESD 17) ■ ESD Performance (Analog Chan. Vs. GND): HMB >2kV (MIL STD 883 method 3015)

Description

The STG3155 is a high-speed CMOS low voltage single analog S.P .D.T. (Single Pole Dual Throw) switch or 2:1 Multiplexer /Demultiplexer switch fabricated in silicon gate C 2MOS technology. It is designed to operate from 1.65V to 4.3V, making this device ideal for portable applications. The device offers very low ON-Resistance (<0.5Ω) at V CC = 4.3V. The SEL inputs are provided to control the switch. The switch S1 is ON (they are connected to common Ports Dn) when the SEL input is held high and OFF (high impedance state exists between the two ports) when SEL is held low; the switch S2 is ON (it is connected to common Port D) when the SEL input is held low and OFF (high impedance state exists between the two ports) when SEL is held high. Additional key features are fast switching speed, break-before-make delay time and Ultra Low Power Consumption. All inputs and outputs are equipped with protection circuits against static discharge, giving them ESD immunity and transient excess voltage. DFN6L STG3155 Low voltage 0.5Ω Max single SPDT switch with break-before-make feature Table 1. Device summary

1 Pin connections and functions

Figure 1. Pin connections (top through view) Figure 2. Input equivalent circuit Table 2. Pin descriptions

3 D Common Channels

1 SEL Control

5 GND Ground (0V)

2 Electrical ratings

Program and other relevant quality documents. Table 3. Absolute maximum ratings

  1. Derate above 70 ºC by 18.5mW/C

Table 4. Recommended operating conditions

  1. Truth table guaranteed: 1.2V to 4.3V

3 Electrical characteristics

3.1 DC Electrical characteristics

Table 5. DC Specifications

  1. ∆RON = RON(Max) - RON(Min)
  2. Flatness is defined as the difference between the maximum and minimum value of ON-resistance as measured over the

specified analog signal ranges. Table 5. DC Specifications (continued)

3.2 AC Electrical characteristics

Table 6. AC Electrical characteristics

3.3 Analog switch characteristics

3.4 Truth table

Table 7. Analog switch characteristics

  1. OFF Isolation = 20Log 10 (VD/VS), VD = output. VS = input to OFF switch.

Table 8. Truth table

4 Typical application circuit

Figure 3. ON-Resistance Figure 4. Bandwidth Figure 5. OFF Leakage Figure 6. Channel to channel crosstalk Figure 7. OFF Isolation

5 Test circuit

Figure 8. Test circuit Figure 9. Break-before-make time delay

6 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com

Table 9. DFN6L (1.45mm x 1mm) Mechanical data Figure 12. Package dimensions

Figure 13. Tape and Reel Information

Figure 14. Tape and Reel Information

Figure 15. Tape and Reel Information

7 Revision history

Table 10. Document revision history