STG200G65FD8AG STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 11
Technical content
Datasheet sections
- 1 Mechanical parameters
- 2 Electrical ratings
- 3 Electrical characteristics
- 4 Die layout
- 5 Additional information
- 5.1 Additional testing and screening
- 5.2 Shipping
- 5.3 Handling
- 5.4 Wafer/die and storage
Features
- AEC-Q101 qualified
- Low-loss series IGBT
- Low VCE(sat) = 1.52 V (typ.) at IC = 200 A
- Positive VCE(sat) temperature coefficient
- Tight parameter distribution
- Maximum junction temperature: TJ = 175 °C
Applications
- EV/HEV traction inverters
Description
This device is an IGBT developed using an advanced proprietary trench gate field- stop structure. The device is part of the M series IGBTs, which represent an optimal balance between inverter system performance and efficiency where the low-loss and the short-circuit functionality is essential. Furthermore, the positive VCE(sat) temperature coefficient and the tight parameter distribution result in safer paralleling operation. C E EGCD G Product status link STG200G65FD8AG Product summary Order code STG200G65FD8AG VCE 650 V ICN 200 A Die size 9.30 x 7.23 mm Packing D8 Automotive-grade trench gate field-stop 650 V, 200 A, high-efficiency M series IGBT die in D8 packing STG200G65FD8AG Datasheet DS14389 - Rev 1 - July 2023 For further information contact your local STMicroelectronics sales office.
1 Mechanical parameters
Table 1. Mechanical parameters
2 Electrical ratings
Table 2. Absolute maximum ratings
- Current level depends on the assembly thermal properties, wires and is limited by maximum junction temperature.
- Pulse width limited by maximum junction temperature.
3 Electrical characteristics
TJ = 25 °C unless otherwise specified. Table 3. Static characteristics (tested on wafer unless otherwise specified) Table 4. Electrical characteristics (not tested at chip level, verified by design/characterization)
Electrical characteristics
Table 5. Switching characteristics on inductive load (not tested at chip level, verified by design/
- Including the reverse recovery of the external diode.
- Including the tail of the collector current.
technology. These results are obtained using an ST custom package.
4 Die layout
Figure 1. Die drawing (dimensions are in mm) Table 6. Die delivery and sealed with a cover tape.
Figure 2. Tape drawing (dimensions are in mm) Controlled document. Consult the Document Management System (DMS) for the latest version.
5 Additional information
5.1 Additional testing and screening
For customers requiring products supplied as KGD (known good die) or requiring specific die level testing, please contact the local ST sales office. If KGD is requested, the shipping delivery is D8.
5.2 Shipping
Several shipping options are offered, consult the local ST sales office for availability:
- Die on film sticky foil - suffix on sales type D7
- Carrier tape - suffix on sales type D8
5.3 Handling
- Products must be handled at ESD safe workstations only. Standard ESD precautions and safe work environments are as defined in MIL-HDBK-263
- Products must be handled in a class 1000 only or better designated clean room environment
- Singular die is not to be handled with tweezers. A vacuum wand with a non-metallic ESD protected tip should be used
5.4 Wafer/die and storage
Proper storage conditions are necessary to prevent product contamination and/or degradation after shipment. STG200G65FD8AG Additional information DS14389 - Rev 1 page 8/11
Revision history
Table 7. Document revision history 21-Jul-2023 1 First release.
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