STG1218 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 29
Technical content
Datasheet sections
- 1 Pin description, block diagram and truth table
- 1.1 Pin description
- 1.2 Block diagram
- 1.3 Truth table
- 2 Absolute maximum ratings
- 3 Electrical characteristics
- 4 Electrical characteristics curves
- 5 Test circuits
- 6 Application information
- 7 Package information
- 7.1 QFN20 (4x4 mm) package information
- 8 Ordering information
Features
- Wide operating voltage range – Total voltage: 2.7 V to 15.5 V – Positive supply: 2.7 V to 5.5 V – Negative supply: down to -12 V
- Break before make feature
- Quad channel with one control pin for all switches
- Inhibit pin to set the swicthes in high impedance
- Benefits – GaN and LDMOS compatible – Compatible with 1.8 V and 3.3 V standard logic levels
Applications
- 5G telecom infrastructure
- Remote radio unit LDMOS and GaN
- Gain selection for instrumentation
Description
The STG1218 is a quad channel analog switch (SPDT), which is able to accommodate with positive and negative voltages. Each channel has an independent selection pin, and a common inhibit pin. Thanks to its large operating voltage range and low Ron, this switch can fit many applications such as RRU (both LDMOS and GaN solutions). It is also a good operational amplifier companion chip used with a standard 3.3 V single supply operation for gain selection. In addition, it has the versatility to be compatible with 3.3 V and 1.8 V logic standard thresholds. Logic 1S1 1S2 2S1 2S2 3S1 Sel1 Sel2 Sel3 Sel4 INH 4S1 4S2 STG1218 SWITCHES SHOWN FOR A 0 INPUT LOGIC 3S2 Product status link STG1218 Dual supply, quad SPDT switch, 1.8 V and 3.3 V logic input compatible STG1218 Datasheet DS13729 - Rev 3 - December 2021 For further information contact your local STMicroelectronics sales office.
1 Pin description, block diagram and truth table
1.1 Pin description
Figure 1. Pin connections (top view)
13 V DD
19 SEL1
17 SEL4
18 INH
Table 1. Pin description Control pins. Operate only when INH is low. If SELi is high, Di is connected to iS1.
4 GND Ground (0 V)
13 VDD Positive supply voltage
3 VSS Negative supply voltage
1.2 Block diagram
Figure 2. Block diagram
1.3 Truth table
Table 2. Truth table
2 Absolute maximum ratings
Table 3. Absolute maximum ratings
- All voltage values are with respect to ground, unless otherwise specified.
- Voltage and current limited whichever occurs first.
- R th-ja is a typical value, obtained with PCB according to the standard JEDEC 2s2p without vias.
- The maximum continuous power dissipation is: (150 °C - Top)/Rth-ja. In each switch, the power dissipation is RON*I2, where
In any case, the DC output current condition should be satisfied.
- Human body model: HBM test according to the standard ESDA/JEDEC JS-001-2017.
- Charged device model: CDM test according to the standard AEC-Q100-011.
Table 4. Operating conditions
3 Electrical characteristics
VSEL = 0 V or VDD, VINH = 0 V, typical characteristics are given at Top = 25 °C and min./max. values cover full temperature range (unless otherwise specified). Table 5. DC electrical characteristics
Electrical characteristics
Symbol Parameters and conditions Specific conditions Min. Typ. Max. Unit ∆RON ON-resistance mismatch Max. delta between 8 Ron values of the device (4 channels x 2 positions) VS = VSS to VDD, I = 10 mA VDD = 5 V, VSS = -10.5 V 0.3 0.5 Ω VDD = 5 V, VSS = 0 V 0.3 0.5 VDD = 4.5 V, VSS = 0 V 0.3 0.5 VDD = 3 V, VSS = -12 V 0.3 0.5 VDD = 3 V, VSS = -10V 0.3 0.5 VDD = 3 V, VSS = -8 V 0.3 0.5 ∆RON/∆T ON-resistance temperature coefficient (worst case between Tmin. to 25 °C and 25 °C to Tmax. considered) VS = VSS to VDD, I = 10 mA VDD = 5 V, VSS = -10.5 V 16 mΩ/°C VDD = 5 V, VSS = 0 V 28 VDD = 4.5 V, VSS = 0 V 30 VDD = 3 V, VSS = -12 V 16 VDD = 3 V, VSS = -10V 18 VDD = 3 V, VSS = -8 V 19 ISOFF Sn OFF leakage current VD = VSS to VDD, VS = VSS to VDD VSEL = 0 V for iS1, VSEL = VDD for iS2 VDD = 5 V, VSS = 0 V 0.001 1.5 µAVDD = 3.3 V, VSS = -12 V 0.001 1.5 VDD = 3.3 V, VSS = -8 V 0.001 1.5 IDOFF DOFF leakage current VD = VSS to VDD, VS = VSS to VDD VSEL = 0 V for iS1, VSEL = VDD for iS2 VDD = 5 V, VSS = 0 V 0.001 2.5 µAVDD = 3.3 V, VSS = -12 V 0.001 2.5 VDD = 3.3 V, VSS = -8 V 0.001 2.5 IDON DON leakage current VD = VSS to VDD, VS = VSS to VDD, VSEL = 0 V for iS2, VSEL = VDD for iS2 VDD = 5 V, VSS = 0 V 0.001 1.5 µAVDD = 3.3 V, VSS = -12 V 0.001 1.5 VDD = 3.3 V, VSS = -8 V 0.001 1.5 STG1218
VINH = 0 V, typical characteristics are given at Top = 25 °C and min./max. values cover full temperature range (unless otherwise specified). Table 6. AC electrical characteristics
Symbol Parameters and conditions Specific conditions Min. Typ. Max. Unit tONS2 (SEL) Skew Turn ON time SEL pin skew max.(tONiS2) -min.(tONiS2) VDD = 5 V, VSS = 0 V 87 nsVDD = 3.3 V, VSS = -12 V 59 VDD = 3.3 V, VSS = -8 V 59 tOFFS1 (SEL) Skew Turn OFF time SEL pin skew max.(tOFFiS1) -min.(tOFFiS1) VDD = 5 V, VSS = 0 V 89 ns VDD = 3.3 V, VSS = -12 V 63 VDD = 3.3 V, VSS = -8 V 63 tOFFS2 (SEL) Skew Turn OFF time SEL pin skew max.(tOFFiS2)-min.(tOFFiS2) VDD = 5 V, VSS = 0 V 1 VDD = 3.3 V, VSS = -12 V 1 VDD = 3.3 V, VSS = -8 V 1 tONS1 (INH) Turn ON time INH pin VS = VSS or VDD VSEL = VDD VINH step VDD to 0 V, RL = 300 Ω, CL = 20 pF, 50% to 90% of VS VDD = 5 V, VSS = 0 V 270 710 915 ns VDD = 3.3 V, VSS = -12 V 180 665 750 VDD = 3.3 V, VSS = -8 V 270 660 930 tONS2 (INH) Turn ON time INH pin VS = VSS or VDD VSEL = 0 V VINH step VDD to 0 V, RL = 300 Ω, CL = 20 pF, 50% to 90% of VS VDD = 5 V, VSS = 0 V 270 563 915 VDD = 3.3 V, VSS = -12 V 180 415 620 VDD = 3.3 V, VSS = -8 V 245 415 915 tOFF (INH) Turn OFF time INH pin VS = VSS or VDD VSEL = 0 V for iS2, VSEL = VDD for IS1, VINH step VDD to 0 V, RL = 300 Ω, CL = 20 pF, 50% to 90% of VS VDD = 5 V, VSS = 0 V 25 37 65 ns VDD = 3.3 V, VSS = -12 V 25 34 65 VDD = 3.3 V, VSS = -8 V 25 33 65 tD Break before make time delay, VSEL step 0 V to VDD 20 pF//300 Ω, 90% to 90% VDD = 5 V, VSS = 0 V, VS = 1.5 V 35 62 115 ns VDD = 3.3 V, VSS = -12 V, VS = 2.5 V 60 108 200 VDD = 3.3 V, VSS = -8 V, VS = 2.5 V 60 109 200 Q Charge injection CL =1 nF, RL = 1 MΩ, f = 500 kHz, iS1 = 0 V, iS2 floating VSEL step 0 V to VDD square waveform, or iS1 floating, iS2 = 0 V VDD = 5 V, VSS = 0 V 48 pC VDD = 3.3 V, VSS = -12 V 220 VDD = 3.3 V, VSS = -8 V 140 STG1218
Symbol Parameters and conditions Specific conditions Min. Typ. Max. Unit Q VSEL step VDD to 0 V square waveform pC CSOFF OFF channel capacitance VSEL = 0 V for iS1 capacitance VSEL = VDD for iS2 capacitance VDD = 5 V, VSS = 0 V 25 pFVDD = 3.3 V, VSS = -12 V 16 VDD = 3.3 V, VSS = -8 V 18 CSON, CDON ON channel capacitance VSEL = 0 V for iS2 capacitance VSEL = VDD for iS1 capacitance VSEL = 0 V or VDD for D capacitance VDD = 5 V, VSS = 0 V 66 pF VDD = 3.3 V, VSS = -12 V 62 VDD = 3.3 V, VSS = -8 V 57 OIRR OFF isolation 20log(VD/VS) VSEL = 0 V and 50 Ω on iS1 for iS1 test, VSEL = VDD and 50 Ω on iS2 for iS2 test, RL = 50 Ω, CL = 5 pF, VS = 1 Vrms, f = 1 MHz For those cases with Vss = 0 V a DC bias is added to AC signal and set to VDD/2 VDD = 5 V, VSS = 0 V -66 dB VDD = 3.3 V, VSS = -12 V -66 VDD = 3.3 V, VSS = -8 V -66 Xtalk Crosstalk 20log(VSi/VSj) VSEL = 0 V and 50 Ω on iS1 for iS2 test, VSEL = VDD and 50 Ω on iS2 for iS1 test, RL = 50 Ω, CL = 5 pF, VS = 1 Vrms, f = 1 MHz For those cases with Vss = 0 V a DC bias is added to AC signal and set to VDD/2 VDD = 5 V, VSS = 0 V -66 dB VDD = 3.3 V, VSS = -12 V -66 VDD = 3.3 V, VSS = -8 V -66 BW -3 dB bandwidth VSEL = 0 V for iS2 test, VSEL = VDD for iS1 test, RL = 50 Ω, CL = 5 pF, VS = 0 dBm For those cases with Vss = 0 V a DC bias is added to AC signal and set to VDD/2 VDD = 5 V, VSS = 0 V 150 200 MHz VDD = 3.3 V, VSS = -12 V 150 200 VDD = 3.3 V, VSS = -8 V 150 200 STG1218 DS13729 - Rev 3 page 10/29
4 Electrical characteristics curves
Figure 3. ON-resistance vs. S or D voltage for Figure 5. ON-resistance vs. S or D voltage for Figure 6. ON-resistance vs. S or D voltage for
Figure 25. Crosstalk
5 Test circuits
Figure 26. Input threshold voltage test circuit Figure 27. Input threshold Figure 28. Control input leakage current test circuit Figure 29. ON-resistance, flatness and mismatch Figure 30. OFF and ON leakage currents test circuit Figure 31. OFF leakage current test circuit
6 Application information
The device should be properly decoupled with 100 nF capacitors connected electrically and physically close to each power supply pin (VDD and VSS); the other terminal of the capacitor being connected to the ground plane. In order to obtain the best performance of the device, a proper layout should be done in order to minimize the impact of parasitic inductance to avoid significant LdI/dt overshoot voltages. Trace length should be minimized. If the application is switching DC signals, adding decoupling capacitors on the S or D pins connected to these sources is also a good practice. Unused analog pins (Di, iS1, iS2) can either be left floating or connected to ground (or any other fixed voltage compatible with the operating table). Digital pins (SELi and INH) must be connected to either 0 V or VDD. It is recommended to solder the exposed pad to a copper plane on PCB at VSS potential to obtain a better thermal impedance (but it can also be left open). When used for gain selection of an inverting gain amplification stage, it is recommended to place the switch directly on the inverting pin of the op amp (and not on the other side of Rg resistor). Indeed, as the input common mode voltage is fixed, the voltage on the analog switch is constant on all the channels, regardless of the analog signal being amplified. Therefore, even if the gain is reduced because of the Ron (-Rf/(Ron+Rg)), it is not modulated by its flatness which is not null. STG1218
Application information
DS13729 - Rev 3 page 21/29
7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
7.1 QFN20 (4x4 mm) package information
Figure 47. QFN20 (4x4 mm) package outline
Package information
DS13729 - Rev 3 page 22/29
Table 7. QFN20 (4x4 mm) mechanical data Figure 48. QFN20 (4x4 mm) recommended footprint
8 Ordering information
Table 8. Order code
Ordering information
DS13729 - Rev 3 page 24/29
Revision history
Table 9. Document revision history 29-Jun-2021 1 Initial release. 02-Dec-2021 3 Updated Section 4 Electrical characteristics curves.