Datasheet - STFW2N105K5 - N-channel 1050 V, 6 Ω typ., 1.5 A MDmesh K5 Power MOSFET in a TO-3PF package

Document overview

  • Manufacturer or author: STMICROELECTRONICS
  • PDF pages: 11

Technical content

Features

Order code VDS RDS(on) max. ID PTOT STFW2N105K5 1050 V 8 Ω 1.5 A 30 W

  • Very low FoM (figure of merit)
  • Ultra-low gate charge
  • 100% avalanche tested
  • Zener-protected

Applications

  • Switching applications

Description

This very high voltage N-channel Power MOSFET is designed using MDmesh K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. TO-3PF D(2) G(1) S(3) AM01476v1_No_tab Product status link STFW2N105K5 Product summary Order code STFW2N105K5 Marking 2N105K5 Package TO-3PF Packing Tube N-channel 1050 V, 6 Ω typ., 1.5 A MDmesh K5 Power MOSFET in a TO-3PF package STFW2N105K5 Datasheet DS10322 - Rev 2 - March 2026 For further information, contact your local STMicroelectronics sales office.

1 Electrical ratings

Table 1. Absolute maximum ratings

  1. Pulse width limited by safe operating area.

Table 2. Thermal data Table 3. Avalanche characteristics

2 Electrical characteristics

TC = 25 °C unless otherwise specified Table 4. On/off states

  1. Specified by design, not tested in production.

Table 5. Dynamic characteristics

  1. Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 V to the stated
  2. Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 V to the stated

Table 6. Switching times

Electrical characteristics

Table 7. Source-drain diode

  1. Pulse width limited by safe operating area.
  2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%.

2.1 Electrical characteristics (curves)

Figure 1. Safe operating area Figure 2. Normalized transient thermal impedance Figure 3. Typical output characteristics Figure 4. Typical transfer characteristics Figure 5. Typical gate charge characteristics Figure 6. Typical drain-source on-resistance

3 Test circuits

Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior Figure 15. Test circuit for inductive load switching and Figure 16. Unclamped inductive load test circuit Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform

4 Package information

To meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions, and product status are available at: www.st.com. ECOPACK is an ST trademark.

4.1 TO-3PF type A package information

Figure 19. TO-3PF type A package outline

Package information

Table 8. TO-3PF type A mechanical data

Revision history

Table 9. Document revision history Updated Section 4.1: TO-3PF type A package information.

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