STFU16N65M2 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 12
Technical content
Datasheet sections
- 1 Electrical ratings
- 2 Electrical characteristics
- 2.1 Electrical characteristics (curves)
- 3 Test circuits
- 4 Package mechanical data
- 4.1 TO-220FP ultra narrow leads package information
- 5 Revision history
Features
Order code VDS RDS(on) max ID STFU16N65M2 650 V 0.36 Ω 11 A Extremely low gate charge Excellent output capacitance (COSS) profile 100% avalanche tested Zener-protected
Applications
Switching applications
Description
This device is an N-channel Power MOSFET developed using MDmesh™ M2 technology. Thanks to its strip layout and an improved vertical structure, the device exhibits low on-resistance and optimized switching characteristics, rendering it suitable for the most demanding high efficiency converters. Table 1: Device summary Order code Marking Package Packaging STFU16N65M2 16N65M2 TO-220FP ultra narrow leads Tube TO-220FP ultra narrow leads 1 2 3 AM15572v1_no_tab D(2) G(1) S(3)
1 Electrical ratings
Table 2: Absolute maximum ratings Symbol Parameter Value Unit VGS Gate-source voltage ± 25 V ID Drain current (continuous) at TC = 25 °C 11(1) A ID Drain current (continuous) at TC = 100 °C 6.9(1) A IDM(2) Drain current (pulsed) 44(1) A PTOT Total dissipation at TC = 25 °C 25 W VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s; TC = 25 °C) 2500 V dv/dt (3) Peak diode recovery voltage slope 15 V/ns dv/dt (4) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range -55 to 150 °C Tj Operating junction temperature range Notes: (1)Limited by maximum junction temperature.. (2)Pulse width limited by safe operating area. (3)ISD ≤ 11 A, di/dt ≤ 400 A/µs; VDSpeak < V(BR)DSS, VDD=400 V (4)VDS ≤ 520 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 5 °C/W Rthj-amb Thermal resistance junction-ambient 62.5 °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 1.9 A EAS Single pulse avalanche energy (starting Tj = 25°C, ID = IAR; VDD = 50 V) 360 mJ
2 Electrical characteristics
(TC = 25 °C unless otherwise specified) Table 5: On /off states Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage ID = 1 mA, VGS = 0 V 650 V IDSS Zero gate voltage drain current VGS = 0 V, VDS = 650 V 1 µA VGS = 0 V, VDS = 650 V, TC = 125 °C(1) 100 µA IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2 3 4 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 5.5 A 0.32 0.36 Ω Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V - 718 - pF Coss Output capacitance - 32 - pF Crss Reverse transfer capacitance - 1.1 - pF Coss eq.(1) Equivalent output capacitance VDS = 0 to 520 V, VGS = 0 V - 189 - pF RG Intrinsic gate resistance f = 1 MHz open drain - 5.2 - Ω Qg Total gate charge VDD = 520 V, ID = 11 A, VGS = 0 to 10 V (see Figure 15: "Test circuit for gate charge behavior" - 19.5 - nC Qgs Gate-source charge - 4 - nC Qgd Gate-drain charge - 8.3 - nC Notes: (1)Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 325 V, ID = 5.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") - 11.3 - ns tr Rise time - 8.2 - ns td(off) Turn-off delay time - 36 - ns tf Fall time - 11.3 - ns
Table 8: Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current 11 A ISDM(1) Source-drain current (pulsed) 44 A VSD(2) Forward on voltage ISD = 11 A, VGS = 0 V - 1.6 V trr Reverse recovery time ISD = 11 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 342 ns Qrr Reverse recovery charge - 3.5 µC IRRM Reverse recovery current - 20.4 A trr Reverse recovery time ISD = 11 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 458 ns Qrr Reverse recovery charge - 4.6 µC IRRM Reverse recovery current - 20.5 A Notes: (1)Pulse width limited by safe operating area. (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5%
2.1 Electrical characteristics (curves)
Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Normalized VBR(DSS)vs. temperature Figure 7: Static drain-source on-resistance ID
0 VDS(V)5
(A) VGS= 7, 8, 9, 10 V GIPD221020141412FSR ID
0 VGS(V)2
(A) VDS = 18 V GIPD221020141640FSR V(BR)DSS 0.96 (norm) 0.88 125 0.92 1.00 1.04
1.08 ID= 1m A
RDS(on) 0.31 0 2 6 ID(A)4 (Ω) 0.30 0.32 0.33 VGS= 10V 0.34 GADG300420171114FSR
Figure 8: Gate charge vs. gate-source voltage Figure 9: Capacitance variations Figure 10: Normalized gate threshold voltage vs. temperature Figure 11: Normalized on-resistance vs. temperature Figure 12: Source-drain diode forward characteristics Figure 13: Output capacitance stored energy VGS 0 4 12 Qg(nC)8 (V) VDS(V) 100 200 300 400 500 VDD = 520 V ID = 11 A VDS GIPD221020141708FSR C 0.1 1 100 VDS(V)10 (pF) 0.1 100
1000 Ciss
VGS(th) 0.8 -75 -25 25 Tj(°C) (norm) 0.6 0.7 0.9 1.0 125 1.1 ID = 250 µ A GIPD180920141442FSR VSD 0.7 0 2 6 ISD(A)4 (V) 0.5 0.6 0.8 0.9 Tj= 150°C Tj= -50°C Tj= 25°C 1.1 GIPD221020141733FSR E 0 100 300 VDS(V)200 (µJ) 400 500 600 GIPD221020141721FSR
3 Test circuits
Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform
4 Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
4.1 TO-220FP ultra narrow leads package information
Figure 20: TO-220FP ultra narrow leads package outline 8576148_1
Table 9: TO-220FP ultra narrow leads mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 B 2.50 2.70 D 2.50 2.75 E 0.45 0.60 F 0.65 0.75 F1 - 0.90 G 4.95 5.20 G1 2.40 2.54 2.70 H 10.00 10.40 L2 15.10 15.90 L3 28.50 30.50 L4 10.20 11.00 L5 2.50 3.10 L6 15.60 16.40 L7 9.00 9.30 L8 3.20 3.60 L9 - 1.30 Dia. 3.00 3.20
5 Revision history
Table 10: Document revision history Date Revision Changes 03-Apr-2017 1 Initial release