STFI10LN80K5 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 13
Technical content
Datasheet sections
- 1 Electrical ratings
- 2 Electrical characteristics
- 2.1 Electrical characteristics (curves)
- 3 Test circuits
- 4 Package information
- 4.1 I2PAKFP (TO-281) package information
- 5 Revision history
Features
Order code VDS RDS(on) max. ID STFI10LN80K5 800 V 0.63 Ω 8 A Fully insulated and low profile package with increased creepage path from pin to heatsink plate Industry ’s RDS(on) x area Industry’s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected
Applications
Switching applications
Description
This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code Marking Package Packing STFI10LN80K5 10LN80K5 I²PAKFP Tube 1 2 3 I2PAKFP (TO-281) AM15572v1_no_tab D(2) G(1) S(3)
1 Electrical ratings
Table 2: Absolute maximum ratings Symbol Parameter Value Unit VGS Gate-source voltage ± 30 V ID (1) Drain current (continuous) at TC = 25 °C 8 A ID (1) Drain current (continuous) at TC = 100 °C 5 A ID (2) Drain current pulsed 32 A PTOT Total dissipation at TC = 25 °C 20 W VISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t=1s; TC=25°C) 2500 V dv/dt (3) Peak diode recovery voltage slope 4.5 V/ns dv/dt (4) MOSFET dv/dt ruggedness 50 Tj Operating junction temperature range - 55 to 150 °C Tstg Storage temperature range Notes: (1)Limited by maximum junction temperature. (2)Pulse width limited by safe operating area (3)ISD≤ 8 A, di/dt≤100 A/μs; VDS peak ≤ V(BR)DSS (4)VDS ≤ 640 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 6.25 °C/W Rthj-amb Thermal resistance junction-ambient 62.5 °C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 2.7 A EAS Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR, VDD = 50 V) 240 mJ
2 Electrical characteristics
TC = 25 °C unless otherwise specified Table 5: On/off-state Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA 800 V IDSS Zero gate voltage drain current VGS = 0 V, VDS = 800 V 1 µA VGS = 0 V, VDS = 800 V TC = 125 °C (1) 50 µA IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 100 µA 3 4 5 V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 4 A 0.55 0.63 Ω Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V - 427 - pF Coss Output capacitance - 43 - pF Crss Reverse transfer capacitance - 0.25 - pF Co(tr) (1) Equivalent capacitance time related VDS = 0 to 640 V, VGS = 0 V - 72 - pF Co(er) (2) Equivalent capacitance energy related 27 - pF Rg Intrinsic gate resistance f = 1 MHz , ID= 0 A - 7 - Ω Qg Total gate charge VDD = 640 V, ID = 8 A VGS= 10 V (see Figure 16: "Test circuit for gate charge behavior") - 15 - nC Qgs Gate-source charge - 4.2 - nC Qgd Gate-drain charge - 9 - nC Notes: (1)Time related is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS (2)Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS
Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD= 400 V, ID = 4 A, RG = 4.7 Ω VGS = 10 V (see Figure 15: "Test circuit for resistive load switching times" and Figure 20: "Switching time waveform") - 11.8 - ns tr Rise time - 10 - ns td(off) Turn-off delay time - 28 - ns tf Fall time - 13 - ns Table 8: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current 8 A ISDM (1) Source-drain current (pulsed) 32 A VSD (2) Forward on voltage ISD = 8 A, VGS = 0 V - 1.5 V trr Reverse recovery time ISD = 8 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 350 ns Qrr Reverse recovery charge - 3.9 µC IRRM Reverse recovery current - 22.5 A trr Reverse recovery time ISD = 8 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 17: "Test circuit for inductive load switching and diode recovery times") - 505 ns Qrr Reverse recovery charge - 5 µC IRRM Reverse recovery current - 20 A Notes: (1)Pulse width limited by safe operating area (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol Parameter Test conditions Min Typ. Max Unit V (BR)GSO Gate-source breakdown voltage IGS= ± 1 mA, ID= 0 A 30 - - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry.
2.2 Electrical characteristics (curves)
Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance δ=0.5K tp(s)10-4 10-3 10 δ=0.2 10-2 10-1 Single pulse 0.05 0.02 0.01 0.1 GC20940_ZTH
Figure 14: Maximum avalanche energy vs starting TJ
STFI10LN80K5 Test circuits
3 Test circuits
Figure 15: Test circuit for resistive load switching times Figure 16: Test circuit for gate charge behavior Figure 17: Test circuit for inductive load switching and diode recovery times Figure 18: Unclamped inductive load test circuit Figure 19: Unclamped inductive waveform Figure 20: Switching time waveform
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
4.1 I 2PAKFP (TO-281) package information
Figure 21: I²PAKFP (TO-281) package outline 8291506 Re v. C
Table 10: I²PAKFP (TO-281) mechanical data Dim. mm Min. Typ. Max. A 4.40 4.60 B 2.50 2.70 D 2.50 2.75 D1 0.65 0.85 E 0.45 0.70 F 0.75 1.00 1.20 G 4.95 5.20 H 10.00 10.40 L1 21.00 23.00 L2 13.20 14.10 L3 10.55 10.85 L4 2.70 3.20 L5 0.85 1.25 L6 7.50 7.60 7.70
5 Revision history
Table 11: Document revision history Date Revision Changes 10-Feb-2016 1 First release.