STF8N80K5 STMICROELECTRONICS | Alldatasheet

Document overview

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  • PDF pages: 15

Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuits
  • 4 Package mechanical data
  • 5 Revision history

Features

  • Worldwide best FOM (figure of merit)
  • Ultra low gate charge
  • 100% avalanche tested
  • Zener-protected

Applications

  • Switching applications

Description

These N-channel Zener-protected Power MOSFETs are designed using ST’s revolutionary avalanche-rugged very high voltage SuperMESH™ 5 technology, based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance, and ultra-low gate charge for applications which require superior power density and high efficiency. D(2) G(1) S(3) AM01476v1 TO-220FP I2PAKFP (TO-281) 1 2 Order codes V DS RDS(on)max. I D PTOT STF8N80K5 800 V 0.95 Ω 6 A 25 W STFI8N80K5 Table 1. Device summary

1 Electrical ratings

Table 2. Absolute maximum ratings

  1. Pulse width limited by safe operating area.
  2. Pulse width limited by T Jmax.
  3. Starting T J = 25 °C, ID=IAS, VDD= 50 V
  4. I SD ≤ 6 A, di/dt ≤ 100 A/μs, VDS(peak) ≤ V(BR)DSS

Table 3. Thermal data

2 Electrical characteristics

Table 4. On/off states Table 5. Dynamic

  1. Time related is defined as a constant equivalent capacitance giving the same charging time as C oss when
  2. Energy related is defined as a constant equival ent capacitance giving the same stored energy as C oss

voltage is appropriate to achieve efficient and cost-effective protection of device integrity. The integrated Zener diodes thus eliminate the need for external components. Table 6. Switching times Table 7. Source drain diode

  1. Pulsed: pulse duration = 300 μs, duty cycle 1.5%

Table 8. Gate-source Zener diode

2.1 Electrical characteristics (curves)

Figure 2. Safe operating area Figure 3. Thermal impedance Figure 4. Output characteristics Figure 5. Transfer characteristics Figure 6. Gate charge vs gate-source voltage Figure 7. Static drain-source on-resistance

Figure 8. Capacitance variations Figure 9. Output capacitance stored energy Figure 10. Normalized gate threshold voltage Figure 11. Normalized on-resistance vs. Figure 12. Drain-source diode forward Figure 13. Normalized VDS vs. temperature

0 VDS(V)

1.1 ID = 1mA

Figure 14. Maximum avalanche energy vs.

3 Test circuits

Figure 15. Switching times test circuit for Figure 16. Gate charge test circuit Figure 17. Test circuit for inductive load Figure 18. Unclamped inductive load test circuit Figure 19. Unclamped inductive waveform Figure 20. Switching time waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

Table 9. TO-220FP mechanical data

Figure 21. TO-220FP drawing

Figure 22. I2PAKFP (TO-281) drawing Table 10. I2PAKFP (TO-281) mechanical data

5 Revision history

Table 11. Document revision history