STESB01 STMICROELECTRONICS | Alldatasheet

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Technical content

Datasheet sections

  • 1 Schematic diagram
  • 2 Pin configuration
  • 3 Maximum ratings
  • 4 Electrical characteristics
  • 5 Diagram
  • 6 Package mechanical data
  • 7 Revision history

October 2006 Rev. 3 1/14 STESB01 ESBT Base Driver Feature summary ■ Controls ESBT base current in every line/load condition ■ Supply voltage range: 8V to 20 V ■ Storage time controlled by closed loop architecture (from 150ns to 1.5µs) ■ Under voltage lockout with hysteresis

Description

The STESB01 is a dedicated base current biasing transistor for the Emitter-Switched Bipolar Transistor (ESBT) family of power switches. The device is able to control the ESBT storage time (from 150ns to 1.5ìs) using closed loop architecture. This guarantees proper operation of the ESBT in every line and load condition, avoiding oversaturation of the device and, at the same time, ensuring the correct base current when a higher load is required. The storage time can be adjusted with an external resistor, which allows maximum flexibility in different applications. The optimization of the base current value also reduces the base current losses to minimum level. SOT23-6L SO-8 Order code Part number Package Packaging STESB01STR SOT23-6L 3000 Parts per Reel STESB01DR SO-8 2500 Parts per Reel

1 Schematic diagram

Figure 1. Schematic diagram

2 Pin configuration

Table 1. Pin description Figure 2. Pin Connections (Top View) Schematic) which determines the ESBT base current value. 6, 7 2 GND Ground. Reference for all the signal of the IC.

53 STGADJ

pin). A minimum value of 150ns can be achieved with 10kΩ resistor. See note 4.

44 VCOLL

rising edge of this signal provides end-of-storage time information.

25 P W M

signal provides beginning-of-storage time information.

3 Maximum ratings

Table 2. Absolute maximum ratings Table 3. Thermal data This value is referred to 1 layer PCB board with minimum copper connections for the leads.

4 Electrical characteristics

Table 4. Electrical characteristics

1 To the PWM pin must be applied a 5V to 0V falling edge while the voltage level on the VCOLL pin

maximum frequency of signals applied to PWM and VCOLL pins must be 300 kHz.

2 To the PWM pin must be applied a 5V to 0V falling edge while the voltage level on the VCOLL pin

maximum frequency of signals applied to PWM and VCOLL pins must be 300 kHz.

4 In parallel to the resistor a low-leakage/low-ESR capacitor could be necessary for bypassing

5 Diagram

Figure 3. Block diagram Figure 4. Typical operating characteristics

6 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

DIM. mm. mils A 0.90 1.45 35.4 57.1 A1 0.00 0.15 0.0 5.9 A2 0.90 1.30 35.4 51.2 b 0.35 0.50 13.7 19.7 C 0.09 0.20 3.5 7.8 D 2.80 3.00 110.2 118.1 E 2.60 3.00 102.3 118.1 E1 1.50 1.75 59.0 68.8 e. 9 5 3 7 . 4 e1 1.9 74.8 L 0.35 0.55 13.7 21.6 SOT23-6L MECHANICAL DATA

DIM. mm. inch A 1.35 1.75 0.053 0.069 A1 0.10 0.25 0.04 0.010 A2 1.10 1.65 0.043 0.065 B 0.33 0.51 0.013 0.020 C 0.19 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 E 3.80 4.00 0.150 0.157 e 1.27 0.050 H 5.80 6.20 0.228 0.244 h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 k ˚ (max.) ddd 0.1 0.04 SO-8 MECHANICAL DATA 0016023/C

DIM. mm. inch A 180 7.086 D 20.2 0.795 N 60 2.362 T 14.4 0.567 Tape & Reel SOT23-xL MECHANICAL DATA

DIM. mm. inch A 330 12.992 C 12.8 13.2 0.504 0.519 D 20.2 0.795 N 60 2.362 T 22.4 0.882 Ao 8.1 8.5 0.319 0.335 Bo 5.5 5.9 0.216 0.232 Ko 2.1 2.3 0.082 0.090 Po 3.9 4.1 0.153 0.161 P 7.9 8.1 0.311 0.319 Tape & Reel SO-8 MECHANICAL DATA

7 Revision history

Table 5. Revision history 16-Nov-2005 1 Initial release. 26-Jul-2006 2 Mistake on table 3 function of pin 3. 03-Oct-2006 3 Add new package SO-8.