Datasheet - STEF512GR - Dual electronic fuse for 5 V and 12 V rails
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 24
Technical content
Datasheet sections
- 1 Diagram
- 2 Pin configuration
- 3 Typical application
- 4 Maximum ratings
- 5 Electrical characteristics
- 6 Device functional description
- 6.1 Undervoltage lockout
- 6.2 Start-up sequence and voltage clamp
- 6.3 Current limit function
- 7 Typical characteristics
- 8 Package information
- 8.1 TSOT23-8L package information
- 8.2 TSOT23-8L packing information
- 9 Ordering information
Features
- 5 V and 12 V channels into one chip
- 25 V absolute maximum input voltage
- Precise output over voltage clamp
- Fixed current limit: 3 A on 5 V, 4 A on 12 V
- Latched-off thermal protection
- Input undervoltage lockout
- Adjustable output voltage slew-rate for each channel
- Integrated 40 mΩ Power FETs
- SAS disable pin
- TSOT23-8L package
Applications
- HDD and SSD drives
- Set-top boxes
- HDD and SSD array
Description
The STEF512GR is an integrated dual electronic fuse, designed to protect circuitry on its output from overcurrent and overvoltage events, in those applications requiring hot swap operation and in-rush current control. The device embeds two independent electronic fuses, one for the 5 V rails and one for the 12 V rails. Thanks to the very low ON-resistance of the integrated Power FETs, the voltage drop from the main supply to the load is very low during normal operations. The start-up time can be adjusted by the user for each eFuse, via two small soft-start capacitors, connected to the relevant pins. In this manner, the inrush current at startup can be kept under control. The maximum load current is precisely limited, by utilizing a sense FET topology, to factory-defined values. The device also provides a precise overvoltage clamp for each channel, preventing the load from being damaged by power supply failures, and undervoltage lockout (UVLO), assuring that the input voltage is above the minimum operating threshold, before the power device is turned on. When an overload condition occurs, the STEF512GR limits the output current to the predefined safe value. If the anomalous overload condition persists, the device goes into thermal shutdown, the internal switch is opened and the load disconnected from the power supply. Maturity status link STEF512GR Dual electronic fuse for 5 V and 12 V rails STEF512GR Datasheet DS13212 - Rev 3 - June 2021 For further information contact your local STMicroelectronics sales office.
1 Diagram
Figure 1. Block diagram (one channel)
2 Pin configuration
Figure 2. Pin connection (top view) Table 1. Pin description 1 VIN_12 12 V rail supply voltage.
2 SS12
this pin and GND to program the output voltage slew-rate. Do not leave floating.
3 SS5
this pin and GND to program the output voltage slew-rate. Do not leave floating. 4 VIN_5 5 V rail supply voltage. 5 VOUT_5 5 V rail output voltage.
7 EN SAS disable input: set this pin logic-low to turn on the device, high to turn off the
device. This pin is internally pulled down via 1 MΩ resistor. 8 VOUT_12 12 V rail output voltage.
3 Typical application
Figure 3. Typical application circuit
4 Maximum ratings
Table 2. Absolute maximum ratings Table 3. Thermal data
- Based on 4-layer JEDEC (2S2P) test board, constructed in accordance with the JESD 51-7 specification.
5 Electrical characteristics
TJ = 25°C, VIN_5 = 5 V, VIN_12 = 12 V, VEN = 0 V, CIN = 10 µF, COUT = 10 µF; unless otherwise specified. Table 4. Electrical characteristics
5 V eFuse
12 V eFuse
Electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit Iq Quiescent current (excluding EN current) Device operating 250 1000 µA Off-state, VEN = 5 V 40 80 µA IEN Sas disable pin current VEN = 5 V 10 µA Thermal protection TSD Shutdown temperature (2) 165 Hysteresis 20 1. Pulsed test. 2. Guaranteed by design or characterization, but not tested in production. 3. The maximum continuous current is the current level above which the control loop starts increasing the ON-resistance of the pass element. Table 5. Recommended operating conditions
6 Device functional description
The STEF512GR embeds a 5 V and a 12 V electronic fuse (eFuses). Each eFuse is an intelligent load switch, which is able to limit the voltage or the current during fault events, such as: input overvoltage or output overload respectively. For this purpose, it contains 2 analogue control loops, the former limits the output voltage and the latter limits the input current. The current limiting loop is also used during the start-up phase of the eFuse to limit the inrush current into the output capacitor. During the normal operation, the eFuse behaves like a low-resistance Power FET, therefore the output voltage follows the input one. In case of overvoltage or overcurrent events, the eFuse limits the VGS of the internal FET, in order to clamp the output voltage or current respectively. During such events the die temperature rises due to the power dissipation and so, if the fault persists and the overtemperature threshold is overcome, the device goes into thermal shutdown, the internal FET is turned-off and the load disconnected from the power supply. Once the eFuse is in thermal shutdown, it does not restart automatically. The eFuse can be restarted manually by toggling the EN pin or performing a power-up cycle, (this becomes effective as soon as the die temperature drops by at least the overtemperature hysteresis). Each eFuse provides factory-trimmed undervoltage lockout feature and user-adjustable output voltage rise time.
6.1 Undervoltage lockout
The undervoltage lockout circuit prevents each eFuse from turning on if the supply voltage is below the UVLO rising threshold. During this operation, if the input voltage falls below (VUVLO_x - VHyst_x), the output of the relevant channel is turned off. If the supply voltage comes back into the operative range, the relevant channel restarts with a soft-start cycle.
6.2 Start-up sequence and voltage clamp
The typical start-up sequence of each eFuse is as follows:
- The power supply is connected to the V IN_x pin and it is higher than the undervoltage lockout threshold
- The disable pin is asserted by the user to low logic level (or left floating), enabling the device
- Typically, 1.2 ms after the eFuse starts ramping up the output voltage
- Each channel ramps up with a rate set by the relevant C SSx
- If the input voltage continues rising, above the overvoltage threshold (V Clamp_x), as a consequence of a failure in the power supply, the eFuse limits the output voltage to VClamp_x. The eFuse keeps operating in this state until it hits its overtemperature threshold and shuts down.
6.3 Current limit function
Each eFuse provides 2 kinds of current limit protections:
- Operative current limit: in case of overload, i.e. if the load current exceeds the I Dxx, the device starts increasing the power MOS resistance. The overload current limit (ILim_x) is 3 A typ. for the 5 V fuse and 4 A (typ.) for the 12 V one.
- In case of strong overload or short-circuit, the short-circuit current limit is activated and the current is clamped to IShort_x: 1 A typ. on 5 V channel and 1.8 A typ. on 12 V channel. STEF512GR Device functional description DS13212 - Rev 3 page 8/24
7 Typical characteristics
The following plots are referred to the typical application circuit and, unless otherwise noted, at TA = 25°C. Figure 4. 5 V channel Ilim vs. temperature Figure 5. 12 V channel Ilim vs. temperature Figure 6. 5 V ch. RDS_ON vs. temperature Figure 7. 12 V ch. RDS_ON vs. temperature
Figure 26. VOut_12 voltage clamp
8 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.
8.1 TSOT23-8L package information
Figure 27. TSOT23-8L package outline
Package information
DS13212 - Rev 3 page 14/24
Table 6. TSOT23-8L mechanical data
Figure 28. TSOT23-8L recommended footprint
8.2 TSOT23-8L packing information
Figure 29. TSOT23-8L reel drawing outline
9 Ordering information
Table 7. Order code
Ordering information
DS13212 - Rev 3 page 19/24
Revision history
Table 8. Document revision history 24-Feb-2020 1 Initial release. 02-Mar-2020 2 Updated title in Figure 16. VOut_12 startup with 2 A load. 10-Jun-2021 3 Added new Section 8.2 TSOT23-8L packing information.