STE2007_06 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 62
Technical content
Features
■ 68 x 96 bits Display Data RAM ■ 33,49, 65 and 68 Lines mode ■ Row by row scrolling ■ Interfaces – 3-lines Serial Interface (read and write) –I 2C (read and write) – 4-Line serial (read and write) ■ Partial display mode (33,25,17,9 lines mode) ■ Fully integrated oscillator that requires no external components ■ CMOS compatible inputs ■ Programmable ID-Number ■ Programmable Bias Ratio ■ Programmable columns organization ■ Fully integrated configurable LCD bias voltage generator with: – Selectable multiplication factor (3x, 4X and 5X) – Effective sensing for high precision output – Eight selectable temperature compensation coefficients ■ Designed for chip-on-glass (COG) applications ■ Low power consumption, suitable for battery operated systems ■ Interfaces supply voltage range from 1.6 to 3.6V ■ High voltage generator supply voltage range from 2.4 to 3.6V ■ Display supply voltage range from 3 to 13.2V
Description
The STE2007 is a low power LCD driver, capable to drive 96 columns and up to 68 lines, designed for monochrome displays. The STE2007 includes fully integrated bias voltage generator (up to 5x multiplication factor), and internal oscillator, thus reducing to minimum the number of external components required and the current consumption. The STE2007 features the three standard serial interfaces (3 and 4 lines serial, I 2C interface).
1 Introduction
resolution of 96x68, 96x65, 96x49, and 96x33 (ColumnsXRows). Table 1. General driver parameters
Figure 1. Chip mechanical drawing
2 Driver pin description
2.1 CPU interface pins
2.2 Power supply pins
Table 2. CPU interface logic Table 3. Power supply pins
2.3 Configuration pins
Table 4. High voltage pins Table 5. Configuration pin description
2.4 Test pins
Table 6. Test pin description
3 Electrical characteristics
3.1 Absolute maximum ratings
Table 7. Absolute maximum ratings
- Device behavior and characterization are measur ed over this temperature range during internal
ambient temperature, typically 25°C.
3.2 DC characteristics
Tamb = 25°C; unless otherwise specified. Table 8. DC characteristics
3.3 AC characteristics
Tamb = 25°C; unless otherwise specified.
3.4 MCU Tx data mode
Note: 1 The input signal rise and fall times must be within 10ns. 2 Every timing is specified on the basis of 30% and 70% of VDDI. Figure 2. MCU TxData timing Table 9. AC Operation - Internal oscillator Table 10. AC Characteristics for serial interface
3.5 Driver TxData mode
2 The input signal rise and fall times must be within 10ns. 3 Every timing is specified on the basis of 30% and 70% of VDDI. Note: 1 The input signal rise and fall times must be within 10ns. 2 Every timing is specified on the basis of 30% and 70% of VDDI. Table 11. Input signals change time Table 12. Timings based on 4 MHz SCLK speed Table 13. Timings based on 1 MHz SCLK speed
Figure 3. Driver TxData Mode AC timing characteristics
3.5.1 Reset timing
Note: 1 The input signal rise and fall times must be within 10ns. 2 Every timing is specified on the basis of 30% and 70% of VDDI. Table 14. Reset timing
Figure 4. Reset timing
4 Interface
4.1.1 MCU TxData mo de (write mode)
following byte is a command (D/!C =0) or a Display Data Byte (D/!C =1). During data transfer, the data line is sampled by the receiver unit on the SCLK rising edge. after the latching rising edge or on the !CS rising edge. D/!C bit of the next data byte on the next SCLK positive edge. A reset pulse on !RES pin interrupts any transmission. Figure 5. MCU TxData mode
4.1.1.1 Data/command transfer break
interrupted and the interface is forced in reset state. to receive the same byte interrupted re-transmitted or a new command identifier.
Figure 6. 3-lines SPI Data transfer break condition
4.1.1.2 Data/command transfer pause
communication session is definitively closed. Figure 7. 3-lines SPI data transfer pause
4.1.2 Driver TxData Mode (read mode)
The Driver TxData–mode is a method to check the electrical interconnection between LCD driver and baseband, to identify the driver and for VDD Intercfonnection electrical self testing. Self Testing of the electrical contacts is based on the monitoring of VLCD. The improper electrical contact on VDD can be noted from a too low level of VLCD. The serial interface Driver TxData–mode is controlled by three input signals. The serial data output (SDAOUT/Driver TxData) and serial clock input (SCLK) are enabled when !CS is low after having received one Reading Command. To access Driver TxData–mode a Reading command must be sent to STE2007 driver. The first bit (D/C) is low to indicates next 8–bits are for command. The data is read to the driver on the rising edge of SCLK (see section ”MCU TxData–mode”). After last command bit (bit 0) is read SDAOUT becomes active (Low impedance) and MCU is able to read data from driver. SDAOUT is forced in high impedence when !CS line is forced high or after the eight SCLK rising edges from the last SCLK rising edge of teh reading command transfer (Figure 8). After sending out all 8 bits the driver release automatically the bus and go back to the MCU TxData–mode. MCU Txdata line changes from high–z to active low or high in the falling edge of 8th SCLK pulse. !CS must be set high and low again before !D/C writing can continue. If !CS is forced high during the Driver TxDAta-mode, the Driver Tx data session is aborted and SDAOUT is forced in high impedance Mode. SDAOUT and SDAIN line can be short circuited in normal working conditions.
!RES, the serial interface is ready to receive data after the internal reset time.
4.2.1 MCU TxData mo de (write mode)
communication clock on the SCL pin from the master. Information are exchanged byte-wide. During data transfer, the data line is sampled by the receiver unit on the SCL rising edge. read on the eighth SCL clock pulse during every byte transfer. MSB of the next data byte on the next SCL positive edge. Commands bytes are discarded. A reset pulse on !RES pin interrupts any transmission. Figure 10. 4-lines SPI commands transfe Figure 11. 4-lines SPI Video data write cycle
4.2.1.1 Data/command transfer break
interrupted and the interface is forced in reset state. to receive the same byte interrupted re-transmitted or a new command identifier. Figure 12. 4-lines SPI Data Transfer break condition
4.2.1.2 Data/command transfer pause
communication session is definitively closed.
Figure 13. 4-lines SPI Data transfer pause
4.2.2 Driver TxData Mode (read mode)
SDA (output Driver) is in High impedance in steady state and during data write. Figure 14. 4-lines SPI 8-Bit read cycle
4.3 I 2C Bus
(400kHz Clock) and High Speed Mode (3.4MHz). lines must be connected to a positive supply voltage via an active or passive pull-up. – Data transfer may be initiated only when the bus is not busy. Start or Stop Data Transfer condition (see below). BUS not busy: Both data and clock lines remain High.
Start Data Transfer: A change in the state of the data line, from High to Low, while the clock is High, define the START condition. Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock signal is High, defines the STOP condition. Data Valid: The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the High period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer starts with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and the stop conditions is not limited. The information is transmitted byte-wide and each receiver acknowledges with the ninth bit. By definition, a device that gives out a message is called "transmitter", the receiving device that gets the signals is called "receiver". The device that controls the message is called "master". The devices that are controlled by the master are called "slaves" Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA_IN line during the acknowledge clock pulse. Of course, setup and hold time must be taken into account. A master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case, the transmitter must leave the data line High to enable the master to generate the STOP condition. Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line. Having the acknowledge output (SDAOUT) separated from the serial data line is advantageous in Chip-On-Glass (COG) applications. In COG applications where the track resistance from the SDAOUT pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is possible that during the acknowledge cycle the STE2007 will not be able to create a valid logic 0 level. By splitting the SDA input from the output the device could be used in a mode that ignores the acknowledge bit. In COG applications where the acknowledge cycle is required, it is necessary to minimize the track resistance from the SDACK pad to the system SDA line to guarantee a valid LOW level. To be compliant with the I 2C-bus Hs-mode specification the STE2007 is able to detect the special sequence "S00001xxx". After this sequence no acknowledge pulse is generated. Since no internal modification are applied to work in Hs-mode, the device is able to work in Hs-mode without detecting the master code.
Figure 15. Bit transfer and START,STOP conditions definition Figure 16. Acknowledgment on the I 2C-bus
4.3.1 Communication protocol
SA1 inputs to a logic 0 or to a logic 1.
4.3.2 Starting the communication
the type of communication (read or write). Figure 17. Addree byte
4.3.3 MCU TxData M ode (Write Mode)
If the R/W bit is set to logic 0 the STE2007 is set to be a receiver and the master can send commands or data. After the communication has started and slaves have acknowledged, the master sends a control byte defined as follows and waits for its acknowledgement: The Co bit is the control byte MSB and defines if after this control byte will follow a single byte sequence (Co = 1) or a multiple bytes sequence (Co = 0). The D/C bit defines whether the following byte (if Co = 1) or the following stream of bytes (if Co = 0) are command (D/C = 0) or DDRAM data (D/C = 1). Depending on state of flags Co and D/C, four writing sequences are possible: SINGLE COMMAND BYTE SEQUENCE (Co = 1, D/C = 0): a single byte interpreted as a command will follow the control byte; SINGLE DATA BYTE SEQUENCE (Co = 1, D/C = 1): a single byte interpreted as a data to be written in DDRAM will follow the control byte; MULTIPLE COMMAND BYTES SEQUENCE (Co = 0, D/C = 0): a stream of bytes will follow the control byte, with each single byte interpreted as a command; MULTIPLE DATA BYTES SEQUENCE (Co = 0, D/C = 1): a stream of bytes will follow the control byte, with each byte interpreted as a data byte to be written in DDRAM. Every single byte of a sequence must be acknowledged by all addressed units. A multiple data sequence is terminated only by sending a STOP condition on the I 2C bus. When a sequence is terminated, another sequence of any type can follow or a I2C STOP condition can be sent to close the communication. In a single or multiple data bytes sequence, every data byte received is stored in the DDRAM at the location specified by the current values of data pointers. Data pointers are automatically updated after each single data byte written. CONTROL BYTE Co DC 000 000
4.3.4 Driver TxData mode (Read mode)
the D/C bit during the last write access, is set to a logic 0, the byte read is the status byte. Figure 18. Communication protocol
00001 DATA Byte A
4.4 Reading mode
4.4.1 IIdentification byte
Identification byte is an 8 Bit code that identify the module revision Number. Figure 19. Identification byte in reading mode Figure 20. Identification information Table 15. ID byte format
00 I D B P A D I D A P A D 0000
5 Display Data RAM (DDRAM)
5.1 DDRAM and Page/column address circuit
Figure 21. DDRAM vs. display on LCD MCU issues Page address set command to change the page and access to another page. The DDRAM column address is specified by Column address set command. Figure 22. Column address in normal mode
Figure 23. Column address in reversed mode DDRAM in reverse order (from Right to left). Table 16. Column address direction
5.2 Line address circuit
the display, can be specified by Display start line address set command.
Figure 24. M68–line mode
Figure 25. 65–line mode
Figure 26. 49–line mode
Figure 27. 33–line mode
5.3 Partial display
Partial display Area location on the screen is defined by Image Location Parameter. Image Location + Partial display area > Multiplexing rate.
Figure 30. Example: Partial Display 33 lines & MUX68
Figure 31. Example: Partial display 25 lines & MUX65
Figure 32. Partial display 17 lines
Figure 33. Partial display 9 lines
5.4 Command parameters default configuration
Table 17. Command parameters default configuration N-Line inversion Frame Inv. Frame Inv. Frame Inv.
Instruction setups STE2007
6 Instruction setups
6.1 Initialization (power on sequence)
6.2 Display data writing sequence
6.3 Power off
V0-Voltage Range (H) Electronic volume (H) Power saver OFF (Display all points OFF (A4H)) Power control set (2FH) Reset status Power ON Page address set (B*H) Column address set Upper 3-bit address (1*H) Column address set Lower 4-bit address (0*H) Display data write Display ON (AFH) This command is need- ed only at 1st time after initialization. Optional Status VDD - GND Power OFF VDDI - GND Power OFF min.20ms Power Saver Status or Booster OFF Status !RES Pin="Low Level" VDD - GND Power OFF VDDI - GND Power OFF min. 0ms !RES Pin="Low Level"
7 Power on/power off timing sequence
Figure 34 shows the timing diagram for power on/power down sequences. Figure 34. Timing for phone’s power on sequence when VDD,VDDCP Up before VDDI XCS,SDAIN,XRES can become ”High” simultaneously with VDDI (tcs>0,tpi>0;tp2>0). driver is forced in reset state. Figure 35. Timing for phone’s power on sequence when VDDI Up before VDD
Table 18. Instruction Set
Table 18. Instruction Set (continued)
8 Commands
8.1 Display on/off
Table 19. Display on/ofF saver mode is entered. See the section on the Power saver for details.
8.2 Display normal/reverse
This command can reverse the lit and unlit without overwriting the contents of the DDRAM. Table 20. Display normal/reverse
8.3 Display all points on/off
takes priority over the Display normal/reverse command. Table 21. Display all points ON/OFF Power saver mode is entered. See the section on the Power Saver for details.
01 A 7 Reverse:DDRAM Data ”L ”=LCD ON
8.4 Page address set
This command specifies the page address of the DDRAM. very last address (column = 5FH, page = 8H), page address return to 0H. Table 22. Page address set
8.5 Column address set
into two sections (the upper 3–bits and lower 4–bits) when it is set. column address (5FH), column address returns to 00H. Table 23. Column address set
0 A3 A2 A1 A0 Lower bit address
8.6 Display start line address set
This command is used to specify the display start line address of the DDRAM. scrolling, page swapping can be performed. Table 24. Display start line address set
8.7 Segment driver direction select
Table 25. Segment driver direction select
8.8 Common driver direction select
Table 26. Common driver direction select
01 A 1 R e v e r s e
8.9 Display data write
Table 27. Display data write
8.10 Data reading from driver (Driver TxData–mode)
Table 28. ID Byte
8.11 Power Control Set
This command sets the on–chip power supply function ON/OFF . Table 29. Power Control Set
1 Write Data
8.12 VLCD set
For information on VLCD thermal compensation see PAR. 8.18 .
8.12.1 V0R - Voltage Range Set
This command sets a value of the Voltage Range. Table 30. V0R – Voltage Range
Table 31. V0R
8.12.2 VOP set
Contrast Setting Adjustment . Table 32. VOP Set Table 33. VOP
0 V O P 7V O P 6V O P 5V O P 4V O P 3V O P 2V O P 1V O P 0 D a t a F i e l d
11111101 F D - 1 2 5 S t e p
11111110 F E - 1 2 6 S t e p
11111111 F F - 1 2 7 S t e p
8.12.3 Electronic volume
adjust the contrast of LCD panel display (End User). Table 34. Electronic volume Table 35. EV
8.13 Power saver mode
power saver mode is entered. This mode stops every operation of the LCD display system. Figure 38. Power saver mode held, and the MCU can access to the DDRAM and internal registers.
8.14 Reset
Table 36. Reset
8.15 NOP
Table 37. NOP
8.16 Image Location
Table 38. Image Location Table 39. Image Location
8.17 Bias Ratio
It is possible to select different Bias Ratio. Table 40. Bias Ratio Table 41. BIAS Ratio Figure 39. Bias levels Generator
- VLCD
- VLCD
- VLCD
- VLCD R 6 R R R R VLCD VSS
- VLCD
- VLCD
- VLCD
- VLCD R 5 R R R BR=000 BR=001 R VLCD VSS
- VLCD
- VLCD
- VLCD
- VLCD R 4 R R R R VLCD VSS
- VLCD
- VLCD
- VLCD
- VLCD R 3 R R R BR=010 BR=011 R VLCD VSS
- VLCD
- VLCD
- VLCD
- VLCD R 2 R R R R VLCD VSS
- VLCD
- VLCD
- VLCD
- VLCD R 1 R R R BR=100 BR=101 R VLCD VSS
- VLCD
- VLCD
- VLCD
- VLCD R 4 R R R BR=110
8.18 Temperature Compensation
Its is possible to select different VLCD temperature compensation Coefficients. Table 42. VLCD Temperature Compensation Table 43. TC
8.19 Charge Pump Multiplication Factor
It is possible to select different Charge Pump Multiplication Factors. Table 44. Charge Pump Setting
000 T C = 0 P P M
001 T C = - 3 0 0 P P M
010 T C = - 6 0 0 P P M
011 T C = - 9 0 0 P P M
100 T C = - 1 0 7 0 P P M
101 T C = - 1 2 0 0 P P M
110 T C = - 1 5 0 0 P P M
111 T C = - 1 8 0 0 P P M
Table 45. Charge Pump Multiplication Factor
8.20 Refresh Rate
It is possible to select different Refresh Rate. Table 46. Refresh rate setting Table 47. Refresh Rate
8.21 Icon mode
Table 48. Icon Mode
8.22 N- Line inversion
Table 49. N-Line Inversion
8.23 Number of lines
Multiplexing Rate setting command. Table 51. Number of lines Table 52. Multiplexing rate
9 Pad coordinates
See Table 53: Pad coordinates and Table 55: Alignment marks coordinates. Table 50. N-Line
Table 53. Pad coordinates
Table 53. Pad coordinates (continued)
10 Chip mechanical drawing
Figure 40. Alignment marks dimensions Table 54. Mechanical dimensions Table 55. Alignment marks coordinates
Table 56. Order codes Table 57. Document revision history 09-Nov-2005 1 Initial release. Adjustments in Abs Max ratings regarding ESD in Ta bl e 7.