102 X 65 single-chip LCD controller/driver
Document overview
- Manufacturer or author: STMICROELECTRONICS
- PDF pages: 79
Technical content
Datasheet sections
- 1 Block diagram
- 2 Pin description
- 3 Circuit description
- 3.1 Supplies voltages and grounds
- 3.2 Internal supply voltage generator
- 3.3 Oscillator
- 3.4 Master/slave mode
- 3.5 Bias levels
- 3.6 LCD voltage generation
- 3.7 Temperature coefficients
- 3.8 Display data RAM
- 4 Bus interfaces
- 4.1 I2C Interface
- 4.1.1 Communication protocol
- 4.2 Serial interfaces
- 4.3 Parallel interface
- 5 Instruction set
- 5.1 Reset (RES)
- 5.2 Power down (PD = 1)
- 5.3 Memory blanking procedure
- 5.4 Checker board procedure
- 5.5 Scrolling function
- 5.6 Dual partial display
Features
■ 102 x 65 bits display data RAM ■ Programmable MUX rate ■ Programmable frame rate ■ X,Y programmable carriage return ■ Dual partial display mode ■ Row by row scrolling ■ N-line inversion ■ Automatic data RAM blanking procedure ■ Selectable input interface: –I 2C Bus Fast and Hs-mode (read and write) – 8000 and 8080 Parallel Interfaces (read and write) – 3-lines and 4-lines SPI Interface (read and write) – 3-lines 9 bit Serial Interface (read and write) ■ Fully integrated configurable LCD bias voltage generator with: –S e l e c t a b l e multiplication factor (up to 5X) – Effective sensing for high precision output – Eight selectable temperature compensation coefficients ■ CMOS compatible inputs ■ Fully integrated oscillator requires no external components ■ Designed for chip-on-glass (COG) applications. ■ Low power consumption, suitable for battery operated systems ■ Logic supply voltage range from 1.7 to 3.6V ■ High voltage generator supply voltage range from 1.75 to 4.5V ■ Display supply voltage range from 4.5 to 14.5V ■ Backward compatibility with STE2001/2/4
Description
The STE2004S is a low power CMOS LCD controller driver. Designed to drive a 65 rows by 102 columns graphic display, it provides all necessary functions in a single chip, including on-chip LCD supply and bias voltages generators, resulting in a minimum of externals components and in a very low power consumption. STE2004S features six standard interfaces (3-lines Serial, 3-lines SPI, 4-lines SPI, 68000 Parallel, 8080 parallel and I 2C) for interfacing with the host micro-controller. COLUMN DRIVERS ROW DRIVERS DATA LATCHES 65 x 102 RAM DISPLAY CONTROL LOGIC SCROLL LOGIC DATA REGISTER INSTRUCTION REGISTER CO to C101 R0 to R64 VSENSE SLAVE RES VDD1,2 CLOCK TIMING GENERATOR BIAS VOLTAGE GENERATOR HIGH VOLTAGE GENERATOR RESET TEST SHIFT REGISTER VLCD VSS EXT ICON_MODE VSSAUX SAO SDIN/SDA_IN SDA_OUTSCLK/SCL DB0 to DB7
9 Bit SERIAL
D/C CSSA1 SDOUT E/WR R/W- RD I2C BUS 3 & 4 Line SPI Parallel 8080 Parallel 68K SEL 3 SEL 1 SEL 2 TEST_VREF TEST_MODE LR0047 OSCOSC_IN OSC_OUT FR_IN FR_OUT MASTER SLAVE SYNC VLCDSENSE Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s) STE2004S Contents Obsolete Product(s) - Obsolete Product(s)
1 Block diagram
Figure 1. STE2004S block diagram
2 Pin description
Table 1. Pin description VSS 192-203 GND Ground pads. VDD2 164-171 Supply Internal generator supply voltages.
RES 172 I Reset input. Active Low.
174 I Interface data/command selector- cannot be left floating
Table 1. Pin description (continued)
Figure 2. Chip mechanical drawing
Figure 3. Improved ALTH and PLESKO driving method
Obsolete Product(s) - Obsolete Product(s) STE2004S Circuit description
3 Circuit description
3.1 Supplies voltages and grounds
VDD2 supplies voltages to the internal voltage generator (see below). If the internal voltage generator is not used, this should be connected to VDD1 pad. VDD1 supplies the rest of the IC. VDD1 supply voltage could be different form VDD2.
3.2 Internal supply voltage generator
The IC has a fully integrated (no external capacitors required) charge pump for the liquid crystal display (LCD) supply voltage generation. The multiplying factor can be programmed to be: Auto, X5, X4, X3, X2, using the ’set CP multiplication’ command. If auto is set, the multiplying factor is automatically selected to have the lowest current consumption in every condition, allowing an input voltage that changes over time and a constant V LCD voltage. The output voltage (VLCD) is tightly controlled through the VLCDSENSE pad. For this voltage, eight different temperature coefficients (TC, rate of change with temperature) can be programmed using the bits TC1, TC0, T2, T1, T0, to ensure there is no contrast degradation over the LCD operating range. An external supply could be connected to V LCD to supply the LCD without using the internal generator. In such event the internal voltage generator must be programmed to zero (PRS = [0;0], Vop = 0 - reset condition) and the charge pump (CP[0;0]) set to 5x or quto mode.
3.3 Oscillator
A fully integrated oscillator (requires no external components) is present to provide the clock for the display system. When used the OSC pad must be connected to V DD1 pad. An external oscillator could be used and fed into the OSC pin. If an external oscillator is used, it must be always present when STE2004S is not in power down mode. An oscillator out is provided on the OSCOUT Pad to cascade two or more drivers.
3.4 Master/slave mode
STE2004S supports the master slave working mode for both control logic and charge pump. This function allows to drive matrix such as 204x65 or 102x130 using two synchronized STE2004S and the internal charge pump of both devices. If M/S is connected to VDD1, the driver is configured to work in master mode. When STE2004S is in master mode, the Vsense_Slave pin is disabled and the VLCD value can be controlled using Vop bits. The master time generator outputs the relevant timing references on FR_OUT and OSC_OUT. If M/S is connected to GND, the driver is configured to work in slave mode. When STE2004S is in slave mode, the VLCD configuration set by Vop registers and the thermal compensation slope set by TC register, are neglected. The VLCD value generated is equal to the voltage value present on the Vsense_Slave pin so the slave configuration can follow VDD2 2V L C D⋅ Obsolete Product(s) - Obsolete Product(s)
pump to be in off state whatever is the value of Vsense_aux. into power down state before master device. Figure 4. Master slave logic connection with frame synchronization Figure 5. Master slave logic connection without frame synchronization
3.5 Bias levels
Figure 6. Bias level generator Table 2. Bias ratio programmable bits
- VLCD
- VLCD
- VLCD
- VLCD n + 3 n + 4 R nR R R n + 2 n + 4 n + 4 n + 4 D00IN1150 nm 3 –= Obsolete Product(s) - Obsolete Product(s)
3.6 LCD voltage generation
and PRS bits are set to zero the internal voltage generator is switched off. Table 3. Bias level m=65 and m=49 Table 4. LCD voltage generation
6.85 V th Ai–⋅()
3.7 Temperature coefficients
are available through the basic instruction set. Figure 7. Temperature coefficients Table 5. Temperature coefficients with basic instruction set Table 6. Temperature coefficients
Obsolete Product(s) - Obsolete Product(s) Circuit description STE2004S
3.8 Display data RAM
The STE2004S, provides an 102X65 bits static RAM to store display data. This is organized into 9 (Bank0 to Bank8) banks with 102 bytes. One of these banks can be used for icons. RAM access is accomplished in either one of the bus interfaces provided (see below). Allowed addresses are X0 to X101 (Horizontal) and Y0 to Y8 (Vertical). There are four address mode provided to write to RAM:
- Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on the left of the memory map. The X pointer is increased after each byte written. After the last column address (X=X-Carriage), Y address pointer jumps to the following bank and X restarts from X=0. ( Figure 8.)
- Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the left of the memory map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y -Carriage), X address pointer jumps to next column and Y restarts from Y=0 ( Figure 9).
- Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on the right of the memory map. The X pointer is increased after each byte written. After the last column address (X=X-Carriage), Y address pointer jumps to the next bank and X restarts from X=0 ( Figure 10.).
- Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the right of the memory map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y -Carriage), the X pointer jumps to next column and Y restarts from Y=0 ( Figure 11.). After the last allowed address (X;Y)=(X-Carriage; Y -Carriage), the address pointers always Data bytes in the memory could have the MSB either on top (D0 = 0, Figure 16.) or on the bottom (D0=1, Figure 17.). The STE2004S also allows the normal output address to be altered. The display is mirrored along the X axis if a logic one MY bit is set. Only the memory read process is altered, the content is not affected in memory. When ICON MODE=1 the icon row is not mirrored with MY and is not scrolled. When ICON MODE=0 the icon row is like an other graphic line and is mirrored and scrolled. When the partial display mode is disabled, there are three multiplex ratios available (MUX 33, MUX 49 and MUX 65). Only a subset of writable rows are output on row drivers in MUX 33,49 and 65 modes. When Y-Carriage<MUX/8, if MUX 49 is selected only the first 49 memory rows are visualized; if MUX 33 selected, only the first 33 memory rows. The unused output row and column drivers must be left floating. When Y-Carriage<=MUX/8 the icon bank is located to BANK 8 in MUX 65 Mode, to BANK6 in MUX 49 Mode, and to BANK 4 in MUX 33 Mode. In MUX 33 and MUX 49 modes and Y-Carriage>MUX/8, only lines 33 and 49 are visualized. The lines of DDRAM connected on the output drivers using the scrolling function (Range: 0- Y -Carriage*8) are selectable. When Y-Carriage>MUX/8 lines, the icon row is moved in DDRAM to the first row of the bank, corresponding to the Y -CARRIAGE Return value, being always connected on the same output Driver. Obsolete Product(s) - Obsolete Product(s)
Figure 18. Memory rows vs. row drivers mapping ICON_MODE=1 and MUX 65
Figure 19. Memory rows vs. row drivers mapping ICON_MODE=0 and MUX 65
Figure 20. Memory rows vs. Row drivers mapping ICON_MODE=1, Y-Carriage<=6 and
Figure 21. Memory rows vs. row drivers ;apping ICON_MODE=0, Y-Carriage<=6 and
Figure 22. Memory rows vs. row drivers mapping ICON_MODE=0, Y-carriage=7,
Figure 23. Memory rows vs. row drivers mapping ICON_MODE=1, Y-Carriage=7,
Figure 24. Memory rows vs. row drivers mapping ICON_MODE=1, Y-carriage=8,
Figure 25. Memory rows vs. row drivers mapping ICON_MODE=0, Y-carriage=8,
Figure 26. Memory rows vs. row drivers mapping ICON_MODE=1, Y-carriage<=4 and
Figure 27. Memory rows vs. row drivers mapping ICON_MODE=0, Y-carriage<=4 and
Figure 30. Row drivers vs. LCD panel interconnection in MUX33 mode
4 Bus interfaces
(connect to VDD). All the I/O pins of the unused interfaces must be connected to GND. All interfaces work while the STE2004S is in power down.
4.1 I 2C Interface
(400kHz Clock) and High Speed Mode (3.4MHz). lines must be connected to a positive supply voltage via an active or passive pull-up. – Data transfer may be initiated only when the bus is not busy. BUS not busy: Both data and clock lines remain High. is High, define the START condition. signal is High, defines the STOP condition. Each data transfer is initiated with a start condition and terminated with a stop condition. Table 7. Bus interfaces
000 I 2C Read and write; fast and
an extra acknowledge related clock pulse. master to generate the STOP condition. Connecting SDA_IN and SDA_OUT together the SDA line become the standard data line. SDACK pad to the system SDA line to guarantee a valid LOW level. special sequence "S00001xxx". After this sequence no acknowledge pulse is generated. Hs-mode without detecting the master code. Figure 31. Bit transfer and st art,stop conditions definition
Figure 32. Acknowledgment on the I2C-bus
4.1.1 Communication protocol
acknowledge, one or more command word follows to define the status of the device. Every byte of a command word must be acknowledged by all addressed units. Every byte must be acknowledged by all addressed units.
the D/C bit during the last write access is set to a logic 0, the byte read is the status byte. Figure 33. Communication protocol
4.2 Serial interfaces
possible to select a 3-lines SPI, a 4-lines SPI or 3-line 9 bits serial interface. clock signals (SCLK), one for the peripheral enable (CS ) and one for mode selection (SD/C). peripheral power consumption is zero. While CS pin is high the serial interface is kept in reset. line is read on the eighth SCLK clock pulse during every byte transfer. the next byte at the next SCLK positive edge. the internal registers are cleared. If CS is low after the positive edge of RES, the serial interface is ready to receive data.
Figure 37. 4-lines SPI reading sequence (SCLK) and one for peripheral enable (CS). words follow to define the status of the device.
Figure 39. and Figure 40.. without any additional line. Figure 38. 3-lines serial interface protocol in writing mode Figure 39. 3-lines SPI interface protocol in reading mode
0 DATA Byte
Figure 40. 3-lines SPI reading sequence (SCLK) and one for peripheral enable (CS). =1). During data transfer, the data line is sampled on the positive SCLK edge.
- and Figure 44.. SDOUT is in high impedance in steady state and during data write.
Figure 44. 3-lines serial reading sequence
4.3 Parallel interface
both an 8-bits bi-directional link between the display driver and the application supervisor. Both parallel interfaces can be read the I2C driver slave address or the status byte. While CS pin is high the 68000 parallel interface is kept in reset. If R/W line is set to 0, data is latched on the E falling edge. bus is set in high impedance mode when E is set to logic 0. The I2C address or status byte is output on D0-D7 bus, according to R bit value.
5 Instruction set
–W i t h D / C set to LOW : commands are sent to the control circuitry. –W i t h D / C set to HIGH : the data RAM is addressed. pad must be connected to a logic HIGH (connect to VDD1). Table 8. (basic-set) and Table 9. (extended set). Table 8. STE2001/2-like instruction set
Table 9. Extended instruction set
00001 M X M Y P D H [ 1 ] H [ 0 ]
00000001 F R 1 F R 0 F r a m e r a t e c o n t r o l
00000010 M [ 1 ] M [ 0 ] M U X r a t i o
0001 PDY5 PDY4 PDY3 PDY2 PDY1 PDY0 1st Sector start
001 PDY6 PDY5 PDY4 PDY3 PDY2 PDY1 PDY0 2nd Sector start
0000000001 S c r o l l i n g p o i n t e r r e s e t
0000001 T 2 T 1 T 0 Set temperature
000001 N W 3 N W 2 N W 1 N W 0 N - L i n e i n v e r s i o n
Table 10. Explanations of Table 8 and Table 9 symbols Table 11. Page selection
00 P a g e 0
10 P a g e 2
11 P a g e 3
Table 12. Display mode
00 D i s p l a y b l a n k
Table 13. Frame rate control
Table 14. Vlcd range selection Table 15. Multiplexing ratio Table 16. Temperature coefficient (T0, T1, T2) Table 17. Temperature coefficient (TC0, TC1)
Table 18. Charge pump multiplication factor Table 19. Bias ratio Table 20. Y Carriage return register
5.1 Reset (RES )
Table 10. All on-going communication with the host controller is interrupted if a load the reset configuration into the internal registers. A memory blank instruction can be used to clear the DDRAM content. Table 21. Partial display configuration Table 22. N-Line inversion
Obsolete Product(s) - Obsolete Product(s) STE2004S Instruction set
5.2 P ower down (PD = 1)
At power down, all LCD outputs are kept at VSS (display off). Bias generator and VLCD generator are off (VLCDOUT output is discharged to VSS, and then VLCDOUT can be disconnected). The internal oscillator is in off state. An external clock can be provided. The RAM contents is not cleared.
5.3 Memory blanking procedure
This instruction fills the memory with "blank" patterns, in order to delete patterns randomly generated in memory when starting up the device. It substitutes (102X8) single "write" instructions. The procedure can only be programmed if: PD bit = 0 No instruction can be programmed for a period equivalent to 102X8 internal write cycles (102X8X1/fclock). The start of the memory blanking procedure is between one and two fclock cycles from the last active edge (E falling edge for the parallel interface, last SCLK rising edge for the serial and SPI interfaces, last SCL rising edge for the I 2C interface).
5.4 Checker board procedure
This instruction fills the memory with "checker-board" pattern, allowing developers to create a complex module test configuration using one instruction. It can only be programmed if: PD bit = 0 No instruction can be programmed for a period equivalent to 102X8 internal write cycles (102X8X1/fclock). The start of checker-board procedure is between one and two fclock cycles from the last active edge (E falling edge for the parallel interface, last SCLK rising edge for the serial and SPI interfaces, last SCL rising edge for the I 2C interface).
5.5 Scrolling function
The STE2004S can scroll the graphics display in units of raster-rows. The scrolling function changes the correspondence between the rows of the logical memory map and the output row drivers. The scroll function does not affect the data ram contentm it is only related to the visualization process. The information output on the drivers is related to the row reading sequence (the 1st row read is output on R0, the 2nd on R1 and so on). Scrolling means reading the matrix starting from a row that is sequentially increased or decreased. After every scrolling command the offset between the memory address and the memory scanning pointer is increased or decreased by one. The offset range changes in accordance with MUX Rate. After 64th/65th scrolling commands in MUX 65 mode, or after the 48th/49th scrolling commands in MUX 49 mode, or after 32nd/33rd scrolling command in MUX 33 mode, the offset between the memory address and the memory scanning pointer is again zero (Cyclic Scrolling). A Reset Scrolling Pointer instruction can be executed to force the offset between the memory address and the memory scanning pointer to zero. If ICON MODE =1, the Icon Row is not scrolled. If ICON MODE=0 the last row is like a general purpose row and it is scrolled as other lines. Obsolete Product(s) - Obsolete Product(s)
one and the raster is scrolled from bottom-up.
5.6 Dual partial display
programmable. The icon row is accessed last in each partial display frame. Figure 54. To setup partial display sectors start qddress and partial display mode no particular instruction flow has to be followed. Figure 53. Dual partial display enabling instruction flow Table 23. Scrolling function
Figure 54. Dual partial display mode configuration or duty change Table 24. Partial display configurations END OF PARTIAL DISPLAY CONFIG.
6 ID-number
one LCD module with different configuration parameters can be managed on one platform.
- All have the first 6 bits (001111) in common. The two least significant bits can be
used to connect the SA0 and SA1 inputs to a VSS or VDD1. Figure 55. I2C interface interconnection in master/ slave mode Figure 56. I3-lines SPI and 3-lines serial interfaces interconnection in master slave
Figure 57. 4-lines SPI interface interconnection in master slave mode Figure 58. 8080-series and 68000-series interface interconnection in master slave
8 LINES 8 LINES
Figure 67. Power-ON timing diagram
Figure 68. Power-OFF timing diagram
Figure 69. Initialization with built-in booster END OF NORMAL DISPLAY MODE CONFIG.
Figure 70. Data RAM to display mapping Table 25. Test pin configuration
7 Electrical characteristics
7.1 Absolute maximum ratings
7.2 DC operation
Table 26. Absolute maximum ratings
- Device behavior and characterization are m easured over this temperature range during internal qualification of the product.
During production testing, however, devic e performance is measured at a fixed ambient temperature - typically 25°C. Table 27. DC operation
Table 27. DC operation (continued)
- The maximum possible V LCD voltage that can be generated is dependent on vo ltage, temperature and (display) load.
- When f sclk = 0 there is no interface clock.
- If external V LCD, the display load current is not transmitted to I DD
- Tolerance depends on the temperat ure; (typically zero at Tamb = 25°C), maximum tolerance values are measured at the
- Power-down mode. During power-down al l static currents are switched-off.
7.3 AC operation
Table 28. AC operation
- For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
- All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and
- Cb is the capacitive load for each bus line.
Figure 75. Serial interface timing
8 Pad coordinates
See Table 29: Pad coordinates and Table 30: Alignment marks coordinates.
Table 29. Pad coordinates
- I 2C bus AC characteristics are tested by correlation
Table 30. Alignment marks coordinates
Figure 76. Alignment marks dimensions Table 31. Bumps Table 32. Die mechanical dimensions
9 Ordering information
Table 33. Ordering information Table 34. Document revision history 24-Jan-2006 1 Initial release. ratings set to: -25 to + 85 and added a footnote. – Ordering information moved from cover page to Chapter 9. 31-Jan-2007 3 Added Chapter 1: Block diagram and corrected the document title.