STE2004

STE2004 STMICROELECTRONICS | Alldatasheet

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Technical content

1 FEATURES

• I2C Bus Fast and Hs-mode (read and write)  68000 & 8080 Parallel Interfaces (read and write)  3-lines and 4-lines SPI Interface (read and write)  3-lines 9 bit Serial Interface (read and write) ■ Fully Integrated Oscillator requires no external components ■ CMOS Compatible Inputs ■ Fully Integrated Configurable LCD bias voltage generator with:  Selectable multiplication factor (up to 5X)  Effective sensing for High Precision Output  Eight selectable temperature compensation coefficients ■ Designed for chip-on-glass (COG) applications. ■ Low Power Consumption, suitable for battery operated systems ■ Logic Supply Voltage range from 1.7 to 3.6V ■ High Voltage Generator Supply Voltage range from 1.75 to 4.5V ■ Display Supply Voltage range from 4.5 to 14.5V ■ Backward Compatibility with STE2001/2

2 DESCRIPTION

Table 1. Order Codes

102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER

Figure 1. Block Diagram

9 Bit SERIAL

Table 2. Pin Description VSS 192-203 GND Ground pads. VDD2 164-171 Supply Internal Generator Supply Voltages.

RES 172 I Reset Input. Active Low. CS 173 I Serial & Parallel Interfaces ENABLE. When Low the Incoming Data are Clocked In. FR_OUT 211 O Master Slave Frame Inversion Synchronization. FR_IN 143 I Master Slave Frame Inversion Synchronization. Table 2. Pin Description (continued)

Figure 2. Chip Mechanical Drawing

Figure 3. Improved ALTH & PLESKO Driving Method

3 CIRCUIT DESCRIPTION

3.1 Supplies Voltages and Grounds

VDD2 is supply voltages to the internal voltage generator (see below). If the internal voltage generator is not used, this should be connected to VDD1 pad. VDD1 supplies the rest of the IC. VDD1 supply voltage could be different form VDD2 .

3.2 Internal Supply Voltage Generator

The IC has a fully integrated (no external capacitors required) charge pump for the Liquid Crystal Display supply voltage generation. The multiplying factor can be programmed to be: Auto, X5, X4, X3, X2, using the ’set CP Multiplication’ Command. If Auto is set, the multiplying factor is automatically selected to have the lowest current consumption in every condition. This make possible to have an input voltage that chang- es over time and a constant V LCD voltage. The output voltage (VLCD ) is tightly controlled through the VL- CDSENSE pad. For this voltage, eight different temperature coefficients (TC, rate of change with temperature) can be programmed using TC1 & TC0 or T2, T1 and T0 bits. This will ensure no contrast degradation over the LCD operating range. An external supply could be connected to V LCD to supply the LCD without using the internal generator. In such event the internal voltage generator must be programmed to zero (PRS = [0;0], Vop = 0 - Reset con- dition) and the Charge pump (CP[0;0]) set to 5x or Auto Mode.

3.3 Oscillator

A fully integrated oscillator (requires no external components) is present to provide the clock for the Dis- play System. When used the OSC pad must be connected to VDD1 pad. An external oscillator could be used and fed into the OSC pin.If an external oscillator is used, it must be always present when STE2004 is not in power down mode. An oscillator out is provided on the OSCOUT Pad to cascade two or more drivers.

3.4 Master/Slave Mode

STE2004 support the Master Slave working Mode for Both Control Logic and Charge Pump. This function allows to drive matrix such as 204x65 or 102x130 using two synchronized STE2004 and the internal Charge Pump of both device. If M/S is connected to VDD1, the driver is configured to work in Master Mode. When STE2004 is in Master Mode the Vsense_Slave Pin is disabled and is possible to control the VLCD value using Vop Bits. The Master Time Generator outputs on FR_OUT and on OSC_OUT the relevant timing references. If M/S is connected to GND, the driver is configured to work in Slave Mode. When STE2004 is in Slave Mode, the VLCD configuration set by Vop registers and the thermal compensation slope set by TC register are neglected. The VLCD Value generated is equal to the Voltage value present on Vsense_Slave Pin so the slave configuration can follow the master configuration. The only recognized configuration is Vop=0 that forces the Charge Pump to be in off state whatever is the value of Vsense_aux. To Synchronize the Master & Slave timing circuits, the slave driver FR_IN pad must be connected to Mas- ter Driver FR_OUT pad and Slave Driver OSC_IN pad must be connected to the master driver OSC_OUT Pad (Fig. 4). This connection ensure a synchronization at both Frame level (R0 on the master is driven together with the Slave R0 driver) and at Oscillator Level (same Frame frequency on the master and on the slave). If the Synchronization at Frame level is not required, FR_IN pin must be connected toVDD1 or to VDD1_aux (Fig. 5). During Power Up Procesure, Master device must be forced to exit from power down before the slave de- vice. To enter in PowerDown Mode, Slave Device must be forced in Power Down state before Master De- vice. V DD2 2V L C D⋅

Figure 4. Master Slave Logic Connection with frame Synchronization Figure 5. Master Slave Logic Connection without frame Synchronization

3.5 Bias Levels

To properly drive the LCD, six (Including VLCD and VSS) different voltage (Bias) levels are generated. Figure 6. Bias level Generator For m = 65, n = 5 and an 1/9 ratio is set. For m = 49, n =4 and an 1/8 ratio is set.

• VLCD
• VLCD
• VLCD
• VLCD n + 3 n + 4 R nR R R n + 2 n + 4 n + 4 n + 4 D00IN1150 nm 3 –=

Table 3. The following table Bias Level for m = 65 and m = 49 are provided: Table 4.

3.6 LCD Voltage Generation

The LCD Voltage at reference temperature (To = 27°C) can be set using the VOP register content according to the following formula: VLCD (T=To) = VLCD o = (Ai+VOP · B) (i=0,1,2) with the following values: Note that the three PRS values produce three adjacent ranges for VLCD. If the VOP register and PRS bits are set to zero the internal voltage generator is switched off. The proper value for the VLCD is a function of the Liquid Crystal Threshold Voltage (Vth) and of the Mul- tiplexing Rate. A general expression for this is: For MUX Rate m = 65 the ideal VLCD is: VLCD(to) = 6.85 · Vth than: BS2 BS1 BS0 n 0007 0016 0105 0114 1003 1012 1101 1110 Symbol m = 65 (1/9) m = 49 (1/8) V1 V LCD VLCD V2 8/9*V LCD 7/8*VLCD V3 7/9*V LCD 6/8*VLCD V4 2/9*V V LCD 2/8*VLCD V5 1/9 *V LCD 1/8*VLCD V6 V SS VSS Symbol Value Unit Note Ao 2.95 V PRS = [0;0] A1 6.83 V PRS = [0;1] A2 10.71 V PRS = [1;0] B 0.0303 V To 27 °C V LCD 1m+ 21 1 m ⋅ V op

6.85 Vth A i–⋅()

3.7 Temperature Coefficients

As the viscosity, and therefore the contrast, of the LCD are subject to change with temperature, there's the need to vary the LCD Voltage with temperature. STE2004 provides the possibility to change the VLCD in a linear fashion against temperature with eight different Temperature Coefficient selectable through T2, T1 and T0 bits. Only four of them are available through basic instruction set. Table 5. Table 6. Figure 7. Finally, the VLCD voltage at a given (T) temperature can be calculated as: VLCD (T) = VLCD o · [1 + (T-To) · TC] NAME TC1 TC0 Value Unit TC0 0 0 -0.0· 10-3 1/ °C TC2 0 1 -0.7 · 10-3 1/°C TC3 1 0 -1.05· 10-3 1/°C TC6 1 1 -2.1 · 10-3 1/°C NAME T2 T1 T0 Value Unit TC0 0 0 0 -0.0· 10-3 1/ °C TC1 0 0 1 -0.35 · 10-3 1/°C TC2 0 1 0 -0.7 · 10-3 1/°C TC3 0 1 1 -1.05· 10-3 1/°C TC4 1 0 0 -1.4 · 10-3 1/°C TC5 1 0 1 -1.75· 10-3 1/°C TC6 1 1 0 -2.1 · 10-3 1/°C TC7 1 1 1 -2.3· 10-3 1/°C 00h 01h 02h 03h 04h 05h …. 7Fh 00h 01h 02h7Ch 7Dh 7Eh 03h 04h 7Dh 7Eh 7Fh05h …. 7Ch A 1 A 1 B A 0 + B PRS = [0;0] PRS = [0;1] V O V LCD 00h 01h 02h 03h 04h 7Dh 7Eh 7Fh 05h 7Ch PRS = [1;0] A 2

3.8 Display Data RAM

The STE2004, provides an 102X65 bits Static RAM to store Display data. This is organized into 9 (Bank0 to Bank8) banks with 102 Bytes. One of these Banks can be used for Icons. RAM access is accomplished in either one of the Bus Interfaces provided (see below). Allowed addresses are X0 to X101 (Horizontal) and Y0 to Y8 (Vertical). When writing to RAM, four addressing mode are provided:  Normal Horizontal (MX=0 and V=0), having the column with address X= 0 located on the left of the mem- ory map. The X pointer is increased after each byte written. After the last column address (X=X-Car- riage), Y address pointer is set to jump to the following bank and X restarts from X=0. (Fig. 8)  Normal Vertical (MX=0 and V=1), having the column with address X= 0 located on the left of the memory map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Carriage), X address pointer is set to jump to next column and Y restarts from Y=0 (Fig. 9).  Mirrored Horizontal (MX=1 and V=0), having the column with address X= 0 located on the right of the memory map. The X pointer is increased after each byte written. After the last column address (X=X- Carriage), Y address pointer is set to jump to the next bank and X restarts from X=0 (fig. 10).  Mirrored Vertical (MX=1 and V=1), having the column with address X= 0 located on the right of the mem- ory map. The Y pointer is increased after each byte written. After the last Y bank address (Y=Y-Car- riage), the X pointer is set to jump to next column and Y restarts from Y=0 (fig. 11). After the last allowed address (X;Y)=(X-Carriage; Y-Carriage), the address pointers always jump to the cell with address (X;Y) = (0;0) (Fig. 12,13,14 & 15). Data bytes in the memory could have the MSB either on top (D0 = 0, Fig.16) or on the bottom (D0=1, Fig. 17). The STE2004 provides also means to alter the normal output addressing. A mirroring of the Display along the X axis is enabled setting to a logic one MY bit.This function doesn't affect the content of the memory map. It is only related to the memory read process. When ICON MODE=1 the Icon Row is not mirrored with MY and is not scrolled. When ICON MODE=0 the Icon Row is like an other graphic line and is mirrored and scrolled. Three are the multiplex ratio available when the partial display mode is disabled (MUX 33, MUX 49 and MUX 65). Only a subset of writable rows are output on Row drivers in MUX 33,49 & 65 Mode. When Y-Carriage<MUX/8, if Mux 49 is selected only the first 49 memory rows are visualized; if Mux 33 is selected only the first 33 memory rows are visualized. The unused output row & column drivers must be left floating. When Y-Carriage<=MUX/8 the icon Bank is located to BANK 8 in MUX 65 Mode, to BANK6 in MUX 49 Mode and to BANK 4 in MUX 33 Mode. In Mux 33 & 49 Mode, when Y-Carriage>MUX/8 lines only 33, 49 lines are visualized. It is possible to select which lines of DDRAM are connected on the output drivers using the scrolling func- tion (Range: 0-Y-Carriage*8). When Y-Carriage>MUX/8 lines, the icon row is moved in DDRAM to the first row of the Bank correspondant to Y-CARRIAGE Return value, being always connected on the same output Driver. When MY=0 , the icon Row is output on R64 in mux 65 mode, on R56 in MUX 49 and on R48 in MUX33. When MY=1 , and ICON MODE=0 , the icon Row is output on R0 whatever is the MUX Rate.

Figure 18. Memory Rows vs. Row Drivers Mapping ICON_MODE=1 and MUX 65

Figure 19. Memory Rows vs. Row Drivers Mapping ICON_MODE=0 and MUX 65

Figure 20. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage<=6 and MUX 49

Figure 21. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage<=6 and MUX 49

Figure 22. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage=7, Scrolling Pointer>07h and MUX 49

Figure 23. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage=7, Scrolling Pointer>07h and MUX 49

Figure 24. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage=8, Scrolling Pointer<10h and MUX 49

Figure 25. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage=8, Scrolling Pointer<10h and MUX 49

Figure 26. Memory Rows vs. Row Drivers Mapping ICON_MODE=1, Y-Carriage<=4 and MUX33

Figure 27. Memory Rows vs. Row Drivers Mapping ICON_MODE=0, Y-Carriage<=4 and MUX 33

Figure 30. Row Drivers vs. LCD Panel Interconnection in MUX33 Mode

4 BUS INTERFACES

To provide the widest flexibility and ease of use the STE2004 features Six different methods for interfacing the host Controller. To select the desired interface the SEL1, SEL2 and SEL3 pads need to be connected to a logic LOW (connect to GND) or a logic HIGH (connect to VDD). All the I/O pins of the unused inter- faces must be connected to GND. All interfaces are working while the STE2004 is in Power Down. Table 7. 4.1 I 2C Interface The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast (400kHz Clock) and High Speed Mode (3.4MHz). This bus is intended for communication between different Ics. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via an active or passive pull-up. The following protocol has been defined: - Data transfer may be initiated only when the bus is not busy. - During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined: BUS not busy: Both data and clock lines remain High. Start Data Transfer: A change in the state of the data line, from High to Low, while the clock is High, de- fine the START condition. Stop Data Transfer: A Change in the state of the data line, from low to High, while the clock signal is High, defines the STOP condition. Data Valid: The state of the data line represents valid data when after a start condition, the data line is stable for the duration of the High period of the clock signal. The data on the line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data bytes transferred between the start and the stop conditions is not limited. The information is transmit- ted byte-wide and each receiver acknowledges with the ninth bit. By definition, a device that gives out a message is called "transmitter", the receiving device that gets the signals is called "receiver". The device that controls the message is called "master". The devices that are controlled by the master are called "slaves" Acknowledge. Each byte of eight bits is followed by one acknowledge bit. This acknowledge bit is a low level put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master receiver must generate an acknowledge after the reception of each byte that has been clocked SEL3 SEL2 SEL1 Interface Note

000 I2C Read and Write; Fast and

0 0 1 SPI 4 lines 8 bit Read and Write 0 1 0 SPI 3 lines 8 bit Read and Write 0 1 1 Serial 3 lines 9 bit Read and Write 1 0 0 Parallel 8080-series Read and Write 1 0 1 Parallel 68000-series Read and Write

master to generate the STOP condition. quence "S00001xxx". After this sequence no acknowledge pulse is generated. out detecting the master code. Figure 31. Bit transfer and START,STOP conditions definition Figure 32. Acknowledgment on the I2C-bus

4.1.1 Communication Protocol

more command word follows to define the status of the device. (D/C = 1 RAM Data, D/C = 0 Command). following data byte will be stored in the data RAM at the location specified by the data pointer. Every byte of a command word must be acknowledged by all addressed units. dated after every byte written and in the end points to the last RAM location written. Every byte must be acknowledged by all addressed units. during the last write access, is set to a logic 0, the byte read is the status byte. Figure 33. Communication Protocol

4.2 SERIAL INTERFACES

a 3-lines SPI, a 4-lines SPI or 3-line 9 bits Serial Interface. STE2004 4-lines serial interface is a bidirectional link between the display driver and the application supervisor. ripheral enable (CS) and one for mode selection (SD/C). consumption is zero. While CS pin is high the serial interface is kept in reset. Information are exchanged byte-wide. During data transfer, the data line is sampled on the positive SCLK edge.

Figure 37. 4-lines SPI Reading Sequence define the status of the device. to update the instruction set page number using only the related instruction in the instruction Set. following data byte will be stored in the data RAM at the location specified by the data pointer. updated after every byte written and in the end points to the last RAM location written. that allows to read I2C slave address or the Status byte is reported in Fig. 39 & 40. SDOUT is in High impedance in steady state and during data write.

Figure 38. 3-lines serial interface protocol in Writing Mode Figure 39. 3-lines SPI interface protocol in Reading Mode

0 DATA Byte

Figure 40. 3-lines SPI Reading Sequence power consumption is zero. While CS pin is high the serial interface is kept in reset. fer, the data line is sampled on the positive SCLK edge. next word at the next SCLK positive edge. ternal registers are cleared. If CS is low after the positive edge of RES, the serial interface is ready to receive data. in steady state and during data write. It is possible to short circuit SDOUT and SDIN and read I2C address or status byte without any additional line.

4.3 Parallel Interface

directional link between the display driver and the application supervisor. 2C driver slave address or the Status Byte. If CS is low after the positive edge of RES, the 68000 parallel interface is ready to receive or transmit data. While CS pin is high the 68000 Parallel interface is kept in reset.

4.3.2 Write Mode

If R/W line is set to 0 Data are latched on E falling edge.

4.3.3 Read Mode

ance mode when E is set to logic 0. Accordingly to R bit value I2C Address or Status Byte is output on D0-D7 bus. Figure 45. 68000-series Parallel interface protocol - one byte transmission Figure 46. 68000-series Parallel interface bus protocol - Several bytes transmission

5 INSTRUCTION SET

Two different instructions formats are provided: - With D/C set to LOW : commands are sent to the Control circuitry. - With D/C set to HIGH : the Data RAM is addressed. Two different instruction set are embedded: the STE2001-like instruction set and the extended instruction set. To select the STE2001-like instruction set the EXT pad has to be connected to a logic LOW (connect to GND). To select the he extended instruction the EXT pad has to be connected to a logic HIGH (connect to VDD1). The instructions have the syntax summarized in Table 1 (basic-set) and Table 2 (extended set)

5.1 Reset (RES

At power-on, all internal registers are configured with the default value. The RAM content is not defined. A Reset pulse on RES pad (active low) re-initialize the internal registers content (see Tables 3,4,5,&6). Every on-going communication with the host controller is interrupted, applying a reset pulse. After the power-on, the Software Reset instruction can be used to re-load the reset configuration into the internal registers. The Default configurations is: A MEMORY BLANK instruction can be executed to clear the DDRAM content. 5.2 P ower Down (PD = 1) When at Power Down, all LCD outputs are kept at VSS (display off). Bias generator and VLCD generator are OFF (VLCDOUT output is discharged to VSS , and then is possible to disconnect VLCDOUT ). The internal Oscillator is in off state. An external clock can be provided. The RAM contents is not cleared.

5.3 Memory Blanking Procedure

This instruction allows to fill the memory with "blank" patterns, in order to delete patterns randomly gener- ated in memory when starting up the device. This instruction substitutes (102X8) single "write" instruc- tions. It is possible to program "Memory Blanking Procedure" only under the following conditions: - PD bit = 0 No instruction can be programmed for a period equivalent to 102X8 internal write cycles (102X8X1/fclock). The start of Memory blanking procedure will be between one and two fclock cycles from the last active edge (E fallig edge for the parallel interface, last SCLK rising edge for the Serial & SPI interfaces, last SCL rising edge for the I 2C interface).

5.4 Checker Board Procedure

This instruction allows to fill the memory with "checker-board" pattern. It is mainly intended to developers, who can now simply obtain complex module test configuration by means of a single instruction. It is pos- sible to program "Checker Board Procedure" only under the following conditions: - PD bit = 0 - Horizontal addressing (V = 0) - Normal instruction set (H[1:0] = 0) - Normal display (MX = MY = 0) - Display blank (E = D = 0) - Address counter X[6: 0] = 0 and Y[4: 0] = 0 - Temperature coefficient (TC[1: 0] = 0) - Bias system (BS[2: 0] = 0) - Multiplexing Ratio (M[1:0]=0 - MUX 65) - Frame Rate (FR[1:0]=”75Hz”) - Power Down (PD = 1) - Dual Partial Display Disabled (PE=0) - V OP =0 - Y-CARRIAGE=8 - X-CARRIAGE=101

No instruction can be programmed for a period equivalent to 102X8 internal write cycles (102X8X1/fclock). The start of Checker-board procedure will be between one and two fclock cycles from the last active edge (E falling edge for the parallel interface, last SCLK rising edge for the Serial & SPI interfaces, last SCL rising edge for the I 2C interface).

5.5 Scrolling Function

The STE2004 can scroll the graphics display in units of raster-rows. The scrolling function is achieved changing the correspondence between the rows of the logical memory map and the output row drivers. The scroll function doesn't affect the data ram content. It is only related to the visualization process. The information output on the drivers is related to the row reading sequence (the 1st row read is output on R0, the 2nd on R1 and so on). Scrolling means reading the matrix starting from a row that is sequentially in- creased or decreased. After every scrolling command the offset between the memory address and the memory scanning pointer is increased or decreased by one. The offset range changes in accordance with MUX Rate. After 64th/65th scrolling commands in MUX 65 mode, or after the 48th/49th scrolling com- mands in mux 49 mode, or after 32nd/33rd scrolling command in MUX 33 mode, the offset between the memory address and the memory scanning pointer is again zero (Cyclic Scrolling). A Reset Scrolling Pointer instruction can be executed to force to zero the offset between the memory ad- dress and the memory scanning pointer If ICON MODE =1, the Icon Row is not scrolled. If ICON MODE=0 the last row is like a general purpose row and it is scrolled as other lines. I f the DIR Bit is set to a logic zero the offset register is increased by one and the raster is scrolled from top down. If the DIR Bit is set to a logic one the offset register is decreased by one and the raster is scrolled from bottom-up. Table 8.

5.6 Dual Partial Display

If the PE Bit is set to a logic one the dual partial display mode is enabled. Eight partial display modes are available. The offset of the two partial display zones is row by row pro- grammable. The Icon row is accessed last in each partial display frame. Two sets of register for the HV-generator parameters are provided (PRS[1:0], Vop[6:0], BS[2:0], CP[2:0].). This allows switching from normal mode to partial display mode only with one instruction. The HV gener- ator is automatically re configured using the parameters related to the enabled mode. The parameters of the two sets of registers with the same function are located in the same position of the instruction set. The registers related to the normal mode are accessible when normal mode (PE=0) is selected, the others are accessible when the partial display mode is enabled (PE=1). To Setup PRS[1:0], Vop[6:0], BS[2:0], CP[2:0] values the instruction flow proposed in Fig. 54 must be followed. To setup Partial Display Sectors Start Address and Partial Display Mode no particular instruction flow has to be followed. MUX RATE ICON MODE DESCRIPTION ICON Row Driver with MY=0 MUX 33 1 ICON ROW NOT SCROOLED R48 MUX 33 0 33 LINE GRAPHIC MATRIX R48 MUX 49 1 ICON ROW NOT SCROOLED R56 MUX 49 0 49 LINE GRAPHIC MATRIX R56 MUX 65 1 ICON ROW NOT SCROOLED R64 MUX 65 0 65 LINE GRAPHIC MATRIX R64

Figure 53. Dual Partial Display Enabling Instruction Flow Figure 54. Dual Partial Display Mode configuration or Duty Change Table 9. Partial Display Configurations

0 SECTION 1 SECTION2 RESET STATE

END OF PARTIAL DISPLAY CONFIG.

manage on one platform more than one LCD module with different configuration parameters. Table 10. STE2001/2-like instruction Set

Table 11. Extended Instruction Set

00001 M X M Y P D H [ 1 ] H [ 0 ] Page selector, Power Down

00000001 F R 1 F R 0 Frame rate Control

0000000001 S c r o l l i n g P o i n t e r R e s e t

000000001 X Not Used

0000001 T 2 T 1 T 0 Set Temperature Coefficient for VLDC

000001 N W 3N W 2N W 1N W 0 N-Line Inversion

000100 YC-3 YC-2 YC-1 YC-0 Y -CARRIAGE RETURN

001 XC-6 XC-5 XC-4 XC-3 XC-2 XC-1 XC-0 X CARRIAGE RETURN

Table 12. Explanations of Table 3 & 4 symbols Table 13. PAGE SELECTION Table 14. DISPLAY MODE Table 15. FRAME RATE CONTROL Table 16. VLCD RANGE SELECTION

00 P a g e 0

10 P a g e 2

11 P a g e 3

Table 17. MULTIPLEXING RATIO Table 18. TEMPERATURE COEFFICIENT Table 20. CHARGE PUMP MULTIPLICATION FACTOR

000 Multiplication Factor

100 N O T U S E D

101 N O T U S E D

110 N O T U S E D

111 A U T O M A T I C

Table 21. BIAS RATIO Table 22. Y CARRIAGE RETURN REGISTER Table 23. PARTIAL DISPLAY CONFIGURATION Table 24. N-LINE INVERSION

Figure 58. 8080-series & 68000-series Interface Interconnection in Master Slave Mode Figure 59. Host Processor Interconnection with I2C Interface

8 LINES 8 LINES

Figure 64. Host Processor Interconnection with 6800

Figure 67. Power-ON timing diagram

Figure 68. Power-OFF timing diagram

Figure 69. Initialization with built-in Booster END OF NORMAL DISPLAY MODE CONFIG.

Figure 70. DATA RAM to display Mapping Table 25. Test Pin Configuration

Table 26. Absolute Maximum Ratings Table 27. Electrical Characteristics

Notes: 1. The maximum possible VLCD voltage that can be generated is dependent on voltage, temperature and (display) load. 2. Internal clock 3. When f sclk = 0 there is no interface clock. 4. Power-down mode. During power-down all static currents are switched-off. 5. If external V LCD , the display load current is not transmitted to IDD 6. Tolerance depends on the temperature; (typically zero at Tamb = 27°C), maximum tolerance values are measured at the temper- ature range limit. 7. For TC0 to TC7 8. Data Byte Writing Mode 9. VDD1<=VDD2 Logic Inputs VIL Logic LOW voltage level VSS 0.3 VDD1 V VIH Logic HIGH Voltage Level 0.7 VDD1 VDD2 V Iin Input Current V in = VSS1 or VDD1 -1 1 µA Logic Inputs/Outputs VIL Logic LOW voltage level V SS 0.3 VDD1 V VIH Logic HIGH Voltage Level 0.7 VDD1 VDD1 + 0.5 V Column and Row Driver R row ROW Output Resistance 3K 5K kohm R col Column Output resistance 5K 10K kohm Vcol Column Bias voltage accuracy No load -50 +50 mV Vrow Row Bias voltage accuracy -50 +50 mV LCD Supply Voltage VLCD LCD Supply Voltage accuracy; Internally generated VDD = 2.8V; VLCD = 10V; fsclk=0; Tamb =25 C; no display load;note 2, 3, 6 & 7, VOP=69h, PRS=2Hex -1.8 +1.8 % TC0 Temperature coefficient -0.0· 10-3 1/°C TC1 -0.35 · 10-3 1/°C TC2 -0.7 · 10-3 1/°C TC3 -1.05· 10-3 1/°C TC4 -1.4 · 10-3 1/°C TC5 -1.75· 10-3 1/°C TC6 -2.1 · 10-3 1/°C TC7 -2.3· 10-3 1/°C DC OPERATION (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit Table 23 Electrical Characteristics (continued)

Figure 71. RESET timing diagram

Figure 72. I2C-bus timings

Figure 75. Serial interface Timing

1. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and VIH with
2. Cb is the capacitive load for each bus line.
3. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated

Table 28. Pad Coordinates Table 28. Pad Coordinates (continued)

Table 29. Alignment marks coordinates

Figure 76. Alignment marks dimensions Table 30. Bumps Table 31. Die Mechanical Dimensions Table 32. Revision History

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America STE2004