STE2001

STE2001 STMICROELECTRONICS | Alldatasheet

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Technical content

This is preliminary information on a new product now in development. Details are subject to change without notice. n 65 x 128 bits Display Data RAM n Configurable matrix: 65 x 128 or 33 x 128 n Programmable (65/33) MUX rate n Row by Row Scrolling n Automatic data RAM Blanking procedure n Selectable Input Interface:

• I2C Bus Fast and Hs-mode (read and write)
• Parallel Interface (write only)
• Serial Interface (write only) n Fully Integrated Oscillator requires no external components n Fully Integrated Configurable LCD bias voltages generator with: Selectable (5X, 4X, 3X, 2X) multiplication factor
• Effective sensing for High Precision Output
• Four selectable temperature compensation coefficients n Designed for chip-on-glass (COG) applications n Programmable bottom row pads mirroring and top row pads mirroring for compatible with both TCP and COG applications n Low Power Consumption, suitable for battery operated systems n Logic Supply Voltage range from 1.9 to 5V n High Voltage Generator Supply Voltage range from 2.4 to 4.5V n Display Supply Voltage range from 4.5 to 9V

DESCRIPTION

The STE2001 is a low power CMOS LCD controller driver. Designed to drive a 65 rows by 128 columns graphic display, provides all necessary functions in a single chip, including on-chip LCD supply and bias voltages generators, resulting in a minimum of exter- nals components and in a very low power consump- tion. The STE2001 features three standard interfaces (Serial, parallel, I 2C) for ease of interfacing with the hostµcontroller. Type Ordering Number Bumped Wafers STE2001DIE1 Bumped Dice on Waffle Pack STE2001DIE2 PRODUCT PREVIEW

65 X 128 SINGLE CHIP LCD CONTROLLER / DRIVER

Figure 1. Block Diagram

N ° Pad Type Function R0 to R64 1 to 16 145 to 177 257 to 272 O LCD Row Driver Output C0 to C127 17 to 144 O LCD Column Driver Output V SS1 ,2 227 to 238 GND Ground pads. V SS1 is GND for VDD1 ,V SS2 for VDD2 and VDD3 VDD1 186 to 191 Supply IC Positive Power Supply VDD2 ,3 192 to 201 Supply Internal Generator Supply Voltages. VLCDIN 246 to 251 Supply LCD Supply Voltages for the Column and Row Output Drivers. VLCDOUT 239 to 244 Supply Voltage Multiplier Ouput VLCDSENSE 245 Supply Voltage Multiplier Regulation Input. VLCDOUT Sensing for Output Voltage Fine Tuning SEL1,2 183, 184 I Interface Mode Selection SDA_IN 223 I I2C Bus Data In SDA_OUT 222 O I2C Bus Data Out SCL 224 I I2C bus Clock SA0 225 I I2C Slave Address LSB OSC 185 I External Oscillator Input RES 221 I Reset Input. Active Low. DB0 to DB7 211 to 218 I Parallel Interface 8 Bit Data Bus E 220 I Parallel Interface Data Latch Signal. Data are Latched on the Falling EDGE. PD/C 219 I Parallel Interface Data/Command Selector SDIN 207 I Serial Interface Data Input SCLK 210 I Serial Interface Clock SCE 209 I Serial Interface ENABLE. When Low the Incoming Data are Clocked In. SD/C 208 I Serial Interface Data/Command selection BSYFLG 206 O Active Procedure Flag. Notice if There is an ongoing Internal Operation. Active Low. T1 to T13 178 to 181 202 to 205 226 252 to 256 I/O Test Pads.

ELECTRICAL CHARACTERISTICS

specified) Symbol Parameter Value Unit VDD1 Supply Voltage Range - 0.5 to + 6.5 V VDD2,3 Supply Voltage Range - 0.5 to + 5 V VLCD LCD Supply Voltage Range - 0.5 to + 10 V ISS Supply Current - 50 to +50 mA Vi Input Voltage (all input pads) -0.5 to V DD2,3 + 0.5 V Iin DC Input Current - 10 to + 10 mA Iout DC Output Current - 10 to + 10 mA Ptot Total Power Dissipation (Tj=8 5°C) 300 mW Po Power Dissipation per Output 30 mW Tj Operating Junction Temperature -40 to + 85 °C Tstg Storage Temperature - 65 to 150 °C Symbol Parameter Test Condition Min. Typ. Max. Unit Supply Voltages VDD1 Supply Voltage 1.9 VDD2,3 +0 . 5 V Tamb =-20 to 85°C 1.8 VDD2,3 +0 . 5 V VDD2,3 Supply Voltage LCD Voltage Internally generated 2.4 4.5 V VLCDIN LCD Supply Voltage LCD Voltage Supplied externally 4.5 9 V VLCDOUT LCD Supply Voltage Internally generated; note 1 4.5 9 V I(VDD1 ) Supply Current V DD = 2.8V; VLCD = 7.6V; 4x charge pump; fsclk=0 ; Tamb =2 5°C; note 3. 81 5 µA I(VDD2,3) Voltage Generator Supply Current with VOP = 0 and PRS = 0 with external VLCD = 7.6V 10 15 µA VLCD =7.6V; VDD =2.8V; fsclk=0 ;Tamb =2 5°C; no display load; 4x charge pump; note 3,6 Fosc =0 70 115 µA

Notes: 1. The maximum possible VLCD voltage that can be generated is dependent on voltage, temperature and (display) load. 2. Internal clock 3. When f sclk= 0 there is no interface clock. 4. Power-down mode. During power-down all static currents are switched-off. 5. If external V LCD , the display load current is not transmitted to IDD 6. Tolerance depends on the temperature; (typically zero at Tamb =2 7°C), maximum tolerance values are measured at the temper- ature range limit. 7. For TC0 to TC3 AC OPERATION specified) I(VDD1,2,3) Total Supply Current V LCD = 7.6V; VDD =2.8V; 4x charge pump; fsclk=0 ;Tamb =2 5°C; no display load; note 3,6 Fosc =0 80 125 µA I(VLDCIN ) External LCD Supply Voltage Current VDD =2.8V; VLCD =7.6V;no display load; fsclk=0 ; Tamb =2 5°C; note 3. Fosc =0 15 25 µA Logic Inputs VIL Logic LOW voltage level V IN =V ih(tp <1 0µs) V SS 0.3 VDD V VIH Logic HIGH Voltage Level V IN =V il(tp <1 0µs) 0.7 VDD VDD2,3 +0 . 5 V Iin Input Current V in=V SS1 or VDD1 -1 1 µA Column and Row Driver R row ROW Output Resistance 12 20 kohm R col Column Output resistance 12 20 kohm Vcol Column Bias voltage accuracy No load -100 100 mV Vrow Row Bias voltage accuracy -100 100 mV LCD Supply Voltage VLCD LCD Supply Voltage accuracy; Internally generated VDD = 2.8V; VLCD = 7.6V; fsclk=0; Tamb=25 C; no display load; note 2, 3, 6 & 7 -300 300 mV TC Temperature coefficient 00 -550 PPM/ °C 01 -1350 PPM/ °C 10 -1650 PPM/ °C 11 -2650 PPM/ °C Symbol Parameter Test Condition Min. Typ. Max. Unit INTERNAL OSCILLATOR FOSC Internal Oscillator frequency VDD = 2.8V; 20 38 70 kHz FEXT External Oscillator frequency 20 38 100 kHz Symbol Parameter Test Condition Min. Typ. Max. Unit ELECTRICAL CHARACTERISTICS (continued)

FFRAME Frame frequency fosc or fext = 38 kHz; note 1 73 Hz TVHRL Vdd1 to RES Low note 2 and 10; C VLCD =1 µF0 5 m s Tw(RES) RES LOW pulse width note 3 600 ns Reset Pulse Rejection T amb =2 5°C; note 11 370 µs Reset Pulse Rejection note 11 200 µs TSTART Reset Pulse vs. Device Ready 1 ms TVDD 0 I2C BUS INTERFACE (See note 4) FSCL SCL Clock Frequency Fast Mode ; V DD1 =4.5V DC 400 kHz VDD1 =18V; Tamb = -20 to 70°C 400 kHz High Speed Mode; Cb=100pF (max); note 6; VDD1 =4.5V DC 3.4 MHz High Speed Mode; Cb=400pF (max); note 6 ; VDD1 =4.5V DC 1.7 MHz TSCLL Cb=100pF 160 ns TSCLH Cb=100pF 160 ns TSCLL Cb=400pF 320 ns TSCLH Cb=400pF 320 ns TSU;DAT Cb=100pF 30 ns THD;DAT Cb=100pF 30 ns TSU;DAT Cb=400pF 30 ns THD;DAT Cb=400pF 30 ns TSU;STA Cb=100pF Note 8 170 ns TSU;STA Cb=400pF Note 8 330 ns THD;STA Cb=100pF Note 8 170 ns THD;STA Cb=400pF Note 8 330 ns TSU;STO Cb=100pF Note 8 170 ns TSU;STO Cb=400pF Note 8 330 ns TrCL Cb=100pF Note 5, 8 25 ns TrCL Cb=400pF Note 5, 8 50 ns TrCL1 Cb=100pF Note 5, 8 30 ns TrCL1 Cb=400pF Note 5, 8 120 ns TrDA Cb=100pF Note 5, 8 30 ns TrDA Cb=400pF Note 5, 8 120 ns TfCL Cb=100pF Note 5, 8 25 ns TfCL Cb=400pF Note 5, 8 50 ns Symbol Parameter Test Condition Min. Typ. Max. Unit ELECTRICAL CHARACTERISTICS (continued)

Notes: 1. 2. RES may be LOW or HIGH before VDD1 goes HIGH. 3. If Tw(RES) is longer than 500ns (typical) a reset may be generated. 4. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to VIL and VIH with an input voltage swing of VSS to VDD 5. The rise and fall times specified here refer to the driver device and are part of general Hs-mode specification. 6. The device inputs SDA and SCL are filtered and will reject any spike on the bus-lines of with T SW 7. Cb is the capacitive load for each bus line. 8. T H5 is the time from the previous SCLK positive edge to the negative edge of SCE 9. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated 10.CVLCD is the filtering capacitor on VLCDOUT 11.If Tw(RES) is shorter than max. value a reset pulse is rejected. TfDA Cb=100pF 25 ns TfDA Cb=400pF 120 ns C b Capacitive load for SDAH and SCLH 100 400 pF C b Capacitive load for SDAH + SDA line and SCLH + SCL line 400 pF TSW note 5 10 ns PARALLEL INTERFACE TCY(EN) Enable Cycle Time V DD = 4.5V; Write 125 ns TW(EN) Enable Pulse width V DD = 4.5V; Write 60 ns TSU(A) Address Set-up Time V DD = 4.5V; Write 30 ns TH(A) Address Hold Time V DD = 4.5V; Write 50 ns TSU(D) Data Set-Up Time V DD = 4.5V; Write 30 ns TH(D) Data Hold Time V DD = 4.5V; Write 50 ns SERIAL INTERFACE FSCLK Clock Frequency V DD = 4.5V 8 MHz VDD1 = 1.8V 5 MHz TCYC Clock Cycle SCLK V DD = 4.5V 125 ns TPWH1 SCLK pulse width HIGH V DD = 4.5V 70 ns TPWL1 SCLK Pulse width LOW V DD = 4.5V 70 ns TS2 SCE setup time 50 ns TH2 SCE hold time 50 ns TPWH2 SCE minimum high time 60 ns TH5 SCE start hold time Note 8 60 ns TS3 SD/C setup time 60 ns TH3 SD/C hold time 40 ns TS4 SDIN setup time 40 ns TH4 SDIN hold time 40 ns Symbol Parameter Test Condition Min. Typ. Max. Unit Fframe fosc ELECTRICAL CHARACTERISTICS (continued)

Supplies Voltages and Grounds VDD2 and VDD3 are supply voltages to the internal voltage generator (see below). They must be externally connected. If the internal voltagegenerator is not used, these should be connected to VDD1 pad. VDD1 supplies the rest of the IC. This supply voltage could be different form VDD2 and VDD3 .VDD1 must be lower than VDD2,3 + 0.5V. Internal Supply Voltage Generator The IC has a fully integrated (no external capacitors required) charge pump for the Liquid Crystal Display supply volt- age generation. The multiplyin g factor can be programmed to be: X5; X4; X3; X2, using the ’set CP Multiplica tion’ Command. The output voltage (V LCDOUT ) is tightly controlled through the VLCDSENSE pad. For this voltage, four dif- ferent temperature coefficients(TC, rate of change with temperature) can be programmed using the bits TC1 and TC0. This will ensure no contrast degradation over the LCD operating range. Using the internal charge pump, the V LCDIN and VLCDOUT pads must be connected together. An external supply could be connected to VLCDIN to supply the LCD without using the internal generator. In such event the VLDCOUT and VLCDSENSE must be connected to GND and the internal voltage generator must be programmed to zero (PRS = 0, Vop = 0 - Reset condition). Oscillator A fully integrated oscillator (requires no external components) is present to provide the clock for the Display System. Whenused the OSC padmust be connectedto VDD1 pad. An external oscilla torcould beused andfedintothe OSC pin. Display Data RAM The STE2001, provides an 65X128 bits Static RAM to store Display data. This is organized into 8 (Bank0 to Bank7) banks with 128 Bytes and one Bank (Bank8) with 128 Bits to be used for icons. RAM access is accom- plished in either one of the Bus Interfaces provided (see below). Allowed addresses are X0 to X127 (Horizontal) and Y0 to Y8 (Vertical). When writing to RAM, four addressing mode are provided:

• Normal Horizontal (MX = 0 and V = 0), having the column with address X = 0 located on the left of the memory map. The X pointer is increased after each byte written. After the last column address (X = 127), Y address pointer is mod- ified to jump to next row. X restarts from X = 0 (Fig.2).
• Normal Vertical (MX = 0 and V = 1), having the column with address X = 0 located on the left of the memory map. The Y pointer is increased after each byte written. After the last row address (Y = 8), the X pointer is modified to jump to next column and Y restarting from Y = 0. (Fig. 3).
• Mirrored Horizontal (MX = 1 and V = 0), having the column with address X = 0 located on the right of the memory map. The X pointer is increased after each byte written. After the last column address (X = 127), Y address pointer is modified to jump to next row. X restarts from X = 0 (fig. 4).
• Mirrored Vertical (MX =1 and V = 1), having the column with address X = 0 located on the right of the memory map. The Y pointer is increased after each byte written. After the last row address (Y = 8), the X pointer is modified to jump to next column and Y restarting from Y = 0. (Fig. 5). After the last allowed address (X;Y) = (128;8), the address pointers always jump to the cell with address (X;Y) = (0;0). Data bytes in the memory could have the MSB either on top (D0 = 0, Fig. 6) or on the bottom (D0 = 1, Fig. 7). Mux 65 Mode The STE2001 provides also means to alter the normal output addressing. A mirroring of the Display along the X axis is enabled setting to a logic one the MY bit. This function is achieved reading the matrix from physical row 63 to 0, since the relation between the physical memory rows and the output row drivers is only dependent on the memory reading sequence (1st row read output on R0, 2nd on R1... last on R65). This function doesn’t affect the content of the memory map. It is only related to the visualizatio nprocess (Fig. 8 & Fig. 9). It is also possible to modify the why with which row drivers are connected with DDRAM memory. A flip along y-axis of each sub-block can be applied on both the Row Pads located on the Interface Side (the edge of the chip where the Interface Pads are located), setting the TRS bit to a logic one, and on the Row Pads located on the other edge, setting the BRS bit to a logic one. Figure 2 Automatic data RAM writing sequence with V=0 and Data RAM Normal Format (MX=0) Figure 3 Automatic data RAM writing sequence with V=1 and Data RAM Normal Format (MX=0)

are the ones related to Bank4 to Bank7. The icon row (BANK8) is always the last being output either MY bit is a logic one or zero. The functions related to bit TRS is the same as in MUX 65 mode. drivers become columns drivers. If a 33x128 LCD matrix is driven, the output row drivers R0-R15 and R32-R47 must be floating. Figure 10. Physical 65x128 memory matrix and 33x128 correspondence

To clear the RAM content a MEMORY BLANK instruction should be executed. off state. An external clock can be provided. The RAM contents is not cleared. At Reset the X2 factor is selected. Figure 13. Bias level Generator

• VLCD
• VLCD
• VLCD
• VLCD n+3 n+4 R nR R R n+2 n+4 n+4 n+4 D00IN1150

thus providing an 1/(n+4) ratio, with n calculated from: For m = 65, n = 5 and an 1/9 ratio is set. For m = 33, n =3 and an 1/7 ratio is set. The STE2001 provides three bits (BS0, BS1, BS2) for programming the desired Bias Ratio as shown below: The following table Bias Level for m = 65 and m = 33 are provided: LCD Voltage Generation The LCD Voltage at reference temperature (To = 35°C) can be set using the VOP register content according to the following formula: VLCD (T=To) = VLCD o = (Ai+VOP · B) (i=0,1) with the following values: Note that the two PRS value produces two adjacent ranges for VLCD. If the register and PRS bit are set to zero BS2 BS1 BS0 n 0007 0016 0105 0114 1003 1012 1101 1110 Symbol m = 65 (1/9) m = 33 (1/7) V1 V LCD VLCD V2 8/9*V LCD 6/7* VLCD V3 7/9*V LCD 5/7* VLCD V4 2/9*V V LCD 2/7* VLCD V5 1/9 *V LCD 1/7* VLCD V6 V SS VSS Symbol Value Unit Note Ao 2.90 V PRS = 0 A1 6.91 V PRS = 1 B 0.034 V To 35 °C nm 3 –=

the internal voltage generator is switched off. Figure 14. VLCD Slopes Cross Point with Different TC

6.85 Vth Ai–⋅()

Figure 15. Finally, the VLCD voltage at a given (T) temperature can be calculated as: VLCD (T) = VLCD o · [1 + (T-To) · TC] Memory Blanking Procedure This instruction allows to fill the memory with ”blank” patterns, in order to delete patterns randomly generated in memory when starting up the device. This instruction substitutes (128X9) single ”write” instructions. It is pos- sible to program ”Memory Blanking Procedure” only under the following conditions: - X address = 0 - Y address = 0 -Vb i t =0 - PD bit = 0 - MX bit = 0 The end of the procedure will be notified on the BSY_FLG pad going HIGH (while LOW the procedure is run- ning). Any instruction programmed with BSY_FLG LOW will be ignored that is, no instruction can be pro- grammed for a period equivalent to 128X9 internal write cycles (128X9X1/fclock). The start of Memory blanking procedure will be between one and two fclock cycles from the last active edge (E rising edge for the parallel interface, last SCLK rising edge for the Serial interface, last SCL rising edge for the I 2C interface). Checker Board Procedure This instruction allows to fill the memory with ”checker-board” pattern. It is mainly intended to developers, who can now simply obtain complex module test configuration by means of a single instruction. It is possible to pro- gram ”Checker Board Procedure” only under the following conditions: - X address = 0 - Y address = 0 -Vb i t =0 - PD bit = 0 - MX bit = 0 A0+B A 1 B PRS=0 D01IN1257PRS=1 VO VLCD 01h00h 03h 05h02h 04h 7Dh 7Eh 7Fh 00h 01h 02h 03h 04h 05h7Ch 7Dh 7Eh 7Fh 7Ch

The end of the procedure will be notified on the BSY_FLG pad going HIGH, while LOW the procedure is running. Any instruction programmed with BSY_FLG LOW will be ignored, that is, no instruction can be programmed for a period equivalent to 128X9 internal write cycles (128X9X1/fclock). The start of Memory blanking procedure will be between one and two fclock cycles from the last active edge (E rising edge for the parallel interface, last SCLK rising edge for the Serial interface, last SCL rising edge for the I 2C interface). Scroll The STE2001 can scroll the graphics display in units of raster-rows. The scrolling function is achieved changing the correspondence between the rows of the logical memory map and the output row drivers. The scroll function doesn’t affect the data ram content. It is only related to the visualization process. The information output on the drivers is related to the row reading sequence (the 1st row read is output on R0, the 2nd on R1 and so on). Scrolling means reading the matrix starting from a row that is sequentially increased or decreased. After every scrolling command the offset between the memory address and the memory scanning pointer is increased or decreased by one. The offset range is between 0 to 63 in mux 65 mode and 0-31 in mux 33 mode. After the 64th scrolling command in mux 65 mode and after the 32th in mux 33 mode, the offset between the memory address and the memory scanning pointer is again zero (Cyclic Scrolling). Bank8 is always accessed last in each frame, and so isn’t scrolled. If the DIR Bit is set to a logic zero the offset register is increased by one and the raster is scrolled from top down. If the DIR Bit is set to a logic one the offset register is decreased by one and the raster is scrolled from bottom-up. Bus Interfaces To provide the widest flexibility and ease of use the STE2001 features three different methods for interfacing the host Controller. To select the desired interface the SEL1 and SEL2 pads need to be connected to a logic LOW (connect to GND) or a logic HIGH (connect to VDD). All the I/O pins of the unused interfaces must be connected to GND. If I/O pins voltage is lower than VDD interfaces could sink more current than expected. All interfaces are working while the STE2001 is in Power Down. I2C Interface The I2C interface is a fully complying I2C bus specification, selectable to work in both Fast (400kHz Clock) and High Speed Mode (3.4MHz). This bus is intended for communication between different Ics. It consists of two lines: one bi-directional for data signals (SDA) and one for clock signals (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via an active or passive pull-up. The following protocol has been defined: - Data transfer may be initiated only when the bus is not busy. - During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined: BUS not busy:Both data and clock lines remain High. Start Data Transfer:A change in the state of the data line, from High to Low, while the clock is High, define the START condition. SEL2 SEL1 Interface Note

00 I2C Read and Write; Fast and

of the clock signal. There is one clock pulse per bit of data. wide and each receiver acknowledges with the ninth bit. put on the bus by the receiver, whereas the master generates an extra acknowledge related clock pulse. ”S00001xxx”. After this sequence no acknowledge pulse is generated. Figure 16. Bit transfer and START,STOP conditions definition

Figure 19. communication protocol The STE2001 serial Interface is a unidirectional link between the display driver and the application supervisor. (SCE) and one for mode selection (SD/C). ter. The STE2001 is only able to receive data. Information are exchanged byte-wide. During data transfer, the data line is sampled on the positive SCLK edge. While SCE pin is high the serial interface is kept in reset. eighth SCLK clock pulse during every byte transfer. at the next SCLK positive edge. If SCE is low after the positive edge of RES, the serial interface is ready to receive data.

The STE2001 parallel Interface is a unidirectional link between the display driver and the application supervisor. (E) for data latch and PD/C for mode selection. The data lines and the control line values are internally latched on E rising edge (fig. 23). Figure 23. Parallel interface timing Table 1. Instruction Set

Table 2. Explanations of Table 6 symbols

Figure 35. Chip Mechanical Drawing

Figure 36. Improved ALTH & PLESKO Driving Method

Figure 37. DATA RAM to display Mapping Table 7. Test Pin Configuration

Table 8. Mechanical Dimensions Table 9. Pad Coordinates Table 9. Pad Coordinates(continued)

Table 10. Alignment marks coordinates Figure 38. Alignment marks dimensions

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics  2001 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com STE2001