STE110NA20 STMICROELECTRONICS | Alldatasheet

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N - CHANNEL ENHANCEMENT MODE FAST POWER MOS TRANSISTOR PRELIMINARY DATA n TYPICAL RDS(on) = 0.015Ω n HIGH CURRENT POWER MODULE n AVALANCHE RUGGED TECHNOLOGY n VERY LARGE SOA - LARGE PEAK POWER CAPABILITY n EASY TO MOUNT n SAME CURRENT CAPABILITY FOR THE TWO SOURCE TERMINALS n EXTREMELY LOW Rth (Junction to case) n VERY LOW INTERNAL PARASITIC INDUCTANCE n ISOLATED PACKAGE UL RECOGNIZED

APPLICATIONS

n SMPS & UPS n MOTOR CONTROL n WELDING EQUIPMENT n OUTPUT STAGE FOR PWM, ULTRASONIC CIRCUITS INTERNAL SCHEMATIC DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V DS Drain-source Voltage (VGS = 0) 200 V V DGR Drain- gate Voltage (RGS =2 0k Ω ) 200 V V GS Gate-source Voltage ± 30 V ID Drain Current (continuous) at Tc =2 5 oC 110 A ID Drain Current (continuous) at Tc =1 0 0oC7 3 A IDM (•) Drain Current (pulsed) 440 A P tot Total Dissipation at Tc =2 5 oC 450 W Derating Factor 3.6 W/ oC Tst g Storage Temperature -55 to 150 oC Tj Max. Operating Junction Temperature 150 oC V ISO Insulation Withhstand Voltage (AC-RMS) 2500 V (•) Pulse width limited by safe operating area TYPE V DSS R DS(on) ID STE110NA20 200 V < 0.019 Ω 110 A March 1996 ISOTOP

Thermal Resistance Junction-case Max Thermal Resistance Case-heatsink With Conductive Grease Applied Max 0.27 0.05 oC/W oC/W AVALANCHE CHARACTERISTICS Symbol Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max, δ <1 % ) 55 A E AS Single Pulse Avalanche Energy (starting Tj =2 5 oC, ID =I AR ,V DD =5 0V ) 500 mJ E AR Repetitive Avalanche Energy (pulse width limited by Tj max, δ <1 % ) 175 mJ IAR Avalanche Current, Repetitive or Not-Repetitive (Tc =1 0 0oC, pulse width limited by Tj max, δ <1 % ) 32.5 A ELECTRICAL CHARACTERISTICS (Tcase =2 5oC unless otherwise specified) OFF Symbol Parameter Test Conditions Min. Typ. Max. Unit V (BR)DSS Drain-source Breakdown Voltage ID =1m A V GS = 0 200 V IDSS Zero Gate Voltage Drain Current (VGS =0 ) V DS =M a xR a t i n g V DS =M a xR a t i n gx0 . 8 Tc = 125 oC 400 200 µ A mA IGSS Gate-body Leakage Current (VDS =0 ) V GS = ± 30 V ± 400 nA ON (∗) Symbol Parameter Test Conditions Min. Typ. Max. Unit V GS(th) Gate Threshold Voltage VDS =V GS ID =1m A 2 . 2 5 3 3 . 7 5 V R DS(on) Static Drain-source On Resistance V GS = 10V I D =5 5A V GS = 10V I D =5 5A T c =1 0 0oC 0.015 0.019 Ω Ω ID(on) On State Drain Current VDS >I D(on) xR DS(on)max V GS =1 0V 110 A DYNAMIC Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (∗)F o r w a r d Transconductance V DS =15 V I D =5 5A 3 8 S C iss C oss C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS =2 5V f=1M H z V GS = 0 12.9 2870 980 nF pF pF STE110NA20

ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Time Rise Time V DD =1 0 0V I D =5 5A R G =4 . 7 Ω VGS =1 0V (see test circuit, figure 3) 100 125 ns ns (di/dt)on Turn-on Current Slope V DD =1 6 0V I D = 110 A R G =4 7 Ω VGS =1 0V (see test circuit, figure 5)

290 A/ µ s

V DD =1 6 0V I D = 110 A V GS = 10 V 470 226 600 nC nC nC SWITCHING OFF Symbol Parameter Test Conditions Min. Typ. Max. Unit tr(Voff) tf tc Off-voltage Rise Time Fall Time Cross-over Time V DD =1 6 0V I D = 110 A R G =4 . 7 Ω V GS =1 0V (see test circuit, figure 5) 115 160 150 100 210 ns ns ns SOURCE DRAIN DIODE Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD ISDM (•) Source-drain Current Source-drain Current (pulsed) 110 440 A A V SD (∗)F o r w a r d O n V o l t a g e ISD =1 1 0A V GS =0 1 . 6 V trr Q rr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 110 A di/dt = 100 A/µ s V R =5 0V T j =1 5 0oC (see test circuit, figure 5) 625 ns µ C A (∗) Pulsed: Pulse duration = 300µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area Safe Operating Area Thermal Impedance STE110NA20

Static Drain-source On Resistance Output Characteristics Transconductance Gate Charge vs Gate-source Voltage STE110NA20

Normalized On Resistance vs Temperature Turn-off Drain-source Voltage Slope Normalized Gate Threshold Voltage vs Temperature Turn-on Current Slope Cross-over Time STE110NA20

Switching Safe Operating Area Source-drain Diode Forward Characteristics Fig. 1:Unclamped Inductive Load Test Circuit Accidental Overload Area Fig. 2:Unclamped Inductive Waveform STE110NA20

Fig. 3:Switching Times Test Circuits For Resistive Load Fig. 5:Test Circuit For Inductive Load Switching And DIode Recovery Times Fig. 4:Gate Charge test Circuit STE110NA20

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsabilit y for the consequences of use of such information nor for any infringemen t of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise underany patent or patent rights of SGS-THOMSON Microelectr onics. Specifications mention ed in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectr onics products are not authorized for use as critical compon ents in life supportdevices or systems withoutexpre ss written approval of SGS-THOMSON Microelectonics.  1995 SGS-THOMSON Microelectroni cs - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain- Sweden- Switzerland - Taiwan - Thailand - United Kingdom - U.S.A ... STE110NA20