STE10A STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Overview
- 1.1 Block diagrams
- 1.2 Detailed features
- 2 Pin description
- 3 Functional description
- 3.1 Initialization flow
- 3.2 Network packet buffer management
- 3.2.1 Descriptor structure types
- 3.2.2 Descriptor management
- 3.3 T ransmit scheme and transmit early interrupt
- 3.3.1 Transmit scheme
- 3.3.2 Transmit pre-fetch data flow
- 3.3.3 Transmit early interrupt scheme
- 3.4 Receive scheme and receive early interrupt scheme
- 3.5 Network operation
- 3.5.1 MAC operation
- 3.5.2 Transceiver operation
- 3.5.3 Flow control in full duplex application
- 3.6 LED display operation
- 3.7 Reset operation
- 3.7.1 Reset whole chip
- 3.7.2 Reset transceiver only
- 3.8 Wake on LAN function
- 3.9 ACPI power management function
- 3.9.1 Power states
- 4 Registers and descriptors description
- 4.1 STE10/100A configuration registers
- 4.1.1 STE10/100A configuration registers description
- 4.2 PCI control/status registers
- 4.3 T ransceiver(XCVR) registers
Features
■ IEEE802.3u 100BASE-TX and IEEE802.3 10BASE-T compliant ■ Support for IEEE802.3x flow control ■ IEEE802.3u auto-negotiation support for 10BASE-T and 100BASE-TX ■ PCI bus interface rev. 2.2 compliant ■ ACPI and PCI power management standard compliant ■ Support for PC99 wake on LAN ■ Provides 32-bit PCI bus master data transfer at PCI clocks of 20-33 MHz ■ Provides writable EEPROM/Boot rom interface ■ Provides independent transmission and receiving FIFOs, each 2k bytes long ■ Supports big endian or little endian byte ordering ■ ACPI and PCI compliant power management functions offer significant power-savings performance ■ Provides general purpose timers ■ 128-pin QFP package
Description
The STE10/100A is a high performing PCI fast ethernet controller with integrated physical layer interface for 10BASE-T and 100BASE-TX applications. It was designed with advanced CMOS technology to provide glueless 32-bit bus master interface for PCI bus, boot ROM interface, CSMA/CD protocol for fast ethernet, as well as the physical media interface for 100BASE-TX of IEEE802.3u and 10BASE-T of IEEE802.3. The auto-negotiation function is also supported for speed and duplex detection. The STE10/100A provides both half-duplex and full-duplex operation, as well as support for full- duplex flow control. It provides long FIFO buffers for transmission and receiving, and early interrupt mechanism to enhance performance. The STE10/100A also supports ACPI and PCI compliant power management function PQFP128 (14mm x 20mm x 2.7mm)
1 Overview
1.1 Block diagrams
Figure 1. STE10/100A block diagram Figure 2. STE10/100A system diagram
1.2 Detailed features
- Provides independent transmission and receiving FIFOs, each 2k bytes long
- Pre-fetches up to two transmit packets to minimize inter frame gap (IFG) to 0.96us
- Retransmits collided packet without reload from host memory within 64 bytes.
- Automatically retransmits FIFO under-run packet with maximum drain threshold until 3rd time retry failure threshold of next packet. PCI interface
- Provides 32-bit PCI bus master data transfer
- Supports PCI clock with frequency from 0Hz to 33MHz
- Supports network operation with PCI system clock from 20MHz to 33MHz
- Provides performance meter and PCI bus master latency timer for tuning the threshold to enhance the performance
- Provides burst transmit packet interrupt and transmit/receive early interrupt to reduce host CPU utilization
- As bus master, supports memory-read, memory-read-line, memory-read-multiple, memory-write, memory-write-and-invalidate command
- Supports big or little endian byte ordering EEPROM/Boot ROM interface
- Provides writable flash ROM and EPROM as boot ROM, up to 128Kbit
- Provides PCI to access boot ROM by byte, word, or double word
- Re-writes flash boot ROM through I/O port by programming register
- Provides serial interface for read/write 93C46 EEPROM
- Automatically loads device ID, vendor ID, subsystem ID, subsystem vendor ID, maximum-latency, and minimum-grand from the 64 byte contents of 93C46 after PCI reset de-asserted MAC/physical
- Integrates the complete set of physical layer 100BASE-TX and 10BASE-T functions
- Provides full-duplex operation in both 100Mbps and 10Mbps modes
- Provides auto-negotiation (NWAY) function of full/half duplex operation for both 10 and
100 Mbps
- Provides MLT -3 transceiver with DC restoration for base-line wander compensation
- Provides transmit wave-shaper, receive filters, and adaptive equalizer
- Provides MAC and transceiver (TXCVR) loop-back modes for diagnostic
- Built-in stream cipher scrambler/ de-scrambler and 4B/5B encoder/decoder
- Supports external transmit and receive transformer with 1:1 turn ratio
- Provides 2 LED display modes: – 3 LED displays for 100Mbps (on) or 10Mbps (off) link (remains on when link ok) or activity (Blinks at 10Hz when receiving or transmitting collision-free) FD (Remains on when in full duplex mode) or when collision detected (Blinks at 20Hz) – 4 LED displays for: 100 link (On when 100M link ok) 10 link (On when 10M link ok) Activity (Blinks at 10Hz when receiving or transmitting) FD (Remains on when in full duplex mode) or when collision detected (Blinks at 20Hz)
- If no LED is used, then: Pull the pins 90, 91, 92 of U4 to high with 4.7K resistor (see STE10/100A evaluation board schematics for details)
2 Pin description
Figure 3. Pin connection
Table 1. Pin description one of the interrupt event is set.
114 RST# I
impedance state and all the O/D pins are floated.
116 PCI-CLK I
117 GNT# I
119 PME# O
a power management event has occurred. magic packet frame from the network.
host issues configuration cycles to the STE10/100A.
18 FRAME# I/O Asserted by PCI bus master during bus tenure
20 IRDY# I/O Master device is ready to begin data transaction
21 TRDY# I/O Target device is ready to begin data transaction
23 STOP# I/O PCI target device request to the PCI master to stop the
24 PERR# I/O Data parity error detected, driven by the device receiving
25 SERR# O/D Address parity error
26 PAR I/O
drives PAR for read data phase. status is detected in the half duplex configuration.
76 EECS O Chip select of serial EEPROM
77 BrCS# O BootROM chip select
78 BrOE# O BootROM read output enable for flash ROM application
79 BrWE# O BootROM write enable for flash ROM application. Table 1. Pin description (continued)
98 X1 I
pin will be connected to the oscillator’s output pin.
97 X2 O
clock source is used, then this pin should be left open. T, these pins connect directly to magnetic. these pins connect directly from magnetic.
101 Iref O Reference resistor connecting pin for reference current,
directly connects a 5KOhm ± 1% resistor to Vss. receiving or transmitting is detected.
89 Vaux-detect I When this pin is asserted, it indicates an auxiliary power
source is supported from the system.
88 Vcc-detect I When this pin is asserted, it indicates a PCI power source is
3 Functional description
3.1 Initialization flow
Figure 4. STE10/100A initialization flow
3.2 Network packet buffer management
3.2.1 Descriptor structure types
controlled by RCH (RDES1 bit 24) and TCH (TDES1 bit 24). complete or partial packet. A buffer may not contain more than one packet. There are two buffers per descriptor in the ring structure. Support receive early interrupt. Figure 5. Frame buffer ring structure
There is only one buffer per descriptor in chain structure. Figure 6. Frame buffer chain structure
3.2.2 Descriptor management
Figure 7. Transmit descriptor management
Figure 8. Receive descriptor management
3.3 Transmit scheme and transmit early interrupt
3.3.1 Transmit scheme
Figure 9. Transmit scheme
3.3.2 Transmit pre-fetch data flow
Figure 10. Transmit pre-fetch data flow
3.3.3 Transmit early interrupt scheme
Figure 11. Transmit normal interrupt and early interrupt comparison
3.4 Receive scheme and receive early interrupt scheme
Figure 12. Receive data flow (without early interrupt and with early interrupt) Figure 13. Detailed receive early interrupt flow
3.5 Network operation
3.5.1 MAC operation
requirements for operating as an IEEE802.3 and ethernet compliant node. according to IEE802.3u, clause 24. detected, the STE10/100A will report a CRC error. the channel even though a carrier has been sensed on the network. Table 2. Format
- If padding is disabled (TDES1 bit 23), the data field may be shorter than 46 bytes
STE10/100A Functional description Collision handling The scheduling of re-transmissions are determined by a controlled randomization process called “truncated binary exponential back-off”. At the end of enforcing a collision (jamming), the STE10/100A delays before attempting to re-transmit the packet. The delay is an integer multiple of slot time. The number of slot times to delay before the nth re-transmission attempt is chosen as a uniformly distributed integer r in the range: 0 · r < 2 k where k = min(n, 10)
3.5.2 Transceiver operation
The transceiver portion of the ste10/100a integrates the ieee802.3u compliant functions of PCS (physical coding sub-layer), PMA (physical medium attachment) sub-layer, and PMD (physical medium dependent) sub-layer for 100base-tx, and the ieee802.3 compliant functions of manchester encoding/decoding and transceiver for 10base-t. All the functions and operating schemes are described in the following sections. 100BASE-TX transmit operation For 100BASE-TX transmissions, the STE10/100A transceiver provides the transmission functions of PCS, PMA, and PMD for encoding of MII data nibbles into five-bit code-groups (4B/5B), scrambling, serialization of scrambled code-groups, converting the serial NRZ code into NRZI code, converting the NRZI code into MLT3 code, and then driving the MLT3 code into the category 5 unshielded twisted pair cable through an isolation transformer with the turns ratio of 1: 1. Recommended transformers HB626-1 from transpower technologies, 9410 prototype drive, suite #1, Reno, NV 89511. Tel: (775) 852-0140 and H1102 from pulse engineering Inc., 12220 World Trade Drive, San Diego, CA92128. Tel: (619) 674-8100. Data code-groups encoder In normal MII mode applications, the transceiver receives nibble type 4B data via the TxD0~3 inputs of the MII. These inputs are sampled by the transceiver on the rising edge of Tx-clk and passed to the 4B/5B encoder to generate the 5B code-group used by 100BASE- TX. Idle code-groups In order to establish and maintain the clock synchronization, the transceiver must keep transmitting signals to medium. The transceiver will generate Idle code-groups for transmission when there is no actual data to be sent by MAC. Start-of-stream delimiter-SSD (/J/K/) In a transmission stream, the first 16 nibbles comprise the MAC preamble. In order to let a network partner delineate the boundary of a data transmission se quence and to authenticate carrier events, the transceiver will replace the first 2 nibbles of the MAC preamble with /J/K/ code-groups.
Functional description STE10/100A End-of-stream delimiter-ESD (/T/R/) In order to indicate the termination of normal data transmissions, the transceiver will insert 2 nibbles of /T/R/ code-group after the last nibble of the FCS. Scrambling All the encoded data (including the idle, SSD, and ESD code-groups) is passed to the data scrambler to reduce EMI by spreading the power spectrum using a 10-bit scrambler seed loaded at the beginning. Data conversion of parallel to serial, NRZ to NRZI, NRZI to MLT3 After being scrambled, the 5B type transmission data at 25MHz will be converted to a 125HMz serial bit stream by the parallel-to-serial function. The bit stream will be further converted from NRZ to NRZI format, unless the conversion function is bypassed by clearing ENRZI (bit 7 of XR10) to 0. After NRZI conversion, the NRZI bit stream is passed through MLT3 encoder to generate the TP-PMD specified MLT3 code. By using MLT3 code, the frequency and energy content of the transmission signal is reduced in the UTP , making the system more easily compliant to FCC EMI specifications. Wave-shaper and media signal driver In order to reduce the energy of the harmonic frequency of transmission signals, the transceiver provides a wave-shaper prior the line driver to smooth the rising/falling edge of transmission signals while maintaining the waveforms’ symmetry. The 100BASE-TX and 10BASE-T wave-shaped signals are both passed to the same media signal driver. This can simplify system design by employing a single external magnetic connection. 100BASE-TX receiving operation For 100BASE-TX receiving operation, the transceiver provides the receiving functions of PMD, PMA, and PCS for incoming data signals through category 5 UTP cable and an isolation transformer with a 1:1 turns ratio. The receive transceiver portion includes the adaptive equalizer and baseline wander, MLT3 to NRZI data conversion, NRZI to NRZ conversion, serial to parallel conversion, a PLL for clock and data recovery, de-scrambler, and the 5B/4B decoder. Adaptive equalizer and baseline wander High speed signals over unshielded (or shielded) twisted pair cable will experience attenuation and phase shift. These effects depend on the signal frequency, cable type, cable length and the cable connectors. Robust circuits in the transceiver provide reliable adaptive equalizer and baseline wander compensation for amplitude attenuation and phase shift due to transmission line parasites. MLT3 to NRZI decoder and PLL for data recovery Following adaptive equalizer, baseline wander, the transceiver converts the resulting MLT3 to NRZI code, which is passed to the Phase Lock Loop circuits in order to extract the synchronous clock and the original data.
STE10/100A Functional description Data conversions of NRZI to NRZ and serial to parallel After the data is recovered, it will be passed to the NRZI-to-NRZ converter to produce a 125MHz serial bit stream. This serial bit stream will be packed to parallel 5B type for further processing. The NRZI to NRZ conversion may be bypassed by clearing ENRZI (bit 7 of XR10) to 0. De-scrambling and decoding of 5B/4B The parallel 5B type data is passed to the de-scrambler and 5B/4B decoder to restore it to its original MII nibble representation. Carrier sensing The carrier sense (CRS) signal is asserted when the transceiver detects any 2 non- contiguous zeros within any 10-bit boundary of the receiving bit stream. CRS is de-asserted when ESD code-group or Idle code-group is detected. In half duplex mode, CRS is asserted during packet transmission or receive; in full duplex mode, CRS is asserted only during packet reception. 10BASE-T transmission operation The parallel-to-serial converter, Manchester Encoder, Link test, Jabber and the transmit wave-shaper and line driver functions described in the section of “Wave-Shaper and Media Signal Driver” of “100BASE-T Transmission Operation” are also provided for 10BASE-T transmission. Additionally, Collision detection and SQE test for half duplex application are provided. 10BASE-T receive operation Carrier sense function, receiving filter, PLL for clock and data recovery, Manchester decoder, and serial to parallel converter functions are provided to support 10BASE-T reception. Loop-back operation of transceiver
- The transceiver provides internal loop-back (also called transceiver loop-back) operation for both 100BASE-TX and 10BASE-T operation. The loop-back function can be enabled by setting XLBEN (bit 14 of XR0) to 1. In loop-back mode, the TX± and RX± lines are isolated from the media. The transceiver also provides remote loop-back operation for 100BASE-TX operation. The remote loop-back operation can be enabled by setting ENRLB (bit 9 of XR10) to 1.
- In 100BASE-TX internal loop-back operation, the data is routed from the transmit output of NRZ-to-NRZI converter and looped back to the receive input of NRZI-to-NRZ converter. In 100BASE-TX remote loop-back operation, data is received from RX± pins and passed through the receive path to the output of the data and clock recovery section, and then looped back to the input of the NRZI-to-MLT3 converter and out to the medium via the transmit line drivers. In 10BASE-T loop-back operation, the data is passed through the transmit path to the output of the Manchester encoder and then looped back into the input of the phase lock loop circuit in the receive path.
Functional description STE10/100A Full duplex and half duplex operation of transceiver The transceiver can operate in either full duplex or half duplex network applications. In full duplex, both transmission and reception can take place simultaneously. In full duplex mode, collision (COL) signal is ignored and carrier sense (CRS) signal is asserted only when the transceiver is receiving. In half duplex mode, transmission and reception can not take place simultaneously. In half duplex mode, the collision signal is asserted when transmitted and received signals collide, and carrier sense is asserted during both transmission and reception. Auto-negotiation operation The auto-negotiation function provides the means to exchange information between the transceiver and the network partner to automatically configure both to take maximum advantage of their abilities. The auto-negotiation function is controlled by ANEN (bit 12 of XR0). During auto-negotiation information is exchanged with the network partner using fast link pulses (FLPs) - a burst of link pulses. There are 16 bits of signaling information contained in the link pulses which advertise to the remote partner the capabilities which are represented by the contents of ANA (register XR4). According to this information the partners find out their highest common capabilities by following the priority sequence listed below: – 100BASE-TX full duplex – 100BASE-TX half duplex – 10BASE-T full duplex – 10BASE-T half duplex During power-up or reset, if auto-negotiation is enabled, the FLPs will be transmitted and the auto-negotiation function will proceed. Otherwise, auto-negotiation will not occur until ANEN (bit 12 of XR0) is set to 1. When the auto-negotiation is disabled, then network speed and duplex mode are selected by programming the XR0 register. Power down operation The transceiver is designed with a power-down feature which can reduce power consumption significantly. Since the power supply of the 100BASE-TX and 10BASE-T circuits are separate, the transceiver can turn off the circuit of either the 100BASE-TX or 10BASE-T when the other is active.
3.5.3 Flow control in full duplex application
describe how the STE10/100A implements the PAUSE function. Figure 14. MAC control frame format PAUSE times is 0 to 65535 slot-times. requests to inhibit its transmission of data frames. – The MAC control opcode field set to 0001h.
STE10/100A exits the PAUSE state immediately. Figure 15. Pause operation receive state diagram
STE10/100A Functional description
3.6 LED display operation
The STE10/100A provides 2 LED display modes; the detailed descriptions of their operation are described in the pin description section. First mode – 3 LED displays – 100Mbps (on) or 10Mbps (off) – Link (Remains on when link ok) or activity (Blinks at 10Hz when receiving or transmitting collision-free) – FD (Remains on when in full duplex mode) or collision (Blinks at 20Hz when collisions detected) Second mode – 4 LED displays – 100 Link (On when 100M link ok) – 10 Link (On when 10M link ok) – Activity (Blinks at 10Hz when receiving or transmitting) – FD (Remains on when in full duplex mode) or collision (Blinks at 20Hz when collisions detected)
3.7 Reset operation
3.7.1 Reset whole chip
There are two ways to reset the STE10/100A: – Hardware reset Via RST# pin (to ensure proper reset operation, the RST# signal should be asserted at least 100ms) – Software reset Via SWR (bit 0 of CSR0) being set to 1 (the STE10/100A will reset all circuits except the transceivers and configuration registers, set registers to their default values, and will clear SWR) and set XRST(XR0, bit 15) to reset the transceivers.
3.7.2 Reset transceiver only
When XRST (bit 15 of XR0) is set to 1, the transceiver will reset its circuits, will initialize its registers to their default values, and clear XRST.
Functional description STE10/100A
3.8 Wake on LAN function
The STE10/100A can assert a signal to wake up the system when it has received a Magic Packet from the network. The wake on LAN operation is described as follow. The Magic Packet format – Valid destination address that can pass the address filter of the STE10/100A – Payload of the frame including at least 6 contiguous ‘FF’ followed immediately by 16 repetitions of IEEE address – The frame can contain multiple ‘six FF + sixteen IEEE address’ pattern – Valid CRC The wake on LAN operation The wake on LAN enable function is controlled by WOL (bit 18 of CSR18), which is loaded from EEPROM after reset or programmed by driver software. If WOL is set and the STE10/100A receives a Magic Packet, it will assert the PME# signal (active low) to indicate reception of a wake up frame and will set the PME status bit (bit 15 of CSR20).
3.9 ACPI power management function
The STE10/100A has a built-in capability for power management (PM) which is controlled by the host system. The STE10/100A will provide: – Compatibility with device class power management reference specification – Network device class, draft proposal v0.9, october 1996 – Compatibility with ACPI, Rev 1.0, december 22, 1996 – Compatibility with PCI bus power management interface specification, Rev 1.0, january 6, 1997 – Compatibility with AMD Magic Packet™ Technology.
3.9.1 Power states
DO (Fully on) In this state the STE10/100A operates with full functionality and consumes normal power. While in the D0 state, if the PCI clock is lower than 16MHz, the STE10/100A may not receive or transmit frames properly. D1, D2, and D3hot In these states, the STE10/100A doesn’t respond to any accesses except configuration space and full function context in place. The only network operation the STE10/100A can initiate is a wake-up event. D3cold (Power removed) In this state all function context is lost. When power is restored, a PCI reset must be asserted and the function will return to D0.
power-up reset condition without the RST# pin asserted. Table 3. Power stage
4 Registers and descriptors description
registers, PCI control/status registers, and transceiver control/status registers. STE10/100A and for identifying and querying the STE10/100A. through mapped I/O or memory address space. The STE10/100A contains 11 16-bit registers to supported transceiver control and status. addition, 4 special registers are provided for advanced chip control and status.
4.1 STE10/100A configuration registers
Table 4. STE10/100A configuration registers list
Table 5. STE10/100A configuration registers table
- Automatically recalled from EEPROM when PCI reset is deserted
4.1.1 STE10/100A configuration registers description
Table 6. Configuration registers description
31 SPE
1: means that STE10/100A detected a parity error.
30 SES
29 SMA
and has terminated a master transaction.
28 STA
and has terminated a master transaction. the chip’s assertion of device select. 01: indicates a medium assertion of DEVSEL#.
01 R/O
24 SDPR
detected parity error asserted by another device. b. STE10/100A is operating as a bus master.
23 SFBB
accept fast back to back transactions.
0: the STE10/100A doesn’t provide new capabilities. Command system error response. Command parity error response. operating. Default value is 0. Command master operation ability. 0: disable the STE10/100A bus master ability.
1 CMSA
Command memory space access. 0: disable the memory space access ability. 1: enable the memory space access ability. 0: enable the I/O space access ability. 1: disable the I/O space access ability. R/W: Read and write able. RO: Read able only. Table 6. Configuration registers description (continued)
of the STE10/100A in units of PCI bus clock cycles. soon as its GNT# is removed. cache line size in units of 32-bit double words (DW). (CSR0~28), and transceiver registers (XR0~10). as a result of power-on or hardware reset. EEPROM as a result power-on or hardware reset. accessing the boot ROM space.
access bit (bit 1 of CR1) and this bit are set to 1. 1: enable boot ROM. (If bit 1 of CR1 is also set). as a result of power-on or hardware reset. whenever it initiates a transaction, in units of 250ns. priority and vector information. Driver space for implementation-specific purpose.
3.3Vaux current requirements for STE10/100A chip.
21 DSI
transition to the D0 uninitialized state.
19 PMEC
power management interface specification.
15 PMEST
the state of the PME-En bit. STE10/100A to deassert PME# (if so enabled). Writing a “0” has no effect. for any function that implements the data register. The STE10/100A does not support Data_select.
- R/W1C: Read only and write one cleared
4.2 PCI control/status registers
Table 7. PCI control/status registers list
Table 8. Control/status register description
24 MWIE
Memory write and invalidate enable.
23 MRLE
memory read command instead.
21 MRME
Memory read multiple enable.
00 R/W *
000000 R/W *
Big or little endian selection.
1 BAR
after the reset process is completed. R/W* = Before writing the transmit and receive operations should be stopped. data from the FIFO to buffer is then started. Table 8. Control/status register description (continued)
interrupt generated by this field. state only, no interrupt will be generated. only, no interrupt will be generated.
16 NISS
15 AISS
13 FBE
11 GPTT General purpose timer timeout, based on
8 RPS Receive process stopped, receive state = stop 0 RO/LH *
7 RDU
Receive descriptor unavailable. recognized frame is received). 6 RCI Receive completed interrupt. report the under-flow error on bit 1 of TDES0.
Transmit jabber timer time-out. Transmit descriptor unavailable. command should then be issued. 1T P S Transmit process stopped. Transmit completed interrupt. LH = High Latching and cleared by writing 1.
19 SQE
0: enable SQE function for 10BASE-T operation. 10BASE-T half duplex operation.
00 R/W **
5 SBC
and resumes when carrier is dropped. of CSR6) should be set to 1. processor is in the running or suspending state. 1: receive processor will enter running state. W* = only write when the transmit processor stopped. W** = only write when the transmit and receive processor both stopped. W*** = only write when the receive processor stopped.
16 NIE
15 AIE
13 FBEIE
Fatal bus error interrupt enable. CSR7) will enable the fatal bus error interrupt.
11 GPTIE
General purpose timer interrupt enable. Receive stopped interrupt enable. CSR7) will enable the receive stopped interrupt. Receive descriptor unavailable interrupt enable.
6 RCIE
Receive completed interrupt enable. Transmit under-flow interrupt enable.
3 TJTTIE
Transmit jabber timer time-out interrupt enable.
2 TDUIE
Transmit descriptor unavailable interrupt enable.
1 TPSIE
Transmit processor stopped interrupt enable. Transmit completed interrupt enable.
16 LPCO
Lost packet counter overflow. 1: when lost packet counter overflow occurs. descriptors being available. Cleared after read.
14 SRC
when SRS (CSR9 bit 11) is also set.
13 SWC
Serial EEPROM write control. when SRS (CSR9 bit 11) is also set.
11 SRS
0S C S Serial EEPROM chip select.
16 COM
General-purpose timer value. counter with a cycle time of 204us.
30 CRCT
29 WP1E Wake-up pattern one matched enable 0 R/W
28 WP2E Wake-up pattern two matched enable 0 R/W
27 WP3E Wake-up pattern three matched enable 0 R/W
26 WP4E Wake-up pattern four matched enable 0 R/W
25 WP5E Wake-up pattern five matched enable 0 R/W
17 LinkOFF
link status has switched from ON to OFF .
16 LinkON
link status has switched from OFF to ON.
10 WFRE
R/W1C*, Read only and write one cleared.
long words write operation to CSR14 should be done. bytes, the watchdog timer will expire. 1: disable the receive watchdog.
1: cut off transmission after 2560 byte-time. after 42 ms (100Mbps) or 420ms (10Mbps).
31 TEIS
30 REIS
Receive early interrupt status. descriptor. This bit is cleared by writing a 1.
26 PFR
PAUSE frame received interrupt status. interrupt generated by this field.
state only, no interrupt will be generated. only, no interrupt will be generated.
16 ANISS
Added normal interrupt status summary.
15 AAISS
Added abnormal interrupt status summary.
31 TEIE Transmit early interrupt enable 0 R/W
30 REIE Receive early interrupt enable 0 R/W
29 XIE Transceiver (XCVR) interrupt enable 0 R/W
28 TDIE Transmit deferred interrupt enable 0 R/W
26 PFRIE PAUSE frame received interrupt enable 0 R/W
16 ANISE
Added normal interrupt summary enable.
15 AAIE
Added abnormal interrupt summary enable.
31 D3CS
is detected then bit 31 of PMR0 will be set to ‘1’.
18 WOL
mode and enters the sleep state.
6 RWP Reset wake-up pattern data register pointer 0 R/W
0: PAUSE function is disabled. 1: the receive FIFO threshold is enabled.
01 R/W
RO* = Read only and cleared by reading.
15 PMES
regardless of the state of the PME-En bit. STE10/100A to deassert PME# (if so enabled). Writing a “0” has no effect. that implements the data register. The STE10/100A does not support Data_select.
discarded and no state change occurs. transmit completed interrupt will be generated. interrupt will be generated. otherwise it functions as LED pin – fd/col.
PAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bits 19-17=000).
4.3 Transceiver(XCVR) registers
registers are provided for advanced chip control and status. word (bit 31~16) of the XCVR registers (XR0~XR10) should be ignored. Table 9. Transceiver registers list
Table 10. Transceiver registers description XR0(offset = b4h) - XCR, XCVR control register. The default value is chosen as listed below.
15 XRST
14 XLBEN
Transceiver loop-back mode select. (CSR6 bits 11,10) of must contain 00.
13 SPSEL
Auto-negotiation is enabled (ANEN, XR0 bit 12).
12 ANEN
Auto-negotiation ability control. 1: Auto-negotiation function is enabled. 0: Auto-negotiation is disabled.
11 PDEN
9 RSAN
Re-start auto-negotiation process control. 1: Auto-negotiation process will be restarted. Auto-negotiation has restarted.
8 DPSEL
Full/half duplex mode select. 7C O L E N Collision test control. R/W = Read/Write able. RO = Read only. XR1(offset = b8h) - XSR, XCVR status register. All the bits of this register are read only.
14 TXFD
100BASE-TX full duplex ability.
13 TXHD
100BASE-TX half duplex ability.
10BASE-T full duplex ability. 10BASE-T half duplex ability. 0: Auto-negotiation process incomplete. 1: Auto-negotiation process complete. Result of remote fault detection. 0: no remote fault condition detected. 1: remote fault condition detected.
0 EXT
LL* = Latching Low and clear by read. LH * = Latching High and clear by read. organizationally unique identifier (OUI). 9~4 MODEL Model number of STE10/100A. 3~0 REV Revision number of STE10/100A. Table 10. Transceiver registers description (continued)
15 NXTPG
13 RF Remote fault function. Flow control function ability. 8T X F 100BASE-TX full duplex ability. 7T X H 100BASE-TX half duplex ability. 6 10F 10BASE-T full duplex ability. 5 10H 10BASE-T half duplex ability.
15 LPNP
Link partner next page ability. 0: link partner without next page ability. 1: link partner with next page ability.
14 LPACK
Received link partner acknowledge. 0: link code word not yet received. STE10/100A’s link code word.
13 LPRF
Link partner’s remote fault status. 0: no remote fault detected.
10 LPFC
Link partner’s flow control ability. 0: link partner without PAUSE function ability.
Link partner’s 100BASE-T4 ability. 0: link partner without 100BASE-T4 ability. 1: link partner with 100BASE-T4 ability.
8 LPTXF
Link partner’s 100BASE-TX full duplex ability.
7 LPTXH
Link partner’s 100BASE-TX half duplex ability. 0: link partner without 100BASE-TX. 1: link partner with 100BASE-TX ability. Link partner’s 10BASE-T full duplex ability. 1: link partner with 10BASE-T full duplex ability. Link partner’s 10BASE-T half duplex ability. 0: link partner without 10BASE-T ability. 1: link partner with 10BASE-T ability. 1: a fault detected via parallel detection function. Link partner’s next page ability. 0: link partner without next page ability. 1: link partner with next page ability. STE10/100A’s next page ability. 0: no new page has been received. 1: a new page has been received. Link partner auto-negotiation ability. 0: link partner has no auto-negotiation ability. 1: link partner has auto-negotiation ability. LH = High Latching and cleared by reading.
Long distance mode of 10BASE-T.
9 SPEED
Speed configuration setting.
8 DUPLEX
Duplex configuration setting. 0: PAUSE function is disabled.
6 ANC
Auto-negotiation completed interrupt. 0: Auto-negotiation has not completed yet. 1: Auto-negotiation has completed. Remote fault detected interrupt. 0: there is no remote fault detected. 1: remote fault is detected. 0: there is no link code word received. 1: link code word is receive from link partner. Parallel detection fault interrupt. 0: there is no parallel detection fault. 1: parallel detection is fault. Auto-negotiation page received interrupt. 0: there is no auto-negotiation page received. 1: auto-negotiation page is received.
Receive error full interrupt. 0: the receive error number is less than 64. 1: 64 error packets is received. LH = High Latching and cleared by reading.
6 ANCE
Auto-negotiation completed interrupt enable. 0: disable auto-negotiation completed interrupt. 1: enable auto-negotiation complete interrupt. Remote fault detected interrupt enable. 0: disable remote fault detection interrupt. 1: enable remote fault detection interrupt. 0: disable link fail interrupt. 1: enable link fail interrupt. Auto-negotiation acknowledge interrupt enable. 1: enable link partner acknowledge interrupt. Parallel detection fault interrupt enable. 0: disable fault parallel detection interrupt. 1: enable fault parallel detection interrupt. Auto-negotiation page received interrupt enable. RX_ERR full interrupt enable. 0: disable rx_err full interrupt.
13 DISRER
12 ANC
1: the auto-negotiation process has completed.
9 ENRLB
Enable remote loop-back function.
8 ENDCR
7 ENRZI
Enable the conversions between NRZ and NRZI. receiving and NRZ to NRZI in transmitting. Reports current transceiver operating mode. 0: the MLT3 encoder and decoder are enabled. 1: the MLT3 encoder and decoder are bypassed.
0 DISCRM
0: the scrambler and de-scrambler is enabled. 1: the scrambler and de-scrambler are disabled.
4.4 Descriptors and buffer management
4.4.1 Receive descriptor
Table 11. Receive descriptor table Table 12. Receive descriptor description
31 OWN
0: Host has not yet processed the received data currently in this descriptor. This field is valid only in a frame’s last descriptor. Descriptor error. This bit is valid only in a frame’s last descriptor. received. The packet is truncated. These bits are valid only in a frame’s last descriptor. 10 MF Multicast frame. This bit is valid only in a frame’s last descriptor.
9 FS First descriptor
8 LS Last descriptor
Frame type. This bit is valid only in a frame’s last descriptor.
24 RCH
Table 12. Receive descriptor description (continued)
4.4.2 Transmit descriptor
Table 13. Receive descriptor table Table 14. Transmit descriptor description 0: No transmit data in this descriptor.
14 TO Transmit jabber time-out
11 LO Loss of carrier
10 NC No carrier
9 LC Late collision
8 EC Excessive collision
7 HF Heartbeat fail
1 UF Under-run error
0 DE Deferred
31 IC Interrupt completed
30 LS Last descriptor
29 FS First descriptor
26 AC Disable add CRC function
25 TER End of ring
23 DPD Disable padding function
Table 14. Transmit descriptor description (continued)
5 General EEPROM format description
Table 15. Connection type definition
21 Format major version: 0x02,
old ROM format version 0x01 is for STE10/100A-MAC only.
44 R e s e r v e d
01: Enable flow control function.
Table 16. Connection type definition
6 Electrical specifications and timings
Table 17. Absolute maximum ratings Table 18. General DC specifications
6.1 Timing specifications
Table 19. AC specifications Table 18. General DC specifications (continued) Table 20. PCI clock specifications
Figure 16. PCI clock waveform Table 21. X1 specifications
50 PPM
Table 22. PCI timing
Figure 17. PCI timings Table 23. Flash interface timings
Figure 22. Fast link pulse timings Table 27. 100BASE-TX transmitter AC timings specification
STE10/100A Package mechanical data
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOP ACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 23. Package mechanical data
0.7 DEGREES
0.25 GAGE PLANE
8 Ordering information
9 Revision history
Table 28. Order codes Table 29. Document revision history