STE10 STMICROELECTRONICS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 66
Technical content
This is preliminary information on a new product now in development. Details are subject to change without notice.
1.0 DESCRIPTION
face for 10BASE-T and 100BASE-TX application. supported for speed and duplex detection.
2.0 FEATURES
2.1 Industry standard
2.2 FIFO
host memory within 64 bytes. registers and transmit threshold of next packet. Figure 1. STE10/100Block Diagram
2.3 PCI I/F
■ Provides 32-bit PCI bus master data transfer ■ Supports PCI clock with frequency from 0Hz to 33MHz ■ Supports network operation with PCI system clock from 20MHz to 33MHz ■ Provides performance meter and PCI bus master latency timer for tuning the threshold to enhance the performance ■ Provides burst transmit packet interrupt and transmit/receive early interrupt to reduce host CPU utilization ■ As bus master, supports memory-read, memory-read-line, memory-read-multiple, memory-write, memory-write-and-invalidate command ■ Supports big or little endian byte ordering
2.4 EEPROM/Boot ROM I/F
■ Provides writeable Flash ROM and EPROM as boot ROM, up to 128kB ■ Provides PCI to access boot ROM by byte, word, or double word ■ Re-writes Flash boot ROM through I/O port by programming register ■ Provides serial interface for read/write 93C46 EEPROM ■ Automatically loads device ID, vendor ID, subsystem ID, subsystem vendor ID, Maximum-Latency , and Minimum-Grand from the 64 byte contents of 93C46 after PCI reset de-asserted
2.5 MAC/Physical
■ Integrates the complete set of Physical layer 100BASE-TX and 10BASE-T functions ■ Provides Full-duplex operation in both 100Mbps and 10Mbps modes ■ Provides Auto-negotiation (NWAY) function of full/half duplex operation for both 10 and 100 Mbps ■ Provides MLT-3 transceiver with DC restoration for Base-line wander compensation ■ Provides transmit wave-shaper, receive filters, and adaptive equalizer ■ Provides MAC and Transceiver (TXCVR) loop-back modes for diagnostic ■ Built-in Stream Cipher Scrambler/ De-scrambler and 4B/5B encoder/decoder ■ Supports external transmit transformer with 1.414:1 turn ratio ■ Supports external receive transformer with 1:1 turn ratio
2.6 LED Display
■ Provides 2 LED display modes:
3 LED displays for
100Mbps (on) or 10Mbps (off) Link (Remains on when link ok) or Activity (Blinks at 10Hz when receiving or transmitting collision-free) FD (Remains on when in Full duplex mode) or when collision detected (Blinks at 20Hz)
4 LED displays for
100 Link (On when 100M link ok)
10 Link (On when 10M link ok)
Activity (Blinks at 10Hz when receiving or transmitting) FD (Remains on when in Full duplex mode) or when collision detected (Blinks at 20Hz)
2.7 Miscellaneous
Figure 2. System Diagram of the STE10/100
3.0 PIN ASSIGNEMENT DIAGRAM
Figure 3. Pin Connection
Table 1. Pin Description impedance state and all the O/D pins are floated. ownership of the PCI Bus as a result of a Bus Request.
119 PME# O
receipt of a Magic Packet frame from the network. signal follows HP’s protocol; otherwise, it is IBM protocol. configuration cycles to the STE10/100.
18 FRAME# I/O Asserted by PCI Bus master during bus tenure
20 IRDY# I/O Master device is ready to begin data transaction
21 TRDY# I/O T arget device is ready to begin data transaction
23 STOP# I/O PCI target device request to the PCI master to stop the current transaction
24 PERR# I/O Data parity error detected, driven by the device receiving data
25 SERR# O/D Address parity error
Provides up to 128kB EPROM or Flash-ROM application space. is detected in the half duplex configuration.
76 EECS O Chip Select of serial EEPROM
77 BrCS# O BootROM Chip Select
78 BrOE# O BootROM Read Output Enable for flash ROM application
79 BrWE# O BootROM Write Enable for flash ROM application. pin will be connected to the oscillator’s output pin. above). If an external clock source is used, then this pin should be left open. connect directly to Magnetic.
101 Iref O Reference Resistor connecting pin for reference current, directly connects a 5K
90 LED M1-
frequency when either effective receiving or transmitting is detected. frequency when either effective receiving or transmitting is detected.
92 LED M1-
100 Link
when the 100M b/s network operating speed is detected. 100Mb/s network operating spped is detected.
91 LED M1-
10 Link
10Mb/s network operating speed is detected.
89 Vaux-
88 Vcc-detect I When this pin is asserted, it indicates a PCI power source is supported.
5.0 REGISTERS AND DESCRIPTORS DESCRIPTION
registers, and Transceiver control/status registers. tialize, control, and read the status of the STE10/100 through mapped I/O or memory address space. IEEE802.3u standard. In addition, 4 special registers are provided for advanced chip control and status. The STE10/100 also provides receive and transmit descriptors for packet buffering and management.
5.1 STE10/100 Configuration Registers
byte, word, and double word accessible. Table 2. STE10/100 configuration registers list
Table 3. STE10/100 configuration registers table
5.1.1 STE10/100 configuration registers descriptions
Table 4. Configuration Registers Descriptions
0 R/W
1: means that STE10/100 asserted the system error pin.
terminated a master transaction. 28 STA Status T arget Abort. terminated a master transaction.
01 R/O
24 SDPR Status Data Parity Report. parity error asserted by another device. b. STE10/100 is operating as a bus master.
23 SFBB Status Fast Back-to-Back
1 R/O
list of extended capabilities, such as PCI power management. 0: the STE10/100 doesn’t provide New Capabilities.
8 CSE Command System Error Response
SERR# when it finds a parity error during the address phase.
6 CPE Command Parity Error Response
error (bit 13 of CSR5) when a parity error is detected.
2 CMO Command Master Operation Ability
0: disable the STE10/100 bus master ability.
1 CMSA Command Memory Space Access
0: disable the memory space access ability. 1: enable the memory space access ability.
0 CIOSA Command I/O Space Access
0: enable the I/O space access ability. 1: disable the I/O space access ability. R/W: Read and Write able. RO: Read able only. as soon as its GNT# is removed. and memory-write-and-invalidate. 1: means that the configuration registers map into I/O space.
0 IOSI Memory Space Indicator. 1: means that the configuration registers map into I/O space. CR11(offset = 2ch), SID - Subsystem ID. of power-on or hardware reset. a result power-on or hardware reset. the STE10/100 supports up to 128kB of boot ROM. CR1) and this bit are set to 1. CR13(offset = 34h), CP - Capabilities Pointer. from serial EEPROM as a result power-on or hardware reset. pins to which the STE10/100 is connected. priority and vector information. CR16(offset = 40h), DS - Driver Space for special purpose.
driver can use this R/W area as user-specified storage. CR48(offset = c0h), PMR0, Power Management Register0. 375 mA to support remote wake-up in D3cold power state. does not support remote wake-up from D3cold power state.
21 DSI The Device Specific Initialization bit indicates whether any
generic class device driver is able to use it. there are no additional items in the Capabilities List. link list item as being the PCI Power Management Registers.
CR49(offset = c4h), PMR1, Power Management Register 1. a wake-up event, regardless of the state of the PME-En bit. deassert PME# (if so enabled). Writing a “0” has no effect. not modified by either hardware or software reset. required for any function that implements the Data register. to be reported through the Data register and Data_Scale field. The STE10/100 does not support Data_select. 8 PME_En PME_En. When set, enables the STE10/100 to assert PME#. When cleared, disables the PME# assertion. not modified by either hardware or software reset. data is discarded and no state change occurs. R/W1C*, Read Only and Write one cleared.
5.2 PCI Control/Status registers
Table 5. PCI Control/Status registers list
Table 6. Control/Status register description 24 MWIE Memory Write and Invalidate Enable. while writing full cache lines. STE10/100 will use memory write commands instead.
0 R/W*
23 MRLE Memory Read Line Enable. 21 MRME Memory Read Multiple Enable. 18,17 T AP Transmit auto-polling in transmit suspended state.
00 R/W*
number of DW to be transferred in one DMA transaction.
010000 R/W*
7 BLE Big or Little Endian selection. descriptors in the units of DW.
1 BAR Bus arbitration
0 SWR Software reset
R/W* = Before writing the transmit and receive operations should be stopped. 31~ 0 TPDM Transmit poll demand. R/W* = Before writing the transmit process should be in the suspended state. the FIFO to buffer is then started. R/W* = Before writing the receive process should be in the suspended state. R/W* = Before writing the receive process should be stopped. R/W* = Before writing the transmit process should be stopped.
interrupt will be generated.
0 RO/LH*
11 GPTT General Purpose Timer Timeout, based on CSR11 timer
9 RWT Receive Watchdog Timeout, based on CSR15 watchdog timer
8 RPS Receive Process Stopped, receive state = stop 0 RO/LH*
7 RDU Receive Descriptor Unavailable
when a new recognized frame is received).
6 RCI Receive Completed Interrupt
1: when a frame reception is completed.
5 TUF Transmit Under-Flow
3 TJT Transmit Jabber Timer Time-out
transmit jabber time-out flag) will be asserted.
2 TDU Transmit Descriptor Unavailable
poll demand command should then be issued. 1 TPS Transmit Process Stopped. 0 TCI Transmit Completed Interrupt. TDES1) asserted in the first transmit descriptor of the frame. LH = High Latching and cleared by writing 1.
21 SF Store and forward for transmit
19 SQE SQE Disable
1 R/W*
13 ST Stop transmit
12 FC Force collision mode
0 R/W**
00 R/W**
7 MM Multicast Mode
0 R/W***
6 PR Promiscuous Mode
1 R/W***
5 SBC Stop Back-off Counter
3 PB Pass Bad packet
bad packets, PR (bit 6 of CSR6) should be set to 1.
1 SR Start/Stop Receive
received if the corresponding function is enabled. 1: receive processor will enter running state. W* = only write when the transmit processor stopped. W** = only write when the transmit and receive processor both stopped. W*** = only write when the receive processor stopped.
16 NIE Normal Interrupt Enable
15 AIE Abnormal Interrupt Enable
13 FBEIE Fatal Bus Error Interrupt Enable
11 GPTIE General Purpose Timer Interrupt Enable
the general purpose timer expired interrupt.
9 RWTIE Receive Watchdog Time-out Interrupt Enable
the receive watchdog time-out interrupt.
8 RSIE Receive Stopped Interrupt Enable
the receive stopped interrupt.
7 RUIE Receive Descriptor Unavailable Interrupt Enable
the receive descriptor unavailable interrupt.
6 RCIE Receive Completed Interrupt Enable
the receive completed interrupt.
5 TUIE Transmit Under-flow Interrupt Enable
the transmit under-flow interrupt.
3 TJTTIE Transmit Jabber Timer Time-out Interrupt Enable
the transmit jabber timer time-out interrupt.
2 TDUIE Transmit Descriptor Unavailable Interrupt Enable
the transmit descriptor unavailable interrupt.
1 TPSIE Transmit Processor Stopped Interrupt Enable
the transmit processor stopped interrupt.
0 TCIE Transmit Completed Interrupt Enable
the transmit completed interrupt.
16 LPCO Lost Packet Counter Overflow
0 RO/LH
14 SRC Serial EEPROM Read Control
13 SWC Serial EEPROM Write Control
11 SRS Serial EEPROM Select
3 SDO Serial EEPROM data out
2 SDI Serial EEPROM data in
1 R/W
1 SCLK Serial EEPROM clock
High/Low this bit to provide the clock signal for EEPROM.
0 SCS Serial EEPROM chip select
1: selects the serial EEPROM chip.
16 COM Continuous Operation Mode
30 CRCT CRC-16 Type
PMR1 (CR49) after STE10/100 has received a Magic packet. STE10/100 has detected a link status changed event.
2 WFR Wake-up Frame Received,
affected by a hardware or software reset.
1 MPR Magic Packet Received,
affected by a hardware or software reset.
0 LSC Link Status Changed,
is not affected by a hardware or software reset. R/W1C*, Read Only and Write one cleared.
- Offset value is from 0-255 (8-bit width).
- To load the whole wake-up frame filtering information, consecutive 25 long words write operation to CSR14 should be done.
sensing dropped carrier to releasing watchdog timer.
4 RWD Receive Watchdog Disable
1: disable the receive watchdog.
2 JCLK Jabber clock
1: cut off transmission after 2560 byte-time.
1 NJ Non-Jabber
0 JBD Jabber disable
31 TEIS Transmit Early Interrupt status
30 REIS Receive Early Interrupt Status. receive descriptor. This bit is cleared by writing a 1.
26 PFR PAUSE Frame Received Interrupt Status
no interrupt will be generated. 16 ANISS Added normal interrupt status summary. 1: whenever any of the added normal interrupts occur. 15 AAISS Added Abnormal Interrupt Status Summary. 1: whenever any of the added abnormal interrupts occur. are accessible through either CSR5 or CSR16. LH* = High Latching and cleared by writing 1.
31 TEIE Transmit Early Interrupt Enable 0 R/W
30 REIE Receive Early Interrupt Enable 0 R/W
29 XIE Transceiver (XCVR) Interrupt Enable 0 R/W
28 TDIE Transmit Deferred Interrupt Enable 0 R/W
26 PFRIE PAUSE Frame Received Interrupt Enable 0 R/W
16 ANISE Added Normal Interrupt Summary Enable. the normal interrupt summary (bit 16 of CSR5). 15 AAIE Added Abnormal Interrupt Summary Enable. to the abnormal interrupt summary (bit 16 of CSR5). CSR7, and are accessible through either CSR7 or CSR16.
This bit is used to control the LED mode selection. Packet”, “Unicast”, and “Muliticast”. reset (software or hardware) happens.
6 RWP Reset Wake-up Pattern Data Register Pointer 0 R/W
enable or disable it after the Auto-Negotiation has completed. 0: PAUSE function is disabled. 4 RTE Receive Threshold Enable. 1: the receive FIFO threshold is enabled. 3~2), and the receive threshold is set to the default 64 bytes.
01 R/W
0 RO*
7~0 DWCNT The number of double words accessed by the last bus master. RO* = Read only and cleared by reading. a wake-up event, regardless of the state of the PME-En bit. deassert PME# (if so enabled). Writing a “0” has no effect. required for any function that implements the Data register. to be reported through the Data register and Data_Scale field. The STE10/100 does not support Data_select.
8 PME_En PME_En. When set, enables the STE10/100 to assert PME#. When cleared, disables the PME# assertion. data is discarded and no state change occurs. 11~0 TTO Transmit Time-Out = (deferred time + back-off time). interrupt will be generated. brA16; otherwise it functions as LED pin – fd/col.
PAR0 and PAR1 are readable, but can be written only if the receive state is in stopped (CSR5 bits 19-17=000). MAR0 and MAR1 are readable, but can be written only if the receive state is in stopped(CSR5 bit19-17=000).
5.3 Transceiver(XCVR) Registers
cal Layer link signaling for 10 Mb/s and 100 Mb/s Auto-Negotiation on twisted pair” of the IEEE802.3u standard. In addition, 4 special registers are provided for advanced chip control and status. (XR0~XR10) should be ignored. Table 7. Transceiver registers list Table 8. Transceiver registers Descriptions XR0(offset = b4h) - XCR, XCVR Control Register. The default value is chosen as listed below. 15 XRST Transceiver Reset control. transceiver reset has completed. 14 XLBEN Transceiver loop-back mode select. Negotiation is enabled (ANEN, XR0 bit 12). 12 ANEN Auto-Negotiation ability control. 1: Auto-Negotiation function is enabled. 0: Auto-Negotiation is disabled.
11 PDEN Power down mode control. STE10/100 transceivers are turned off. 9 RSAN Re-Start Auto-Negotiation process control. 8 DPSEL Full/Half duplex mode select. Negotiation is enabled (ANEN, XR0 bit 12). 7 COLEN Collision test control. 1: collision test is enabled. R/W = Read/Write able. RO = Read Only. XR1(offset = b8h) - XSR, XCVR Status Register. All the bits of this register are read only. Always 0, since STE10/100 has no T4 ability. 14 TXFD 100BASE-TX full duplex ability. 13 TXHD 100BASE-TX half duplex ability. 12 10FD 10BASE-T full duplex ability. Always 1, since STE10/100 has 10Base-T full duplex ability. 11 10HD 10BASE-T half duplex ability. Always 1, since STE10/100 has 10Base-T half duplex ability. 5 ANC Auto-Negotiation Completed. 0: Auto-Negotiation process incomplete. 1: Auto-Negotiation process complete. 4 RF Result of remote fault detection. 0: no remote fault condition detected. 1: remote fault condition detected. 3 AN Auto-Negotiation ability. Always 1, since STE10/100 has Auto-negotiation ability. 0: a link failure condition occurred. Readin clears this bit.
0 RO/LL*
1: jabber condition detected (10Base-T only).
0 EXT Extended register support. LL* = Latching Low and clear by read. LH* = Latching High and clear by read. 15~0 PHYID1 Part one of PHY Identifier. 15~10 PHYID2 Part two of PHY Identifier. 9~4 MODEL Model number of STE10/100. 6-bit manufacturer’s model number. 3~0 REV Revision number of STE10/100. 4-bits manufacturer’s revision number. Always 0; STE10/100 does not provide next page ability. 13 RF Remote Fault function. 10 FC Flow Control function Ability. 1: supports P AUSE operation of flow control for full duplex link. Always 0; STE10/100 does not provide 100BASE-T4 ability. 8 TXF 100BASE-TX Full duplex Ability. 7 TXH 100BASE-TX Half duplex Ability. 1: 100Base-TX ability supported. 6 10F 10BASE-T Full duplex Ability. 1: 10Base-T full duplex ability supported. 5 10H 10BASE-T Half duplex Ability. 1: 10Base-T ability supported. 15 LPNP Link partner Next Page ability. 0: link partner without next page ability. 1: link partner with next page ability.
14 LPACK Received Link Partner Acknowledge. 0: link code word not yet received. 13 LPRF Link Partner’s Remote fault status. 0: no remote fault detected. 10 LPFC Link Partner’s Flow control ability. 0: link partner without PAUSE function ability. 1, link partner with PAUSE function ability for full duplex link. 9 LPT4 Link Partner’s 100BASE-T4 ability. 0: link partner without 100BASE-T4 ability. 1: link partner with 100BASE-T4 ability. 8 LPTXF Link Partner’s 100BASE-TX Full duplex ability. 0: link partner without 100BASE-TX full duplex ability. 1: link partner with 100BASE-TX full duplex ability. 7 LPTXH Link Partner’s 100BASE-TX Half duplex ability. 0: link partner without 100BASE-TX. 1: link partner with 100BASE-TX ability. 6 LP10F Link Partner’s 10BASE-T Full Duplex ability. 0: link partner without 10BASE-T full duplex ability. 1: link partner with 10BASE-T full duplex ability. 5 LP10H Link Partner’s 10BASE-T Half Duplex ability. 0: link partner without 10BASE-T ability. 1: link partner with 10BASE-T ability. 4 PDF Parallel detection fault. 1: a fault detected via parallel detection function. 3 LPNP Link Partner’s Next Page ability. 0: link partner without next page ability. 1: link partner with next page ability. 2 NP STE10/100’s next Page ability. Always 0; STE10/100 does not support next page ability. 0: no new page has been received. 1: a new page has been received. 0 LPAN Link Partner Auto-Negotiation ability. 0: link partner has no Auto-Negotiation ability. 1: link partner has Auto-Negotiation ability. LH = High Latching and cleared by reading.
11 LD Long Distance mode of 10BASE-T. 1: reduced 10Base-T squelch level for extended cable length. 9 SPEED Speed configuration setting. 8 DUPLEX Duplex configuration setting. 7 PAUSE PAUSE function configuration setting for flow control. 0: PAUSE function is disabled. 6 ANC Auto-Negotiation Completed Interrupt. 0: Auto-Negotiation has not completed yet. 1: Auto-Negotiation has completed. 5 RFD Remote Fault Detected Interrupt. 0: there is no remote fault detected. 1: remote fault is detected. 3 ANAR Auto-Negotiation Acknowledge Received Interrupt. 0: there is no link code word received. 1: link code word is receive from link partner. 2 PDF Parallel Detection Fault Interrupt. 0: there is no parallel detection fault. 1: parallel detection is fault. 1 ANPR Auto-Negotiation Page Received Interrupt. 0: there is no Auto-Negotiation page received. 1: auto-negotiation page is received. 0 REF Receive Error full Interrupt. 0: the receive error number is less than 64. 1: 64 error packets is received. LH = High Latching and cleared by reading.
6 ANCE Auto-Negotiation Completed interrupt Enable. 0: disable Auto-Negotiation completed interrupt. 1: enable auto-negotiation complete interrupt. 5 RFE Remote Fault detected interrupt Enable. 0: disable remote fault detection interrupt. 1: enable remote fault detection interrupt. 4 LDE Link Down interrupt Enable. 0: disable link fail interrupt. 1: enable link fail interrupt. 3 ANAE Auto-Negotiation Acknowledge interrupt Enable. 1: enable link partner acknowledge interrupt. 2 PDFE Parallel Detection Fault interrupt Enable. 0: disable fault parallel detection interrupt. 1: enable fault parallel detection interrupt. 1 ANPE Auto-Negotiation Page Received interrupt Enable. 0: disable Auto-Negotiation page received interrupt. 1: enable Auto-Negotiation page received interrupt. 0 REFE RX_ERR full interrupt Enable. 0: disable rx_err full interrupt. 13 DISRER Disable the RX_ERR counter. 0: the receive error counter - RX_ERR is enabled. 1: the receive error counter - RX_ERR is disabled. 0: the Auto-Negotiation process has not completed yet. 1: the Auto-Negotiation process has completed. 11 RXVPP Select peak to peak voltage of receive. 1: receive voltage peak to peak 1.4 VPP . 9 ENRLB Enable remote loop-back function. 1: enable remote loop-back (CSR6 bits 11 and 10 must be 00). 8 ENDCR Enable DC restoration. 7 ENRZI Enable the conversions between NRZ and NRZI. 0: disable the data conversion between NRZ and NRZI. NRZ to NRZI in transmitting.
5.4 Descriptors and Buffer Management
The STE10/100 provides receive and transmit descriptors for packet buffering and management.
5.4.1 Receive descriptor
Table 9. Receive Descriptor Table 4~2 CMODE Reports current transceiver operating mode. 0: the MLT3 encoder and decoder are enabled. 1: the MLT3 encoder and decoder are bypassed. 0: the scrambler and de-scrambler is enabled. 1: the scrambler and de-scrambler are disabled.
Table 10. Receive Descriptor Descriptions
31 OWN Own bit
0: Host has not yet processed the received data currently in this descriptor. 30-16 FL Frame length, including CRC. This field is valid only in a frame’s last descriptor. This field is valid only in a frame’s last descriptor. 14 DE Descriptor error. This bit is valid only in a frame’s last descriptor. These bits are valid only in a frame’s last descriptor. 11 RF Runt frame (packet length < 64 bytes). This bit is valid only in a frame’s last descriptor. 10 MF Multicast frame. This bit is valid only in a frame’s last descriptor. 7 TL Packet Too Long (packet length > 1518 bytes). This bit is valid only in a frame’s last descriptor. 5 FT Frame type. This bit is valid only in a frame’s last descriptor. 4 RW Receive watchdog (refer to CSR15, bit 4). This bit is valid only in a frame’s last descriptor. 1: Packet length is not integer multiple of 8-bit.
5.4.2 Transmit Descriptor
Table 11. Transmit Descriptor Table
24 RCH Second address chain
31~0 RBA1 Receive Buffer Address 1. This buffer address should be double word aligned. 31~0 RBA2 Receive Buffer Address 2. This buffer address should be double word aligned. Table 12. Transmit Descriptor Descriptions 0: No transmit data in this descriptor.
14 TO Transmit jabber time-out
11 LO Loss of carrier
10 NC No carrier
9 LC Late collision
8 EC Excessive collision
7 HF Heartbeat fail
1 UF Under-run error
0 DE Deferred
31 IC Interrupt completed
30 LS Last descriptor
29 FS First descriptor
26 AC Disable add CRC function
25 TER End of Ring
23 DPD Disable padding function
31~0 BA1 Buffer Address 1. No alignment limitations imposed on the transmission buffer address. 31~0 BA2 Buffer Address 2. No alignment limitations imposed on the transmission buffer address.
6.0 FUNCTIONAL DESCRIPTIONS
6.1 Initialization Flow
Figure 4. Initialization Flow of STE10/100
6.2 Network Packet Buffer Management
6.2.1 Descriptor Structure Types
tain packet and frame parameters, status, and other information vital to controlling network operation. packet. A buffer may not contain more than one packet. ■ Ring structure: There are two buffers per descriptor in the ring structure. Support receive early interrupt. Figure 5. Ring structure of frame buffer
■ Chain structure: There is only one buffer per descriptor in chain structure. Figure 6. Chain structure of frame buffer
6.2.2 Descriptor Management
Figure 7. Transmit descriptor management
Figure 8. Receive descriptor management
6.3 Transmit Scheme and Transmit Early Interrupt
6.3.1 Transmit flow
Figure 9. The flow of packet transmit is shown as below.
Figure 10. Transmit data flow of pre-fetch data
6.3.3 Transmit early interrupt Scheme
Figure 11. Transmit normal interrupt and early interrupt comparison
6.4 Receive scheme and Receive early interrupt scheme
The following figure shows the difference of timing without early interrupt and with early interrupt. Figure 12. Receive data flow (without early interrupt and with early interrupt) Figure 13. Detailed Receive Early interrupt flow
6.5 Network Operation
6.5.1 MAC Operation
The MAC (Media Access Control) portion of STE10/100 incorporates the essential protocol requirements for op- erating as an IEEE802.3 and Ethernet compliant node. ■ Format *Note: If padding is disabled (TDES1 bit 23), the data field may be shorter than 46 bytes. ■ Transmit Data Encapsulation The differences between transmit data encapsulation and a MAC frame while operating in 100BASE- TX mode are listed as follows: 1. The first byte of the preamble is replaced by the JK code according to IEE802.3u, clause 24. 2. After the CRC field of the MAC frame, the STE10/100 will insert the TR code according to IEE802.3u, clause 24. ■ Receive Data Decapsulation When operating in 100BASE-TX mode the STE10/100 detects a JK code in a preamble as well as a TR code at the packet end. If a JK code is not detected, the STE10/100 will abort the reception of the frame and wait for a new JK code detection. If a TR code is not detected, the STE10/100 will report a CRC error. ■ Deferring The Inter-Frame Gap (IFG) time is divided into two parts: 1.IFG1 time (64-bit time): If a carrier is detected on the medium during this time, the STE10/100 will reset the IFG1 time counter and restart to monitor the channel for an idle again. 2.IFG2 time (32-bit time): After counting the IFG2 time the STE10/100 will access the channel even though a carrier has been sensed on the network. ■ Collision Handling The scheduling of re-transmissions are determined by a controlled randomization process called “truncated binary exponential back-off”. At the end of enforcing a collision (jamming), the STE10/100 delays before attempting to re-transmit the packet. The delay is an integer multiple of slot time. The number of slot times to delay before the nth re-transmission attempt is chosen as a uniformly distributed integer r in the range: 0 · r < 2k where k = min(n, 10) Field Description Preamble A 7-byte field of (10101010b) Start Frame Delimiter A 1-byte field of (10101011b) Destination Address A 6-byte field Source Address A 6-byte field Length/Type A 2-byte field indicated the frame is in IEEE802.3 format or Ethernet format. IEEE802.3 format: 0000H ~ 05DCH for Length field Ethernet format: 05DD ~ FFFFH for Type field Data *46 ~ 1500 bytes of data information CRC A 32-bit cyclic redundancy code for error detection
6.5.2 Transceiver Operation
The transceiver portion of the STE10/100 integrates the IEEE802.3u compliant functions of PCS (physical cod- ing sub-layer), PMA (physical medium attachment) sub-layer, and PMD (physical medium dependent) sub-layer for 100BASE-TX, and the IEEE802.3 compliant functions of Manchester encoding/decoding and transceiver for 10BASE-T. All the functions and operating schemes are described in the following sections. ■ 100BASE-TX Transmit Operation For 100BASE-TX transmissions, the STE10/100 transceiver provides the transmission functions of PCS, PMA, and PMD for encoding of MII data nibbles into five-bit code-groups (4B/5B), scrambling, serialization of scrambled code-groups, converting the serial NRZ code into NRZI code, converting the NRZI code into MLT3 code, and then driving the MLT3 code into the category 5 Unshielded Twisted Pair cable through an isolation transformer with the turns ratio of 1.414 : 1. ■ Data code-groups Encoder: In normal MII mode applications, the transceiver receives nibble type 4B data via the TxD0~3 inputs of the MII. These inputs are sampled by the transceiver on the rising edge of Tx-clk and passed to the 4B/5B encoder to generate the 5B code-group used by 100BASE-TX. ■ Idle code-groups: In order to establish and maintain the clock synchronization, the transceiver must keep transmitting signals to medium. The transceiver will generate Idle code-groups for transmission when there is no actual data to be sent by MAC. ■ Start-of-Stream Delimiter-SSD (/J/K/): In a transmission stream, the first 16 nibbles comprise the MAC preamble. In order to let a network partner delineate the boundary of a data transmission sequence and to authenticate carrier events, the transceiver will replace the first 2 nibbles of the MAC preamble with /J/K/ code-groups. ■ End-of-Stream Delimiter-ESD (/T/R/): In order to indicate the termination of normal data transmissions, the transceiver will insert 2 nibbles of /T/R/ code-group after the last nibble of the FCS. ■ Scrambling: All the encoded data (including the idle, SSD, and ESD code-groups) is passed to the data scrambler to reduce EMI by spreading the power spectrum using a 10-bit scrambler seed loaded at the beginning. ■ Data conversion of Parallel to Serial, NRZ to NRZI, NRZI to MLT3: After being scrambled, the 5B type transmission data at 25MHz will be converted to a 125HMz serial bit stream by the parallel-to-serial function. The bit stream will be further converted from NRZ to NRZI format, unless the conversion function is bypassed by clearing ENRZI (bit 7 of XR10) to 0. After NRZI conversion, the NRZI bit stream is passed through MLT3 encoder to generate the TP-PMD specified MLT3 code. By using MLT3 code, the frequency and energy content of the transmission signal is reduced in the UTP, making the system more easily compliant to FCC EMI specifications. ■ Wave-Shaper and Media Signal Driver: In order to reduce the energy of the harmonic frequency of transmission signals, the transceiver provides a wave-shaper prior the line driver to smooth the rising/ falling edge of transmission signals while maintaining the waveforms’ symmetry. The 100BASE-TX and 10BASE-T wave-shaped signals are both passed to the same media signal driver. This can simplify system design by employing a single external magnetic connection. ■ 100BASE-TX Receiving Operation For 100BASE-TX receiving operation, the transceiver provides the receiving functions of PMD, PMA, and PCS for incoming data signals through category 5 UTP cable and an isolation transformer with a 1:1 turns ratio. The receive transceiver portion includes the adaptive equalizer and baseline wander, MLT3 to NRZI data conversion, NRZI to NRZ conversion, serial to parallel conversion, a PLL for clock and data recovery, de-scrambler, and the 5B/4B decoder. ■ Adaptive Equalizer and Baseline Wander: High speed signals over unshielded (or shielded) twisted pair cable will experience attenuation and phase shift. These effects depend on the signal frequency, cable type, cable length and the cable connectors. Robust circuits in the transceiver provide reliable adaptive equalizer and baseline wander compensation for amplitude attenuation and phase shift due to
transmission line parasitics. ■ MLT3 to NRZI Decoder and PLL for Data Recovery: Following adaptive equalizer, baseline wander, the transceiver converts the resulting MLT3 to NRZI code, which is passed to the Phase Lock Loop circuits in order to extract the synchronous clock and the original data. ■ Data Conversions of NRZI to NRZ and Serial to Parallel: After the data is recovered, it will be passed to the NRZI-to-NRZ converter to produce a 125MHz serial bit stream. This serial bit stream will be packed to parallel 5B type for further processing. The NRZI to NRZ conversion may be bypassed by clearing ENRZI (bit 7 of XR10) to 0. ■ De-scrambling and Decoding of 5B/4B: The parallel 5B type data is passed to the de-scrambler and 5B/4B decoder to restore it to its original MII nibble representation. ■ Carrier sensing: The Carrier Sense (CRS) signal is asserted when the transceiver detects any 2 non- contiguous zeros within any 10-bit boundary of the receiving bit stream. CRS is de-asserted when ESD code-group or Idle code-group is detected. In half duplex mode, CRS is asserted during packet transmission or receive; in full duplex mode, CRS is asserted only during packet reception. ■ 10BASE-T Transmission Operation The parallel-to-serial converter, Manchester Encoder, Link test, Jabber and the transmit wave-shaper and line driver functions described in the section of “Wave-Shaper and Media Signal Driver” of “100BASE-T Transmission Operation” are also provided for 10BASE-T transmission. Additionally, Collision detection and SQE test for half duplex application are provided. ■ 10BASE-T Receive Operation Carrier sense function, receiving filter, PLL for clock and data recovery, Manchester decoder, and serial to parallel converter functions are provided to support 10BASE-T reception. ■ Loop-back Operation of transceiver The transceiver provides internal loop-back (also called transceiver loop-back) operation for both 100BASE-TX and 10BASE-T operation. The loop-back function can be enabled by setting XLBEN (bit 14 of XR0) to 1. In loop-back mode, the TX± and RX± lines are isolated from the media. The transceiver also provides remote loop-back operation for 100BASE-TX operation. The remote loop-back operation can be enabled by setting ENRLB (bit 9 of XR10) to 1. In 100BASE-TX internal loop-back operation, the data is routed from the transmit output of NRZ-to- NRZI converter and looped back to the receive input of NRZI-to-NRZ converter. In 100BASE-TX remote loop-back operation, data is received from RX± pins and passed through the receive path to the output of the data and clock recovery section, and then looped back to the input of the NRZI-to-MLT3 converter and out to the medium via the transmit line drivers. In 10BASE-T loop-back operation, the data is passed through the transmit path to the output of the Manchester encoder and then looped back into the input of the Phase Lock Loop circuit in the receive path. ■ Full Duplex and Half Duplex Operation of Transceiver The transceiver can operate in either full duplex or half duplex network applications. In full duplex, both transmission and reception can take place simultaneously. In full duplex mode, collision (COL) signal is ignored and carrier sense (CRS) signal is asserted only when the transceiver is receiving. In half duplex mode, transmission and reception can not take place simultaneously. In half duplex mode, the collision signal is asserted when transmitted and received signals collide, and carrier sense is asserted during both transmission and reception. ■ Auto-Negotiation Operation The Auto-Negotiation function provides the means to exchange information between the transceiver and the network partner to automatically configure both to take maximum advantage of their abilities. The Auto-Negotiation function is controlled by ANEN (bit 12 of XR0). During Auto-Negotiation information is exchanged with the network partner using Fast Link Pulses
tion function will proceed. Otherwise, Auto-Negotiation will not occur until ANEN (bit 12 of XR0) is set to 1. transceiver can turn off the circuit of either the 100BASE-TX or 10BASE-T when the other is active.
6.5.3 Flow Control in Full Duplex Application
implements the PAUSE function. Figure 14. MAC Control Frame Format of Slot-Times. The range of possible PAUSE times is 0 to 65535 Slot-Times. ■ The MAC Control Opcode field set to 0001h.
6 Octets Destination Address
6 Octets Source Address
2 Octets Length/Type = 88-08h
2 Octets MAC Control Opcode
for which the destination is requested to inhibit data frame transmission. been submitted to the MAC (i.e., once a transmit out of the MAC is begun, it can’t be interrupted). PAUSE time value, the STE10/100 exits the PAUSE state immediately. Figure 15. PAUSE operation receive state diagram
6.6 LED Display Operation
The STE10/100 provides 2 LED display modes; the detailed descriptions of their operation are described in the PIN Description section. ■ First mode - 3 LED displays: 100Mbps (on) or 10Mbps (off) Link (Remains on when link ok) or Activity (Blinks at 10Hz when receiving or transmitting collision-free) FD (Remains on when in Full duplex mode) or Collision (Blinks at 20Hz when collidions detected) ■ Second mode – 4 LED displays: Activity (Blinks at 10Hz when receiving or transmitting) FD (Remains on when in Full duplex mode) or Collision (Blinks at 20Hz when collisions detected)
6.7 Reset Operation
6.7.1 Reset whole chip
There are two ways to reset the STE10/100: Hardware reset via RST# pin (to ensure proper reset operation, the RST# signal should be asserted at least 100ms); and software reset via SWR (bit 0 of CSR0) being set to 1 (the STE10/100 will reset all circuits, set registers to their default values, and will clear SWR.
6.7.2 Reset Transceiver only
When XRST (bit 15 of XR0) is set to 1, the transceiver will reset its circuits, will initialize its registers to their default values, and clear XRST.
6.8 Wake on LAN Function
The STE10/100 can assert a signal to wake up the system when it has received a Magic Packet from the net- work. The Wake on LAN operation is described as follow. ■ The Magic Packet format: Valid destination address that can pass the address filter of the STE10/100 The payload of frame must include at least 6 contiguous ‘FF’ followed immediately by 16 repetitions of IEEE address. The frame can contain multiple ‘six FF + sixteen IEEE address’ pattern. Valid CRC ■ The Wake on LAN operation The Wake on LAN enable function is controlled by WOL (bit 18 of CSR18), which is loaded from EEPROM after reset or programmed by driver software. If WOL is set and the STE10/100 receives a Magic Packet, it will assert the PME# signal (active low) to indicate reception of a wake up frame and will set the PME status bit (bit 15 of CSR20).
6.9 ACPI Power Management Function
The STE10/100 has a built-in capability for Power Management (PM) which is controlled by the host system The STE10/100 will provide: ■ Compatibility with Device Class Power Management Reference Specification ■ Network Device Class, Draft proposal v0.9, October 1996 ■ Compatibility with ACPI, Rev 1.0, December 22, 1996 ■ Compatibility with PCI Bus Power Management Interface Specification, Rev 1.0, January 6, 1997
■ Compatibility with AMD Magic Packet™ Technology.
6.9.1 Power States
function context in place. The only network operation the STE10/100 can initiate is a wake-up event. When the STE10/100 is brought back to D0 from D3hot the software must perform a full initialization. without the RST# pin asserted. Table 13. Power Stage D3cold B3 All configuration lost.
7.0 GENERAL EEPROM FORMAT DESCRIPTION
Table 14. Connection Type Definition old ROM format version 0x01 is for STE10/100-MAC only.
86 IEEE network address: ID1, ID2, ID3, ID4, ID5, ID6
11 1 Reserved, should be zero. 14 0B Reserved, should be zero. 26 2 PCI Subsystem Vendor ID. 2E 2 CSR18 ( CR ) bit 31-16 recall data. 30 4E Reserved, should be zero.
Table 15. Connection Type Definition
8.0 ELECTRICAL SPECIFICATIONS AND TIMINGS
Table 16. Absolute Maximum Ratings Table 17. General DC Specifications
Table 18. AC Specifications
8.1 Timing Specifications
Table 19. PCI Clock Specifications Figure 16. PCI Clock Waveform Table 20. X1 Specifications Table 21. PCI Timing
Figure 17. PCI Timings
Table 22. Flash Interface Timings Figure 18. Flash write timings
DIM. mm inch A 3.04 3.40 0.12 0.134 A1 0.25 0.33 0.010 0.013 b 0.13 0.28 0.005 0.011 C 0.13 0.23 0.005 0.009 D 20 0.787 E 14 0.551 e 0.5 0.02 HD 23.2 0.913 HE 17.2 0.677 L1 1.60 0.063 ZD 0.75 0.03 ZE 0.75 0.03 ccc 0.12 0.005 Angle 0°(min.), 7°(max.) L dimension is measured at gauge plane at 0.25 above the seating plane A C 65102 103 128 ZE ZD E PIN 1 ID HE D HD e
0.7 DEGREES
b PQF128CM L MC D A -B0.12 .005 CDC
0.25 GAGE PLANE
PQFP128 (14x20x2.7mm) May 1999 1020818 OUTLINE AND MECHANICAL DATA
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com STE10/100