STD7LN80K5 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuits
  • 4 Package information
  • 4.1 DPAK (TO-252) type A2 package information
  • 4.2 DPAK (TO-252) packing information
  • 5 Revision history

Features

Order code VDS RDS(on) max. ID STD7LN80K5 800 V 1.15 Ω 5 A  Industry’s lowest RDS(on) x area  Industry’s best figure of merit (FoM)  Ultra-low gate charge  100% avalanche tested  Zener-protected

Applications

 Switching applications

Description

This very high voltage N-channel Power MOSFET is designed using MDmesh™ K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code Marking Package Packing STD7LN80K5 7LN80K5 DPAK Tape and reel DPAK AM15572v1_tab D(2, TAB) G(1) S(3)

1 Electrical ratings

Table 2: Absolute maximum ratings Symbol Parameter Value Unit VGS Gate-source voltage ± 30 V ID (1) Drain current (continuous) at TC = 25 °C 5 A ID (1) Drain current (continuous) at TC = 100 °C 3.4 A ID (2) Drain current (pulsed) 20 A PTOT Total dissipation at TC = 25 °C 85 W dv/dt(3) Peak diode recovery voltage slope 4.5 V/ns dv/dt(4) MOSFET dv/dt ruggedness 50 V/ns Tstg Storage temperature - 55 to 150 °C Tj Operating junction temperature Notes: (1)Limited by maximum junction temperature. (2)Pulse width limited by safe operating area. (3)ISD ≤ 5 A, di/dt ≤ 100 A/µs; VDS peak < V(BR)DSS, VDD=640 V (4)VDS ≤ 640 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 1.47 °C/W Rthj-pcb (1) Thermal resistance junction-pcb 50 °C/W Notes: (1)When mounted on FR-4 board of 1 inch², 2 oz Cu Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetetive or not repetetive (pulse width limited by Tjmax) 1.5 A EAS (Single pulse avalanche energy (starting Tj = 25 °C, ID = IAR; VDD = 50 V) 200 mJ

2 Electrical characteristics

TC = 25 °C unless otherwise specified Table 5: On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 mA 800 V IDSS Zero gate voltage Drain current VGS = 0 V, VDS = 800 V 1 µA VGS = 0 V, VDS = 800 V, TC = 125 °C 50 µA IGSS Gate-body leakage current VDS = 0 V, VGS = ±25 V ±10 µA VGS(th) Gate threshold voltage VDS = VGS, ID =100 µA 3 4 5 V RDS(on) Static drain-source on- resistance VGS = 10 V, ID = 2.5 A 0.95 1.15 Ω Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance VDS= 100 V, f = 1 MHz, VGS = 0 V - 270 - pF Coss Output capacitance - 22 - pF Crss Reverse transfer capacitance - 0.5 - pF Co(er) (1) Equivalent capacitance energy related VDS = 0 to 640 V, VGS = 0 V - 17 - nC Co(tr) (2) Equivalent capacitance time related - 48 - nC Rg Intrinsic gate resistance f = 1 MHz, ID=0 A - 7.5 - Ω Qg Total gate charge VDD = 640 V, ID = 5 A, VGS = 10 V (see Figure 15: "Test circuit for gate charge behavior") - 12 - nC Qgs Gate-source charge - 2.6 - nC Qgd Gate-drain charge - 8.6 - nC Notes: (1)Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS (2)Time related is defined as a constant equivalent capacitance giving the same stored energy as Coss when VDS increases from 0 to 80% VDSS Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD = 400 V, ID = 2.5 A, RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") - 9.3 - ns tr Rise time - 6.7 - ns td(off) Turn-off-delay time - 23.6 - ns tf Fall time - 17.4 - ns

Table 8: Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current 5 A ISDM (1) Source-drain current (pulsed) 20 A VSD (2) Forward on voltage ISD= 5 A, VGS = 0 V, - 1.6 V trr Reverse recovery time ISD = 5 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 276 ns Qrr Reverse recovery charge - 2.13 µC IRRM Reverse recovery current - 15.4 A trr Reverse recovery time ISD = 5 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 402 ns Qrr Reverse recovery charge - 2.79 µC IRRM Reverse recovery current - 13.9 A Notes: (1)Pulse width is limited by safe operating area (2)Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)GSO Gate-source breakdown voltage IGS = ±1 mA, ID = 0 A 30 - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry.

2.2 Electrical characteristics (curves)

Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance

3 Test circuits

Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

4.1 DPAK (TO-252) type A2 package information

Figure 20: DPAK (TO-252) type A2 package outline

Table 10: DPAK (TO-252) type A2 mechanical data Dim. mm Min. Typ. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 5.10 5.25 E 6.40 6.60 E1 5.10 5.20 5.30 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 L1 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 1.00 R 0.20 V2 0°

Figure 21: DPAK (TO-252) recommended footprint (dimensions are in mm)

4.2 DPAK (TO-252) packing information

Figure 22: DPAK (TO-252) tape outline

Figure 23: DPAK (TO-252) reel outline Table 11: DPAK (TO-252) tape and reel mechanical data Tape Reel Dim. mm Dim. mm Min. Max. Min. Max. A0 6.8 7 A 330 B0 10.4 10.6 B 1.5 12.1 C 12.8 13.2 D 1.5 1.6 D 20.2 D1 1.5 G 16.4 18.4 E 1.65 1.85 N 50 F 7.4 7.6 T 22.4 K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3

5 Revision history

Table 12: Document revision history Date Revision Changes 16-Dec-2015 1 First release.