STD50NH02L STMICROELECTRONICS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 12

Technical content

N-CHANNEL 24V - 0.0085 Ω - 50A DPAK/IPAK STripFET™ III POWER MOSFET ■ TYPICAL R DS (on) = 0.0085 Ω @ 10 V ■ TYPICAL R DS (on) = 0.012 Ω @ 5 V ■ R DS(ON) * Qg INDUSTRY’s BENCHMARK ■ CONDUCTION LOSSES REDUCED ■ SWITCHING LOSSES REDUCED ■ LOW THRESHOLD DEVICE ■ THROUGH-HOLE IPAK (TO-251) POWER PACKAGE IN TUBE (SUFFIX “-1") ■ SURFACE-MOUNTING DPAK (TO-252) POWER PACKAGE IN TAPE & REEL (SUFFIX “T4")

DESCRIPTION

The STD50NH02L utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology. This is suitable fot the most demanding DC-DC converter application where high efficiency is to be achieved.

APPLICATIONS

■ SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY DC/DC CONVERTES

Ordering Information

TYPE VDSS R DS(on) ID STD50NH02L 24 V < 0.0105 Ω 50 A SALES TYPE MARKING PACKAGE PACKAGING STD50NH02LT4 D50NH02L TO-252 TAPE & REEL STD50NH02L-1 D50NH02L TO-251 TUBE IPAK TO-251 (Suffix “-1”) DPAK TO-252 (Suffix “T4”) ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Vspike(1) Drain-source Voltage Rating 30 V VDS Drain-source Voltage (VGS = 0) 24 V VDGR Drain-gate Voltage (RGS = 20 kΩ ) 24 V VGS Gate- source Voltage ± 20 V ID Drain Current (continuous) at TC = 25°C 50 A ID Drain Current (continuous) at TC = 100°C 36 A IDM (2) Drain Current (pulsed) 200 A Ptot Total Dissipation at TC = 25°C 60 W Derating Factor 0.4 W/°C EAS (3) Single Pulse Avalanche Energy 280 mJ Tstg Storage Temperature -55 to 175 °CTj Max. Operating Junction Temperature INTERNAL SCHEMATIC DIAGRAM

ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED) OFF ON (4) DYNAMIC Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max 2.5 100 275 °C/W °C/W Symbol Parameter Test Conditions Min. Typ. Max. Unit V (BR)DSS Drain-source Breakdown Voltage ID = 25 mA, VGS = 0 24 V IDSS Zero Gate Voltage Drain Current (VGS = 0) VDS = 20 V VDS = 20 V TC = 125°C µA µA IGSS Gate-body Leakage Current (VDS = 0) VGS = ± 20V ±100 nA Symbol Parameter Test Conditions Min. Typ. Max. Unit VGS(th) Gate Threshold Voltage VDS = VGS I D = 250 µA 1 1.8 V R DS(on) Static Drain-source On Resistance VGS = 10 V I D = 25 A VGS = 5 V ID = 12.5 A 0.0085 0.012 0.0105 0.020 Ω Ω Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (4) Forward Transconductance VDS = 15 V I D = 25 A 27 S C iss C oss C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 16V f = 1 MHz VGS = 0 1400 400 pF pF pF R G Gate Input Resistance f = 1 MHz Gate DC Bias = 0 Test Signal Level = 20 mV Open Drain 1 Ω

(1) Garanted when external Rg=4.7 Ω and tf < tfmax. (4) Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %. (2) Pulse width limited by safe operating area (5) Qoss = C oss*Δ Vin , C oss = C gd + C ds . See Appendix A (3) Starting Tj = 25 oC, ID = 25A, VDD = 15V Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time VDD = 10 V I D = 25 A R G = 4.7 Ω V GS = 10 V (Resistive Load, Figure 3) 130 ns ns Q g Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge V DD = 10 V ID = 50 A VGS = 10 V 24 3.4 32 nC nC nC Q oss(5) Output Charge VDS = 16 V VGS = 0 V 9.4 nC Symbol Parameter Test Conditions Min. Typ. Max. Unit td(off) tf Turn-off Delay Time Fall Time VDD = 10 V I D = 25 A R G = 4.7Ω, V GS = 10 V (Resistive Load, Figure 3) 16 21.6 ns ns Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD ISDM Source-drain Current Source-drain Current (pulsed) 200 A A VSD (4) Forward On Voltage ISD = 25 A VGS = 0 1.3 V trr Q rr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current ISD = 50 A di/dt = 100A/µs VDD = 20 V T j = 150°C (see test circuit, Figure 5) ns nC A ELECTRICAL CHARACTERISTICS (continued) Safe Operating Area Thermal Impedance

Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations

Normalized Gate Threshold Voltage vs Temperature Normalized on Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized Breakdown Voltage vs Temperature . .

Fig. 1: Unclamped Inductive Load Test CircuitFig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times

DIM. mm inch A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A3 0.7 1.3 0.027 0.051 B 0.64 0.9 0.025 0.031 B2 5.2 5.4 0.204 0.212 B3 0.85 0.033 B5 0.3 0.012 B6 0.95 0.037 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 15.9 16.3 0.626 0.641 L 9 9.4 0.354 0.370 L1 0.8 1.2 0.031 0.047 L2 0.8 1 0.031 0.039 A C H D LL2 1 3 = = B E G = = = = TO-251 (IPAK) MECHANICAL DATA 0068771-E

DIM. mm inch A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.9 0.025 0.035 B2 5.2 5.4 0.204 0.212 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 9.35 10.1 0.368 0.397 L2 0.8 0.031 L4 0.6 1 0.023 0.039 DL2 1 3 B E G A C H A1 DETAIL "A" DETAIL "A" TO-252 (DPAK) MECHANICAL DATA 0068772-B

Buck Converter: Power Losses Estimation The power losses associated with the FETs in a Synchronous Buck converter can be estimated using the equations shown in the table below. The formulas give a good approximation, for the sake of performance comparison, of how different pairs of devices affect the converter efficiency. However a very important parameter, the working temperature, is not considered. The real device behavior is really dependent on how the heat generated inside the devices is r emoved to allow for a safer working junction temperature. The low side ( SW2) device requires:

  • Very low RDS(on) to reduce conduction losses
  • Small Qgls to reduce the gate charge losses
  • Small Coss to reduce losses due to output capacitance
  • Small Qrr to reduce losses on SW1 during its turn -on
  • The C gd/Cgs ratio lower than V th/Vgg ratio especially with low drain to source voltage to avoid the cross conduction phenomenon; The high side (SW1) device requires:
  • Small R g and L s to allow higher gate current peak an d to limit the voltage feedback on the gate
  • Small Qg to have a faster commutation and to reduce gate charge losses
  • Low RDS(on) to reduce the conduction losses.

High Side Switch (SW1) Low Side Switch (SW2) conductionP d*I *R 2 LDS(on)SW1 )1(*I *R 2 LDS(on)SW2 d− switchingP g L I I*f*)Q(Q*V gd(SW1)gsth(SW1)in + Zero Voltage Switching Recovery Not Applicable 1 f*Q*V rr(SW2)in diodeP Conduction Not Applicable f*t*I*V deadtimeLf(SW2) )gate(QGP f*V*Q ggg(SW1) f*V*Q gggls(SW2) QossP f*Q*V oss(SW1)in f*Q*V oss(SW2)in Parameter Meaning d Duty-cycle Qgsth Post threshold gate charge Qgls Third quadrant gate charge Pconduction On state losses Pswitching On-off transition losses Pdiode Conduction and reverse recovery diode losses Pgate Gate drive losses QossP Output capacitance losses

1 Dissipated by SW1 during turn-on

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics  2003 STMicroelectronics - All Rights Reserved All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com