STCOM STMICROELECTRONICS | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Description
- 1.1 Device architecture
- 1.2 Power line communication (PLC) sub-system
- 1.2.1 Real-time engine (RTE)
- 1.2.2 Digital front-end (DFE)
- 1.2.3 Analog front-end (AFE)
- 1.2.4 Line driver
- 1.3 Application core sub-system
- 1.3.1 ARM ® Cortex™-M4F core
- 1.3.2 Floating point unit (FPU)
- 1.3.3 Nested vectored interrupt controller (NVIC)
- 1.3.4 DMA controller (DMA)
- 1.3.5 Memory protection unit (MPU)
- 1.3.6 Debug and trace
- 1.3.7 General purpose input/outputs (GPIOs)
- 1.3.8 Multi-AHB bus matrix
- 1.3.9 Timers and watchdog
- 1.3.10 CRC (cyclic redundancy check) calculation unit
- 1.3.11 Communication interfaces
- 1.4 Cryptographic engine (CRYP)
- 1.4.1 True random number generator (TRNG)
- 1.4.2 Pseudo random number generator (PRNG)
- 1.5 Interprocessor communication (IPC)
- 1.6 Memories
- 1.6.1 Embedded Flash memory
- 1.6.2 One-time programmable (OTP) section
- 1.6.3 Embedded SRAM
- 1.6.4 Flexible static memory controller (FSMC)
- 1.7 Reset, control, clock generation (RCC) and system controller
- 1.8 Power management
Features
Integrated differential PLC analog front-end – PGA with automatic gain control and ADC – Current DAC with transmission predriver – Digital transmissi on level control – Zero crossing comparator – Up to 500 kHz PLC signal bandwidth Integrated dual line driver – 14 V p-p single ended, 28 V p-p differential output range – Very high linearity for EMC compliance – Externally configurable amplifier topology – 1 A rms max. current – Embedded overtemperature protection – Suitable for all PLC signals up to 500 kHz Fully reprogrammable real-time engine (RTE) modem for PLC standards up to 500 kHz Integrated application core: ARM ® 32-bit Cortex™-M4F CPU – 96 MHz maximum frequency – 8-channel direct memory access controller – 8-region memory protection unit – Serial wire and JTAG interfaces – Cortex-M4 Embedded Trace Macrocell™ – Up to 86 multiplexed GPIOs – 11 timers – 1 flexible CRC calculation unit – 5 USARTs (ISO 7816 compliant), 5 SPI, 3 I – 12-bit general purpose ADC with 6 channels Cryptographic engine – AES 128/192/256 engine – True random number generator Memories – 640 kB or 1 MB of embedded Flash – 128 kB of embedded SRAM – 8 kB of embedded shared RAM – Flexible static memory controller Clock management – 24 MHz external crystal for system clock with internal QFS synthesizer – 32.768 kHz external crystal for RTC Power management – 3.3 V and 8 - 18 V external supply voltages – 1.2 V and 5 V integrated linear regulators – Normal and low power modes Real-time clock (RTC) – VBAT supply with battery health monitoring for RTC and backup registers -40 °C to +85 °C operating temperature range
Applications
Smart metering, smart grid and “Internet of Things” applications Compliant with CENELEC, FCC, ARIB regulations TQFP176 (20 x 20 x 1 mm)
1 Description
and a high-performance application core. The STCOM basic block diagram is shown in Figure 1. Figure 1. STCOM basic block diagram
1.1 Device architecture
The architecture is composed of the following parts: 1. PLC front-end including digital front-end and analog front-end 2. PLC line driver 3. Real-time engine: the digital core running the lower layers of the PLC protocol stack and implementing modulation and demodulation 4. Protocol engine: the main digital core for running the upper layers of the PLC protocol stack 5. Wide range of peripherals logically divided into 4 blocks: – Basic peripherals – Com1 peripherals – Com2 peripherals – Crypto peripherals. The STCOM detailed architecture is shown in Figure 2.
Figure 2. STCOM detailed architecture
1.2 Power line communic ation (PLC) sub-system
The STCOM device embeds a full narrow band power line communication (NB-PLC) sub- system, comprising the RTE, DFE, AFE and line driver. The AFE and line driver have been designed for a differential power line interface; however, single-ended operation is possible for simpler hardware application development. The DC to 500 kHz signal bandwidth is supported, targeting a number of possible NB-PLC solutions.
1.2.1 Real-time engine (RTE)
To match a performance required by emerging NB-PLC standards, the STCOM embeds a proprietary dedicated reprogrammable machine, the real-time engine. It is able to address specific functionalities exploited by OFDM and the ones adopted in the current and future NB- PLC standards in an efficient way.
1.2.2 Digital front-end (DFE)
Transmission and reception filter chains The DFE includes programmable transmission/reception digital filter chains to fit the signal bandwidth in different PLC modulation cases. The ADC and DAC clock frequencies are controlled by the DFE to get the right sample rate fitting the filter chain configuration. Automatic gain control (AGC) The DFE implements the automatic gain control (AGC) block for the PGA, whose purpose is to adapt the signal to the ADC dynamic. Current control (CC) The DFE includes also the current control (CC) block for the line driver to limit the maximum output current.
1.2.3 Analog front-end (AFE)
The STCOM AFE features a programmable gain amplifier (PGA) and a dedicated analog-to- digital converter (ADC) to achieve high RX sensitivity and a wide input range. Transmission chain The transmitted signal, generated in the digital domain, is fed into a dedicated digital-to- analog converter (DAC). The DAC output is then fed into a predriver for buffering and applying an additional gain before the line driver.
The mains line zero crossing can be detected by providing a mains synchronous bipolar (AC) signal at the input of this comparator. The zero crossing comparator provides positive and negative event information (rising/falling edge or high/low level).
1.2.4 Line driver
The STCOM is equipped with an integrated high-performance dual power line driver. It has very low distortion, allowing the device to comply with EMC requirements. When supplied at maximum voltage, the line driver is capable to provide 28 V p-p in differential configuration or 14 V p-p in single-ended configuration. The output current can reach 1 A rms in both differential and single-ended configurations, in order to drive very low power line impedance. Any overtemperature event will force the line driver to shut down, thus preventing the STCOM to get damaged.
1.3 Application core sub-system
1.3.1 ARM ® Cortex™-M4F core
The Cortex™-M4 processor is built on a high-performance processor core, with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high end processing hardware including IEEE754- compliant single precision (32-bit) floating point computation, a range of a single cycle and SIMD multiplication and multiply with accumulate capabilities, saturating arithmetic and dedicated hardware division. To facilitate the design of cost-sensitive devices, the Cortex™-M4 processor implements tightly coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex™-M4 processor implements a version of the Thumb ® instruction set based on Thumb-2® technology, ensuring high code density and reduced program memory requirements. The Cortex™-M4 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers. The Cortex™-M4 processor provides multiple interfaces using AMBA™ technology to provide high-speed, low latency memory accesses. It supports unaligned data accesses and implements atomic bit manipulation that enables faster peripheral controls, system spinlocks and thread-safe Boolean data handling.
1.3.2 Floating point unit (FPU)
point and floating point data formats, and floating point constant instructions.
2008 A, IEEE Standard for Binary Floating-point Arithmetic©, referred to as the IEEE 754
16 double word registers for load, store, and move operations.
1.3.3 Nested vectored interrupt controller (NVIC)
Table 1. Cortex™-M4F core configuration
Table 2. Interrupt definition and position
Table 2. Interrupt definition and position (continued)
1.3.4 DMA controller (DMA)
to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. designed to provide the maximum peripheral bandwidth (AHB/APB). between source and destination are independent.
Table 3. DMA channels muxing scheme
1.3.5 Memory protection unit (MPU)
The MPU divides the memory map into up to 8 regions, and defines the location, size, access permissions, and memory attributes of each region. It supports: Independent attribute settings for each region Overlapping regions Export of memory attributes to the system. Background region When memory regions overlap, memory access is affected by the attributes of the region with the highest number. The background region has the same memory access attributes as the default memory map, but is accessible from privileged software only. The MPU is useful to isolate and protect different parts of the firmware by giving different levels of access privileges. If a part of the firmware tries to access a memory location that is prohibited by the MPU, the processor generates a fault. This causes a fault exception that could be detected by the privileged firmware, which can take the appropriate action. The MPU is optional and can be bypassed for applications that do not need it.
1.3.6 Debug and trace
Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. Embedded Trace Macrocell™ (ETM) The ARM Embedded Trace Macrocell provides greater visibility of the instruction and data flow inside the Cortex™-M4 core by streaming compressed data at a very high rate from the STCOM device through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is then connected to a host in order to record and then format the information for displaying and analysis.
1.3.7 General purpose input/outputs (GPIOs)
The STCOM device has 11 GPIOs ports named from GPIO00 to GPIO10. Each port is able to manage 8 pins, except the GPIO08 port that manages 6 pins. Each GPIO pin can be individually configured by software as output (push-pull or open drain, with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down) or as peripheral alternate functions (with or without pull-up or pull-down). Each GPIO pin can also generate interrupt depending on a level (low and high), or a transactional value of the pin (rising or falling edge). External interrupt Each GPIOs port can generate interrupts. For each port one interrupt line is dedicated. The pins of one port share the same interrupt line.
1.3.8 Multi-AHB bus matrix
The 32-bit multi-AHB bus matrix interconnects all the masters (Cortex™-M4, DMA, and real- time engine) and the slaves (Flash memory, RAM, AHB and APB peripherals, and real-time engine) and ensures a seamless and efficient operation even when several high-speed peripherals work simultaneously.
1.3.9 Timers and watchdog
The STCOM embeds 8 general purpose timers, two advanced timers and one window watchdog. The Cortex™-M4 is also equipped with a SysTick timer. General purpose timer (GPT) The STCOM device includes 8 full-featured general purpose timers based on a 16-bit autoreload up/down counter and a 16-bit programmable prescaler. Advanced timers (AT) The STCOM includes 2 advanced-control timers based on a 16-bit autoreload up/down counter driven by a 16-bit programmable prescaler. They all feature 4 independent channels for input capture, output compare, PWM generation or one pulse mode output. It may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM, complementary PWM with deadtime insertion). Window watchdog (WWDG) The window watchdog is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates a device reset on expiry of a programmed time period, unless the program refreshes the contents of the down counter register. A device reset is also generated if the down counter value is refreshed before the down counter has reached the proper window register value. This implies that the counter must be refreshed in a limited window. The window watchdog is based on a 7-bit free-running down counter with two conditional resets: the down counter is reloaded outside the window or the down counter value becomes less than 0x40. The window watchdog supports early wake-up interrupt trigged when the down counter is equal to 0x40. SysTick timer The Cortex™-M4 has a 24-bit system timer, SysTick, which counts down from the programmable reload value to zero. It supports the autoreload and can generate a maskable system interrupt when the counter reaches zero.
1.3.10 CRC (cyclic redund ancy check) calculation unit
The cyclic redundancy check (CRC) is a widely used method for detecting errors. The CRC calculation unit is used to get a CRC code in a flexible way using a configurable polynomial. Output data size can be selected between 8, 16, 24 or 32 bits. Input data size can be configured between 1, 8, 16, 24 or 32 bits with selectable bit and byte endianness. The CRC unit allows the specification of the initial value (all zero, all one, or a generic value) and the possibility to select an automatic XOR with all one when reading the data output.
1.3.11 Communication interfaces
Inter-integrated circuit interface (I2C) The STCOM embeds 3 I2C bus interfaces that can operate in multimaster and slave modes. They can support the Standard and Fast modes. They support the 7/10-bit addressing mode and the 7-bit dual addressing mode (as slave). A hardware CRC generation/verification is embedded. The I2C peripherals can be served by DMA and support SMBus 2.0/PMBus™ operations. Universal synchronous/asynchronous receiver transmitters (USART) The STCOM embeds 5 universal synchronous/asynchronous receiver transmitters. These five interfaces provide asynchronous communication, IrDA® SIR ENDEC support, a multiprocessor communication mode, single-wire half-duplex communication mode and have an LIN Master/Slave capability. The peripherals also provide hardware management of the CTS and RTS signals, a Smartcard mode (ISO 7816 compliant) and a SPI-like communication capability. All interfaces can be served by the DMA controller. Serial peripheral interface (SPI) The STCOM embeds 5 SPIs in slave and master modes in full-duplex and simplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card™/MMC™ modes. All SPIs can be served by the DMA controller. The SPI interface can be configured to operate in a TI™ mode for communications in master mode and slave mode. Controller area network (CAN) The STCOM embeds 2 CAN modules able to perform communication according to the CAN protocol version 2.0 part A and B. The bitrate can be programmed to values up to 1 MBit/s. For communication on a CAN network, individual message objects are configured. Each message object has its own identifier mask. The message objects and identifier masks are stored in the 256 byte size message RAM with a programmable FIFO mode. All functions concerning the handling of messages are implemented in the message handler. Those functions are the acceptance filtering, the transfer of messages between the CAN core and the message RAM, and the handling of transmission requests as well as the generation of the module interrupt.
General purpose analog-to-digital converter (ADC) One 12-bit SAR ADC working at a maximum conversion rate of 2 Msps is embedded in the STCOM. The ADC has 6 external available input channels performing conversion in a single, continuous or scan mode. The core accesses to the peripheral through a 4x12-bit FIFO interface. The ADC can be served by the DMA controller. Additional 2 channels are internally used to monitor the VBAT and the low power temperature sensor.
1.4 Cryptographic engine (CRYP)
The STCOM embeds an advanced hardware AES peripheral which implements an advanced standard cryptographic algorithm according to the NIST FIPS 197. The block processes 128-bit data blocks using a key with the following possible sizes: 128, 192, 256 bits. The peripheral also supports the following modes: “Electronic Code Book” (ECB), “Cipher Block Chaining” (CBC), “Counter “mode (CTR), “Galois/Counter Mode” (GCM), GMAC and CCM modes. The peripheral is able to encrypt and decrypt data. Interrupt can be generated when one operation is finished.
1.4.1 True random number generator (TRNG)
The STCOM embeds a TRNG processor based on a continuous analog noise that provides a random 16-bit value. To avoid pseudo random sequences, two consecutive accesses have to be performed when the ready bit in the status register is set to 1.
1.4.2 Pseudo random num ber generator (PRNG)
The STCOM embeds a PRNG processor that provides a pseudo random 32-bit value. Initial seed can be configured by software.
1.5 Interprocessor communication (IPC)
The Cortex™-M4 core and the real-time engine communicate by means of an additional 8 kByte shared static RAM. This memory can be accessed by the two cores through an interprocessor communication block that guarantees coherent and consistent read and modify operations, to provide several functionalities to the system, among the others: Configuration of real-time engine modes and functionalities during the normal working operations Data and information exchange between the Cortex™-M4 and real-time engine in both directions. The Cortex™-M4 wake up from a low power mode triggered by the real-time engine. The real-time engine wakes up from a low power mode triggered by the Cortex™-M4.
1.6 Memories
1.6.1 Embedded Flash memory
1.6.2 One-time program mable (OTP) section
firmware in order to protect user confidential information (see Section 1.12). Table 4. Embedded Flash sectors
1.6.3 Embedded SRAM
The STCOM device has 128 kB of a static RAM. The Cortex™-M4 can perform byte, half word (16 bits) or full word (32 bits) access to the SRAM at maximum speed, with zero wait states for both read and write operations. The SRAM start address is 0x20000000, the end address is 0x20001FFFF. The SRAM is split into two blocks of 64 kB with a capability for concurrent access by AHB master sub-systems. The Cortex™-M4 can also execute a code from the RAM at a zero wait state.
1.6.4 Flexible static memory controller (FSMC)
The STCOM embeds a FSMC peripheral able to interface external memory devices. The types of memory supported are: Asynchronous parallel NOR Flash with up to 21-bit address bus (no synchronous parallel NOR supported) Asynchronous SRAM memories The data bus can be selected between 16 bits or 8 bits (reducing the total amount of accessible memory), for little or big endian operation. The FSMC peripheral can connect up to 2 memories with 2 independent chip select lines (Ebar). The maximum size of each memory is 4 MB. Having 2 chip select lines, the maximum external memory size is 8 MB.
1.7 Reset, control, cl ock generation (RCC) and system controller
blocks. Figure 3 shows the interaction between these blocks. Figure 3. Reset, clock and system controller interaction peripherals can be forced through MISC registers.
24 MHz source. Digital blocks can also use the external sources as clock reference. The clock strategy is depicted in Figure 4. Figure 4. STCOM clock tree
At a startup the 24 MHz oscillator clock is selected. This source must be always present to allow the STCOM starting correctly. 24 MHz can be provided by a quartz crystal or by any other source. In this latter case, the clock must be provided through the MCLK_IN pin while the MCLK_OUT pin must be tied to DGND. 32.768 KHz must be provided by a quartz crystal. APB peripherals can work up to 48 MHz. Each PCLK prescaler to the sub-systems should be configured to respect this maximum frequency. The general purpose ADC clock can run up to 33 MHz. The RTC core uses only the 32 KHz external oscillator. The TRNG can work with the external 32 kHz or with the internal cpu_hclk. If the internal clock is selected, the divisor should be configured to provide an accurate 32 kHz clock in order to respect the requirements for a true random generation. One master clock output line can be enabled. The MCO1 is multiplexed with one general purpose I/O and can take one of the QFS outputs with a configurable prescaler.
1.8 Power management
The STCOM should be powered with, at least, two external supply voltages: 3.3 V for I/Os, embedded Flash, QFS, DAC, OSC, ADC general purpose, 1.2 V regulator 8 - 18 V for line driver The device needs also two more supply voltages that can be generated internally: 1.2 V for digital cores and logic, embedded Flash, QFS and oscillator 5 V for the PLC AFE
1.2 V and 5 V can be provided by two internal linear regulators connected respectively to
DVDD_1V2 and AVDD_5V pins and supplied respectively by DVDD_3V3_REG and PVCC pins. A bypass mode is available for the 1.2 V regulator in case an external source is used. The power-on reset (POR) is conditioned by the level of DVDD_3 V3_IO and DVDD_1V2: at power on, the whole STCOM device is kept under reset until the two supply voltages are above the respective turn-on thresholds named V(DVDD_3 V3_IO)_TH and V(DVDD_1V2)_TH, while the device is turned off as soon as one of the voltages goes below its turn-off thresholds, namely V(DVDD_3 V3_IO)_TL and V(DVDD_1V2)_TL. An internal comparator checks the supply voltage on AVDD_5V_AFE as well, enabling the use of the PLC AFE when the voltage is above V(AVDD_5V_AFE)_TH and disabling it when the voltage goes below V(AVDD_5V_AFE)_TL. Refer to Figure 5 and Figure 6 for the detailed power supply scheme.
Figure 5. Power supply scheme - digital section
Figure 6. Power supply scheme - PLC AFE and line driver section
In case the RTC peripheral is used, the VBAT pin shall be supplied (2.0 V to 3.6 V) for the RTC core operation and persistence of backup registers. An external battery or a similar power source can be used. The VBAT operation is activated, through an on-chip power switch, when the DVDD_3V3_IO is not present. In this case the main core of the RTC and the backup registers are under the VBAT domain. The application can constantly monitor the health of the battery by reading the voltage level present at the VBAT pin through the channel 7 of the general purpose 12-bit ADC. A dedicated cutoff switch has been included to avoid continuous leakage from the battery when the ADC is not sampling the line.
1.9 Low power modes
A clock gating is available for any peripheral in order to save all the dynamic power contributes related the resources not used by the application. The CPU is able to run at maximum frequency but, in case lower speed is sufficient to meet the application requirements, also scaled values are allowed. The CPU could be in low power modes waiting for wake-up events.
1.10 Real-time clock (RTC ) and backup registers
The STCOM embeds an integrated real-time clock (RTC). The RTC provides a hardware calendar implementation, instead of a simple 32-bit free-running counter. The calendar can be initialized to set the current time/date of the system and provide information on sub- seconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year. Software can program the daylight saving compensation; it can control two programmable alarms (with interrupt function) that can be triggered by any combination of the calendar fields. Synchronization can be done with an external clock using the sub-second shift feature. RTC maskable interrupts/events are: Alarms: two alarms are present Timestamps: two timestamps are present Tamper: two tamper detection inputs are present The RTC is clocked with a 32.768 kHz external crystal and has coarse calibration (periodic digital calibration), smooth calibration (0.954 ppm) and analog calibration functionalities.The 1 Hz /512 Hz internal reference clock is optionally available on RTC_TAMPB for calibration. The RTC has also twenty 32-bit backup registers (80 bytes), available for user defined data storage. The possibility that backup registers are reset when a tamper detection event occurs is selectable by software.
1.11 Temperature sensors an d overtemperature protection
The STCOM embeds an overtemperature protection mechanism, with fixed temperature threshold, preventing the device from overheating. This automatic protection acts by shutting down the PLC line driver when overheating occurs during PLC transmission. The normal operation of the line driver is restored automatically as the overtemperature event has ended. In addition to the overtemperature automatic protection, information from two temperature sensors is provided: The line driver temperature sensor The low power temperature sensor The first sensor monitors the line driver temperature and can be used by the RTE to prevent the line driver to be shut down abruptly by the overtemperature protection. The way to use this information may depend on the protocol and on the version of the RTE firmware, so its usage (if any) will be described within the specific firmware documentation released by STMicroelectronics The second sensor monitors the temperature of the low power section of the device. It is internally connected to the channel 8 of the general purpose 12-bit ADC (see Section : General purpose analog-to-digital converter (ADC) on page 19 for further details) and it can be used by the application for its own purposes. The accuracy of the sensors is guaranteed by design. In case a higher accuracy is required on the low power temperature sensor, the user shall adopt its own calibration procedure during the application manufacturing.
1.12 Boot modes
The STCOM provides different security levels of protection: 1. Level 1: unsecure The Cortex™-M4 is accessible through the JTAG and it's possible to download the firmware in the embedded Flash using debugger plug-in or to load it from the external NVM using the system boot functionality. It's also possible to download customer OTP data such as cryptography keys. The shadow sector is not accessible. 2. Level 2: secure The JTAG is blocked and it's not possible to access the embedded Flash for external read or write operation. It's possible to load the ciphered firmware image from the external NVM and upgrade the firmware thanks to the IAP functionality. Read access to the embedded Flash is possible to the Cortex TM-M4 code, including the shadow sector. 3. Level 3: secure and locked The JTAG is blocked and it's not possible to access the embedded Flash for external read or write operation. Some embedded Flash sectors are locked. It's possible to upgrade the firmware thanks to the IAP functionality unless the new image tries to change a locked area. Read access to the embedded Flash is possible to the Cortex TM-M4 code, including the shadow sector.
- Level 4: secure for customer loader
- Level 1*: secure erase and unlocking
erased including the customer OTP data. The shadow sector is not accessible. In order to respect these security requirements, the STCOM embeds a bootloader code.
- Normal mode: this is the standard way of booting the code and eventually load (or
restore) a new image version from the external NVM.
- Customer OTP write mode: in this mode the user can write its security keys and data
the firmware upgrade is left to a customer bootloader.
- Unlocking mode: this is the boot mode that enables again all the debug feature.
- Low power mode: the minimal boot mode to guarantee low power operations. The
MHz (the user can then scale the clock up or down). Table 5. Boot mode and security level relationship
Table 6 shows the values of the boot pins for each boot mode.
1.13 System reprogrammability
implement its own bootloader.
1.13.1 In-system programming (ISP)
port. This mode can be inhibited to enhance the security level of the device.
1.13.2 In-application programming (IAP)
its dedicated bootloader to perform IAP with the activation of a specific security level. Table 6. Boot modes and BOOT0/1 pin values
2 Pinout and pin description
2.1 Pin definition
Figure 7. TQFP176 pinout
Table 7. Pin description
1 GPIO00_3 D I/O I General purpose I/O, SPI1_MOSI, AT1_CH_1,
2 GPIO00_2 D I/O I General purpose I/O, SPI1_SS, AT1_BKIN,
3 GPIO00_1 D I/O I General purpose I/O, USART0_CTS, FSMC_PCAD_19
5 GPIO00_0 D I/O I General purpose I/O, USART0_RTS, FSMC_PCAD_20
6 USART0_RXD D I I USART0_RXD
7 USART0_TXD D O I USART0_TXD
8 SPI0_SSn D OD I SPI0_SSn
9 SPI0_SCLK D O I SPI0_SCLK
10 SPI0_MISO D I I SPI0_MISO
11 SPI0_MOSI D O I SPI0_MOSI
13 DGND S - - Embedded Flash memory ground
15 RESERVED - - Reserved, tie to DGND
16 BOOT0 D I I Boot mode selector pin 0
17 BOOT1 D I I Boot mode selector pin 1
18 JTAG_TRSTn D I I JTAG test reset - active low
19 JTAG_TDI D I I JTAG test data input
20 JTAG_TMS D I I JTAG test mode select input, SWIO
21 JTAG_TCK D I I JTAG test clock input, SWCLK
22 JTAG_TDO D O I JTAG test data output, SWV
25 MCLK_IN A - - 24 MHz oscillator input
26 MCLK_OUT A - - 24 MHz oscillator output
31 DGND S - - QFS ground
32 AVDD_5V_PGA S I I PGA 5 V supply
33 RX_INN A I I PGA negative input
34 RX_INP A I I PGA positive input
35 AGND S - - PGA ground
36 ZC_IN A I I Zero crossing comparator input
37 ZC_AGND_REF A I I Zero crossing comparator ground reference - connect to
38 AVDD_5V_AFE S I I PLC AFE 5 V supply + receiver ADC supply
39 PVCC S I I PA supply
40 PGND S - - PA ground
41 PA2_OUT A O O PA2 output
42 PA2_OUT A O O PA2 output
43 PA1_OUT A O O PA1 output
44 PA1_OUT A O O PA1 output
45 PGND S - - PA ground
46 PVCC S I I PA supply / 5 V regulator input voltage
47 PA1_INN A I I PA1 inverting input
48 PA1_INP A I I PA1 non-inverting input
49 PA2_INP A I I PA2 non-inverting input
50 PA2_INN A I I PA2 inverting input
51 AGND S - - 5 V regulator ground
52 CSF A I/O I/O Current sense feedback
53 AVDD_5V S I/O I/O 5 V regulator ou tput / external supply input
54 RESERVED - - - Reserved - connect to AGND
55 AGND S - - Transmission predriver ground
56 TXDRV_OUTP A O O Transmission predriver positive output
57 TXDRV_OUTN A O O Transmission predriver negative output
58 AVDD_5V_TXDRV S I I Transmission predriver 5 V supply
60 AGND S - - Transmission DAC ground
61 DAC_OUTP A O O Transmission DAC positive output
62 DAC_OUTN A O O Transmission DAC negative output
64 GPIO10_7 D I/O I General purpose I/O, USART4_SCLK, AT0_BKIN,
65 GPIO10_6 D I/O I General purpose I/O, USART4_TXD, AT0_CH_1,
Table 7. Pin description (continued)
66 GPIO10_5 D I/O I General purpose I/O, USART4_RXD, AT0_CH_2,
67 GPIO10_4 D I/O I General purpose I/O, USART4_CTS, AT0_CH_3,
68 GPIO10_3 D I/O I General purpose I/O, USART4_RTS, AT0_CH_4,
69 GPIO10_2 D I/O I General purpose I/O, AT0_CHN_1, USART3_RTS,
70 GPIO10_1 D I/O I General purpose I/O, AT0_CHN_2, USART3_RXD
71 GPIO10_0 D I/O I General purpose I/O, AT0_CHN_3, USART3_TXD
74 RESETn D I/OD I/OD Reset input, open drain output - active low
75 GPIO09_7 D I/O I General purpose I/O, AT0_ETR, ETM_SWO, SPI4_SCLK
76 GPIO09_6 D I/O I General purpose I/O, USART3_SCLK, ETM_DATA_3,
77 GPIO09_5 D I/O I General purpose I/O, ETM_DATA_2, SPI4_MOSI
78 GPIO09_4 D I/O I General purpose I/O, ETM_DATA_1, SPI4_SSn
79 GPIO09_3 D I/O I General purpose I/O, ETM_DATA_0, USART2_CTS
80 GPIO09_2 D I/O I General purpose I/O, ETM_CLKOUT, USART2_RTS
81 GPIO09_1 D I/O I General purpose I/O, CAN1_RX, USART2_RXD
82 GPIO09_0 D I/O I General purpose I/O, CAN1_TX, USART2_TXD
96 RTC_TAMPB D I/O I Tamper input B, RTC clock output
97 RTC_TAMPA D I I Tamper input A
100 OSC32_OUT A - - 32 kHz oscillator output
101 OSC32_IN A - - 32 kHz oscillator input
102 ADC_VREFN A I I General purpose ADC negative reference voltage input
103 ADC_VREFP A I I General purpose ADC positive reference voltage input
104 GPIO08_5 D I/O I General purpose I/O, ADC_MUX_VIN_5, SPI3_SSn,
105 GPIO08_4 D I/O I General purpose I/O, ADC_MUX_VIN_4, SPI3_SCLK
106 GPIO08_3 D I/O I General purpose I/O, ADC_MUX_VIN_3, USART1_CTS,
107 GPIO08_2 D I/O I General purpose I/O, ADC_MUX_VIN_2, USART1_RTS,
108 GPIO08_1 D I/O I General purpose I/O, ADC_MUX_VIN_1, USART1_RXD,
109 GPIO08_0 D I/O I General purpose I/O, ADC_MUX_VIN_0, USART1_TXD,
110 GPIO07_7 D I/O I General purpose I/O, AT1_CHN_3, SPI1_SCLK
111 GPIO07_6 D I/O I General purpose I/O, AT1_CHN_2, SPI1_MISO
112 GPIO07_5 D I/O I General purpose I/O, AT1_CHN_1, SPI1_MOSI
113 GPIO07_4 D I/O I General purpose I/O, AT1_CH_4, SPI1_SSn
114 GPIO07_3 D I/O I General purpose I/O, AT1_CH_3
115 GPIO07_2 D I/O I General purpose I/O, AT1_CH_2
116 GPIO07_1 D I/O I General purpose I/O, AT1_CH_1, CAN0_RX
117 GPIO07_0 D I/O I General purpose I/O, AT1_BKIN, CAN0_TX
118 GPIO06_7 D I/O I General purpo se I/O, SPI4_SSn, ETM_SWO
119 GPIO06_6 D I/O I General purpose I/O, SPI4_SCLK, ETM_DATA_3
120 GPIO06_5 D I/O I General purpose I/O, SPI4_MISO, ETM_DATA_2
121 GPIO06_4 D I/O I General purpose I/O, SPI4_MOSI, ETM_DATA_1
122 GPIO06_3 D I/O I General purpose I/O, USART3_CTS, I2C1_SCL,
123 GPIO06_2 D I/O I General purpose I/O, USART3_RTS, I2C1_SDA,
124 GPIO06_1 D I/O I General purpose I/O, USART3_RXD, I2C1_SMBA,
125 GPIO06_0 D I/O I General purpose I/O, USART3_TXD, I2C2_SDA
126 GPIO05_7 D I/O I General purpose I/O, USART3_SCLK, I2C2_SMBA
127 GPIO05_6 D I/O I General purpose I/O, USART0_CTS
128 GPIO05_5 D I/O I General purpose I/O, USART0_RTS
129 GPIO05_4 D I/O I General purpose I/O, MCO1
131 GPIO05_3 D I/O I General purpose I/O, FSMC_Ebar_1
132 GPIO05_2 D I/O I General purpose I/O, USART2_SCLK, FSMC_Ebar_0
133 GPIO05_1 D I/O I General purpose I/O, USART2_RXD, SPI2_SSn,
134 GPIO05_0 D I/O I General purpose I/O, USART2_TXD, SPI2_SCLK,
136 GPIO04_7 D I/O I General purpose I/O, USART2_CTS, SPI2_MISO,
137 GPIO04_6 D I/O I General purpose I/O, USART2_RTS, SPI2_MOSI,
138 GPIO04_5 D I/O I General purpose I/O, FSMC_PCDA_2
139 GPIO04_4 D I/O I General purpose I/O, FSMC_PCDA_3
140 GPIO04_3 D I/O I General purpose I/O, FSMC_PCDA_4
141 GPIO04_2 D I/O I General purpose I/O, FSMC_PCDA_5
142 GPIO04_1 D I/O I General purpose I/O, FSMC_PCDA_6
143 GPIO04_0 D I/O I General purpose I/O, FSMC_PCDA_7
144 GPIO03_7 D I/O I General purpose I/O, SPI3_SSn, FSMC_PCDA_8
145 GPIO03_6 D I/O I General purpose I/O, SPI3_SCLK, FSMC_PCDA_9
146 GPIO03_5 D I/O I General purpose I/O, SPI3_MISO, FSMC_PCDA_10
147 GPIO03_4 D I/O I General purpose I/O, SPI3_MOSI, FSMC_PCDA_11,
148 GPIO03_3 D I/O I General purpose I/O, SPI2_SSn, USART3_CTS,
149 GPIO03_2 D I/O I General purpose I/O, SPI2_SCLK, USART3_RTS,
150 GPIO03_1 D I/O I General purpose I/O, SPI2_MISO, USART3_RXD,
151 GPIO03_0 D I/O I General purpose I/O, SPI2_MOSI, USART3_TXD,
155 RESERVED - - - Reserved - connect to DGND
156 GPIO02_7 D I/O I General purpose I/O, AT0_BKIN, FSMC_Lbar,
157 GPIO02_6 D I/O I General purpose I/O, AT0_CH_1, FSMC_PCWEn,
158 GPIO02_5 D I/O I General purpose I/O, AT0_CHN_1, FSMC_PCOEn,
159 GPIO02_4 D I/O I General purpose I/O, AT0_CH_2, FSMC_PCAD_0,
160 GPIO02_3 D I/O I General purpose I/O, AT0_CHN_2, FSMC_PCAD_1,
161 GPIO02_2 D I/O I General purpose I/O, AT0_CH_3, FSMC_PCAD_2
162 GPIO02_1 D I/O I General purpose I/O, AT0_CHN_3, I2C2_SCL,
163 GPIO02_0 D I/O I General purpose I/O, AT0_CH_4, I2C2_SDA,
164 GPIO01_7 D I/O I General purpose I/O, AT0_ETR, I2C2_SMBA,
165 GPIO01_6 D I/O I General purpose I/O, I2C1_SCL, CAN1_RX,
166 GPIO01_5 D I/O I General purpose I/O, I2C1_SDA, CAN1_TX,
167 GPIO01_4 D I/O I General purpose I/O, USART1_CTS, CAN0_RX,
168 GPIO01_3 D I/O I General purpose I/O, USART1_RTS, CAN0_TX,
169 GPIO01_2 D I/O I General purpose I/O, USART1_RXD, AT1_ETR,
170 GPIO01_1 D I/O I General purpose I/O, USART1_TXD, AT1_CHN_3,
171 GPIO01_0 D I/O I General purpose I/O, I2C0_SMBA, AT1_CHN_2,
172 GPIO00_7 D I/O I General purpose I/O, I2C0_SCL, AT1_CHN_1,
173 GPIO00_6 D I/O I General purpose I/O, I2C0_SDA, AT1_CH_4,
174 GPIO00_5 D I/O I General purpose I/O, SPI1_SCLK, AT1_CH_3,
176 GPIO00_4 D I/O I General purpose I/O, SPI1_MISO, AT1_CH_2,
177 EXPAD S - - Exposed pad - DGND
- Type: D = digital; A = analog; S = supply/ground.
- Direction: I = input; O = output; I/O = input/output, OD = open drain.
- Reset status: I = input, I/O = input/output, O = output.
2.2 GPIOs multiplexing scheme
functions for each pin as described in Table 8. Table 8. GPIOs multiplexing scheme
Table 8. GPIOs multiplexing scheme (continued)
3 Memory map
Figure 8. Memory map
4 Electrical characteristics
4.1 Absolute maximum ratings
Table 9. Absolute maximum ratings - voltage
4.2 Thermal characteristics
Table 9. Absolute maximum ratings - voltage (continued) Table 10. Absolute maximum ratings - current Table 11. Thermal characteristics
4.3 Operating conditions
T(AMB) = -40 to +85 °C, T(J) < 125 °C, PVCC = 18 V unless otherwise specified. All typical values are referred to T(AMB) = 25 °C. Table 12. Analog supply characteristics
5 V PLC AFE supply
3.3 V PLC AFE supply
- Based on characterization, not tested in production.
- I(5 V) = I(AVDD_5V_AFE) + I(AVDD_5V_PGA) + I(AVDD_5V_TXDRV).
Table 12. Analog supply characteristics (continued) Table 13. Digital supply characteristics - RTE
- Based on characterization, not tested in production.
- The tests are performed with the following enabled digital blocks: 2 x GPT, 2 x SPI, 2 x USART, IPC, DMA, 2 x I2C, AES,
the difference in the supply current with and without RTE enabled and running.
Table 14. Digital supply characteristics - Cortex™-M4 fetching from RAM
- All the tests are performed with the following enabled digita l blocks: 2 x GPT, 2 x SPI, 2 x USART, IPC, DMA, 2 x I2C, AES,
Table 15. Digital supply characteristics - Cortex™-M4 fetching data from eFlash
- All the tests are performed with the following enabled digita l blocks: 2 x GPT, 2 x SPI, 2 x USART, IPC, DMA, 2 x I2C, AES,
Table 16. Digital supply characteristics - DOZE (sleep)/deepsleep mode
- The test is performed with the foll owing enabled digital blocks: 2 x GPT, 2 x SPI, 2 x USART, IPC, DMA, 2 x I2C, AES,
Table 17. Supply characteristics - QFS
- The test is performed with the following enabled digita l blocks: 2 x GPT, 2 x SPI, 2 x USART, IPC, DMA, 2 x I2C, AES,
TRNG. The value is calculated by measuring the difference in the supply current with and without QFS enabled and running. Table 18. 24 MHz oscillator
- Guaranteed by design, not tested in production.
Table 19. 32 kHz oscillator
- Guaranteed by design, not tested in production.
Table 20. Digital supply characteristics - I/O
- The tests are performed with the following enabled digital blocks: 2 x GPT, 2 x SPI, 2 x USART, IPC, DMA, 2 x I2C, AES,
the difference in the supply current with and without 8 GPIOs enabled and toggling at the given frequency.
Table 21. I/O characteristics
- Guaranteed by design, not tested in production.
Table 22. Digital supply characteristics - power consumption under battery
4.4 PLC analog front-end (AFE) and line driver characteristics
4.4.1 Line driver characteristics
Table 23. Line driver characteristics
50 Hz -100 dB
- Not tested in production, guaranteed by design.
4.4.2 Line driver test circuit
Figure 9. Line driver test circuit
4.4.3 AFE characteristics
Table 24. DAC characteristics
Table 25. Predriver characteristics
- DAC + predriver chain distortion.
Table 26. Receiver input referred noise Table 27. PLC PGA characteristics
Table 28. ADC characteristics Table 29. Zero crossing characteristics
10 V p-p
4.5 Embedded Flash characteristics
Table 30. Flash memory characteristics
- Based on characterization, not tested in production.
- Assuming nominal supply values and operation at 25 °C, 0 cycles.
- Assuming nominal supply values and operation at 25 °C, 100 cycles.
- Assuming nominal supply values and operation at 125 °C, 100 Kcycles.
Table 31. Flash memory endurance and data retention
- Based on characterization, not tested in production.
- Cycling performed over the whole temperature range.
Table 32. Flash memory current consumption
- During characterization, not tested in production. Th e values exclude the consumption from other pins.
5 Package information
specifications, grade definitions and product status are available at: www.st.com.
5.1 TQFP176 package information
Figure 10. TQFP176 (20 x 20 x 1 mm) package outline
5.2 Thermal data
Table 33. TQFP176 (20 x 20 x 1 mm) package mechanical data Table 34. Thermal data Symbol Parameter Conditions Typ.
6 Ordering information
7 Revision history
Table 35. Ordering information Table 36. Document revision history 15-Oct-2015 1 Initial release.