STCH02 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 24
Technical content
Datasheet sections
- 1 Device description and block diagram
- 2 Typical circuit
- 3 Application information
- 3.1 Gate driver
- 3.2 Frequency jittering for EMI reduction
- 3.3 High voltage start-up generator
- 3.4 Zero current detection and triggering block
- 3.5 Constant voltage operation
- 3.6 Constant current operation
- 3.7 Voltage feedforward block
- 3.8 Burst mode operation
- 3.9 Adaptive UVLO
- 3.10 Overvoltage protection
- 3.11 Soft-start and starter block
- 3.12 Hiccup mode OCP
- 4 Package information
- 4.1 SO-8 package information
- 5 Revision history
Features
Advanced power management for ultra-low standby power consumptions (under 10 mW at
230 Vac)
Fully integrated primary side constant current output regulation (CC) 650 V embedded HV start-up circuit with zero power consumption. Quasi resonant (QR) zero voltage switching (ZVS) operation Automatic self-supply Accurate and adjustable output OVP with autorestart after fault Input voltage feedforward compensation for mains-independent CC regulation Intelligent frequency jitter for EMI suppression SO-8 package
Applications
AC-DC chargers for smartphones, tablets, camcorders and other handheld equipment AC/DC adapters for STB, notebooks and auxiliary power supplies
Description
The STCH02 is a PWM quasi resonant controller specifically designed for ultra-low standby power supplies. The built-in HV startup cell with zero power consumption, the fully integrated blocks for primary side constant current output regulation and the advanced power management make this IC the best choice to build a high efficiency and ultra-low standby consumption power supply, with high overall and excellent dynamic performances. Figure 1. Typical application Table 1. Device summary
STCH02 Device description and block diagram
1 Device description and block diagram
The STCH02 is a current mode controller designed for offline quasi resonant ZVS (zero voltage switching at switch turn-on) flyback converters. It combines a high performance low voltage PWM controller chip and a 650 V HV start-up cell in the same package. The device features a unique characteristic: it is capable to provide a constant output current (CC) regulation using primary-sensing feedback. This eliminates the need for a dedicated current reference IC, as well as the current sensor, still maintaining a quite accurate output current regulation. The quasi resonant operation is achieved by means of a transformer demagnetization sensing input that triggers MOSFET's turn-on, connected on the ZCD pin. This input serves also to monitor the output voltage monitor and to achieve the mains independent CC regulation (line voltage feedforward). The maximum switching frequency is top-limited below 260 kHz, so that at the medium- light-load a special function automatically lowers the operating frequency still maintaining the operation as close to ZVS as possible. At the very light-load, the device enters a controlled burst mode operation that, along with the zero power high voltage start-up circuit, the extremely low quiescent current of the device, helps minimize the residual input consumption, thus meeting the requirements of the most stringent standards. During the CC regulation, where the flyback voltage generated by the auxiliary winding drops and may be not enough to supply the internal circuits, the chip is able to power itself directly from the rectified mains through the high voltage start-up circuit. During the burst mode operation the self-supply feature is disabled (due to very stringent no load consumption requirement), and the V DD supply voltage has to be guaranteed by proper application design. In any case, an innovative adaptive UVLO helps minimize the issues related to the fluctuations of the self-supply voltage with the output load, due to transformer's parasitic and further reducing the IC's bias consumption. In addition to the said functions that optimize power handling under different operating conditions, the device offers also a protection against the transformer saturation and secondary diode short-circuit and an adjustable output overvoltage protection. All of them are in the autorestart mode. An embedded leading edge blanking on the current sense input for greater noise immunity completes the equipment of this device.
Figure 2. Block diagram
Figure 3. Pin connection (top view) Table 2. Thermal data Table 3. Absolute maximum ratings Table 4. Pin functions
are approaching the cycle-by-cycle overcurrent setpoint. input/output voltage monitor. A negative-going edge triggers the MOSFET's turn-on. capacitor is allowed between the pin and the auxiliary winding of the transformer.
5 SENSE
the trace going to this pin and kept separate from any pulsed current return. 7 GD A gate driver with a totem pole output stage for the external power MOSFET. Table 4. Pin functions (continued)
Table 5. Electrical characteristics
2 Typical circuit
Figure 4. Typical configuration
3 Application information
quasi resonant ZVS (zero voltage switching at switch turn-on) flyback converters.
- QR mode at the heavy load. Quasi resonan t operation lies in synchronizing MOSFET's
different line/load conditions (see the hyperbolic-like portion of the curves in Figure 5). the main benefits of this kind of operation.
- Valley-skipping mode at the medium/light-l oad. Depending on voltage on the FB pin,
- Burst mode with no or a very light-load. When the load is extremely light or
the peak current very low, no issue of audible noise arises. Figure 5. Multi-mode operation of STCH02
3.1 Gate driver
The gate driver of the power MOSFET is designed to supply a controlled gate current during both turn-on and turn-off in order to minimize the common mode EMI. Under UVLO conditions an internal pull-down circuit holds the gate low in order to ensure that the power MOSFET cannot be turned on accidentally.
3.2 Frequency jitterin g for EMI reduction
Although the STCH02 device works in the QR mode and the switching frequency is already modulated at twice of the mains frequency, dedicated frequency jittering circuitry is embedded inside the IC to further reduce the EMI filtering. A proprietary frequency jitter technique is implemented in the controller, based on the injection of a modulating signal at 9 kHz (above the feedback loop bandwidth) with 50% duty cycle on the current sense signal: this signal is a square waveform that modulates the amplitude of the peak primary current. The percentage of this amplitude is set as a default at 5%. As the peak current reduces with decreasing load levels, the effect of this modulation automatically attenuates at lower loads, where the energy of EMI noise is highly reduced.
3.3 High voltage start-up generator
Based on a 650 V rated depletion MOSFET embedded into the startup cell, the HV current generator is supplied through the DRAIN pin and is enabled only if the voltage on the HV pin is higher than the HVSTART threshold (50 V typical value). With reference to the timing diagram in Figure 6, when the power is applied to the circuit and the voltage on the input bulk capacitor is high enough, the HV generator is sufficiently biased to start operating, thus it will draw the current I CHARGE (7 mA typ. value) through the HV pin and will charge the capacitor connected between the VDD pin and ground. This charging current will be reduced at 0.6 mA in case the voltage on the VDD is lower than VDD-FOLD, in order to prevent exceeding IC dissipation when the pin is accidentally shorted to ground or during a restart after protection triggering. As the VDD voltage reaches the start-up threshold (13 V typ.) the chip starts operating and the control logic disables the HV generator. While the generator is off, there are virtually no losses across the HV startup cell, except a few hundreds nA of the leakage current through the depletion MOSFET. The IC is powered by the energy stored in the VDD capacitor until the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation. The chip is able to power itself directly from the rectified mains: when the voltage on the VDD pin falls below VDD-OFF (10 V typ.), the HV current generator is turned on and charges the supply capacitor until it reaches the VDD-ON threshold. In this way, the self-supply circuit develops a voltage high enough to sustain the operation of the device. This feature is useful especially during the CC regulation, when the flyback voltage generated by the auxiliary winding alone may not be able to keep V DD within the operative range.
output voltage decay at system power-down. Figure 6. Timing diagram: normal power-up and power-down sequences
3.4 Zero current detection and triggering block
block must be previously armed by a positive-going edge exceeding 100 mV. VFB = 0.6 V, and decreases linearly down to TBLANK = 3.8 µs for VFB 1.65 V. protection on page 18 and Section 3.7: Voltage feedforward block on page 16.
the ZCD pin and the auxiliary winding of the transformer. frequency tends to increase excessively at the light-load and high input voltage. locked to transformer demagnetization, hence setting up the QR operation. high enough to allow the ZCD triggering. will be prevented from exceeding 1/TBLANK. Figure 7. Drain ringing cycle skipping as the load is progressively reduced the converter or on its output voltage.
3.5 Constant voltage operation
the converter. Typically, a TS431 is used as a voltage reference. The FB pin is driven directly by the phototransistor's collector to modulate the duty cycle. controlling the peak drain current cycle-by-cycle. Figure 8. Voltage control principle: internal schematic
3.6 Constant current operation
achieve an output constant current regulation. Equation 1 can be used to define to output current in CC mode. current loop gain KI is internally defined (see Table 5 on page 7).
3.7 Voltage feedforward block
Td, which will switch off the MOSFET with a peak current than higher the foreseen value. the cycle-by-cycle current limitation. The external schematic configuration is shown in Figure 9. Figure 9. Feedforward compensation: internal schematic where RFF is an internal parameter, defined in Table 5 on page 7. In this case the peak drain current does not depend on input voltage anymore.
3.8 Burst mode operation
FBB and the device restarts the switch again. is audible noise free since the peak current is low. Figure 10. Adaptive minimum restart time: timing diagrams
3.9 Adaptive UVLO
A major problem when optimizing a converter for minimum no load consumption is that the voltage generated by the auxiliary winding under these conditions falls considerably as compared even to a few mA load. This very often causes the supply voltage VDD of the control IC to drop and, as the self-supply is disabled during the burst mode, it can go below the UVLO threshold so that the operation becomes intermittent, which is undesired. Furthermore, this must be traded off against the need of generating a voltage not exceeding the maximum allowed by the control IC at the full load but low enough to reduce the bias losses as much as possible. To help the designer to overcome this problem, the device besides reducing its own consumption during the burst mode operation, also features a proprietary adaptive UVLO function. It consists of shifting the V DD-UVLO threshold downwards at the light-load, namely when the voltage at the FB pin falls 65 mV below the burst mode threshold VFBB (0.6 V typ.), to have more headroom. To prevent any malfunction the normal threshold (9.5 V typ.) is re-established when the voltage at the FB pin exceeds the exit burst mode threshold VFBF. The normal UVLO threshold ensures that at full medium-heavy loads the MOSFET will be driven with a proper gate to source voltage. The mode of operation is reported in Figure 10.
3.10 Overvoltage protection
The overvoltage function of the STCH02 device monitors the voltage on the ZCD pin during MOSFET's OFF-time, where the voltage generated by the auxiliary winding tracks converter's output voltage. If the voltage applied to the pin exceeds an internal 2.5 V reference, a comparator is triggered, an overvoltage condition is assumed and the device is shut down. Once R ZCD is fixed by feedforward considerations (see Section 3.7: Voltage feedforward block) it is possible to calculate the value of the ROVP resistor to activate the OVP protection for a certain output voltage level, VOUT-OVP: Equation 3 Where VOVP is the internal OVP threshold, NSEC and NAUX are the secondary and auxiliary turn's number respectively. To reduce sensitivity to noise and prevent the latch from being erroneously activated, the OVP comparator must be triggered for four consecutive oscillator cycles before the STCH02 device is stopped. A counter, which is reset every time the OVP comparator is not triggered in one oscillator cycle, is provided to this purpose. Figure 11 illustrates the timing of the function.
a low frequency intermittent operation (hiccup mode operation). Figure 11. OVP function: timing diagram
3.11 Soft-start and starter block
primary peak current will be limited from the voltage on the internal CC block capacitor. slowly and the soft-start feature will be ensured.
3.12 Hiccup mode OCP
exceeds the VOCP value (1 V typ. value). tripped again a real malfunction is assumed and the device will be stopped.
illustrated in the timing diagram of Figure 12. Figure 12. Hiccup mode OCP: timing diagram
4 Package information
specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
4.1 SO-8 package information
Figure 13. SO-8 package outline
Table 6. SO-8 package mechanical data
- Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm (0.006 inch) in total (both sides).
5 Revision history
Table 7. Document revision history 15-Dec-2015 1 Initial release.