STC62WV1M8 ETC1 | Alldatasheet
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Revision 2.1 Jan. 2004 R0201-STC62WV1M8 Very Low Power/Voltage CMOS SRAM 1M X 8 bit
- Wide Vcc operation voltage : 2.4V ~ 5.5V
- Very low power consumption : Vcc = 3.0V C-grade: 30mA (@55ns) operating current I -grade: 31mA (@55ns) operating current C-grade: 24mA (@70ns) operating current I -grade: 25mA (@70ns) operating current 1.5uA (Typ.) CMOS standby current Vcc = 5.0V C-grade: 75mA (@55ns) operating current I -grade: 76mA (@55ns) operating current C-grade: 60mA (@70ns) operating current I -grade: 61mA (@70ns) operating current 8.0uA (Typ.) CMOS standby current
- High speed access time : -55 55ns -70 70ns
- Automatic power down when chip is deselected The STC62WV1M8 is a high performance , very low power CMOS Static Random Access Memory organized as 1,048,576 words by 8 bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 1.5uA at 3V/25oC and maximum access time of 55ns at 3.0V/85oC. Easy memory expansion is provided by an active LOW chip enable(CE1) , an active HIGH chip enable (CE2) and active LOW output enable (OE) and three-state output drivers. The STC62WV1M8 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The STC62WV1M8 is available in 48B BGA and 44L TSOP2 packages. GENERAL DESCRIPTION FEATURES FUNCTIONAL BLOCK DIAGRAM PRODUCT FAMILY PIN CONFIGURATIONS STC International Limited. reserves the right to modify document contents without notice. Address Input Buffer Row Decoder Memory Array
2048 X 4096
A11A9 A8 A3 A2 A1 A0A10 A19 STC62WV1M8 POWER DISSIPATION SPEED ( ns ) STANDBY ( ICCSB1, Max ) Operating ( ICC, Max ) PRODUCT FAMILY OPERATING TEMPERATURE Vcc RANGE Vcc=3V Vcc=5V Vcc=3V Vcc=5V PKG TYPE STC62WV1M8EC TSOP2-44 STC62WV1M8FC +0 O C to +70O C 2.4V ~ 5.5V 5uA 55uA 24mA 60mA BGA-48-0912 STC62WV1M8EI TSOP2-44 STC62WV1M8FI -40 O C to +85O C 2.4V ~ 5.5V 10uA 110uA 25mA 61mA BGA-48-0912 CE1 NC NC DQ0 DQ1 VCC GND DQ2 DQ3 NC NC WE A19 A18 A17 A16 A15 OE CE2 NC NC DQ7 DQ6 GND VCC DQ5 DQ4 NC NC A10 A11 A12 A13 A14 STC62WV1M8EC STC62WV1M8EI CE1 STC
- Three state outputs and TTL compatible
- Fully static operation
- Data retention supply voltage as low as 1.5V
- Easy expansion with CE1, CE2 and OE options 70ns 70ns 55ns : 3.0~5.5V 70ns : 2.7~5.5V G H F E D C B A A11 A10 A18 A19 A12 A14 A13 A15 WE NC NC NC NC NC VSS A17 A16 VCC VSS VCC VCC OE CE2 NC NC NC NC NC CE1 NC 48-ball BGA top view
Revision 2.1 Jan. 2004 R0201-STC62WV1M8 Name Function A0-A19 Address Input These 20 address inputs select one of the 1,048,576 x 8-bit words in the RAM CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. DQ0-DQ7 Data Input/Output Ports These 8 bi-directional ports are used to read data from or write data into the RAM. Vcc Power Supply Gnd Ground TRUTH TABLE PIN DESCRIPTIONS STC CIN Input Capacitance VIN=0V pF CDQ Input/Output Capacitance VI/O=0V pF ABSOLUTE MAXIMUM RATINGS(1) OPERATING RANGE CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz) 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. This parameter is guaranteed and not 100% tested. SYMBOL PARAMETER RATING UNITS V TERM Terminal Voltage with Respect to GND -0.5 to Vcc+0.5 V T BIAS Temperature Under Bias -40 to +85 O C T STG Storage Temperature -60 to +150 O C P T Power Dissipation 1.0 W I OUT DC Output Current mA STC62WV1M8 RANGE AMBIENT TEMPERATURE Vcc Commercial
0 O C to +70 O C
2.4V ~ 5.5V Industrial -40 O C to +85 O C 2.4V ~ 5.5V MODE WE CE1 CE2 OE I/O OPERATION Vcc CURRENT X H X X Not selected (Power Down) X X L X High Z ICCSB, ICCSB1 Output Disabled H L H H High Z ICC Read H L H L DOUT ICC Write L L H X DIN ICC SYMBOL PARAMETER CONDITIONS MAX. UNIT
Revision 2.1 Jan. 2004 R0201-STC62WV1M8 1. Typical characteristics are at TA = 25oC. 2. Fmax = 1/tRC . 3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC ) 1. Vcc = 1.5V, TA = + 25OC 2. tRC = Read Cycle Time 3. IccDR(Max.) is 1.3uA at TA=70OC. DC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) STC LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled ) CE1 Data Retention Mode Vcc t CDR Vcc t R VIH VIH Vcc VDR 1.5V CE1 Vcc - 0.2V STC62WV1M8 SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS VDR Vcc for Data Retention CE1≧ Vcc - 0.2V or CE2 ≦ 0.2V, VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V 1.5 V ICCDR (3) Data Retention Current CE1≧ Vcc - 0.2V or CE2 ≦ 0.2V, VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V 0.8 2.5 uA tCDR Chip Deselect to Data Retention Time ns tR Operation Recovery Time See Retention Waveform TRC (2) ns PARAMETER NAME PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS Vcc=3V -0.5 0.8 VIL Guaranteed Input Low Voltage(3) Vcc=5V -0.5 0.8 V Vcc=3V 2.0 Vcc+0.3 VIH Guaranteed Input High Voltage(3) Vcc=5V 2.2 Vcc+0.3 V IIL Input Leakage Current Vcc = Max, VIN = 0V to Vcc uA ILO Output Leakage Current Vcc = Max, CE1 = VIH or CE2 = VIL or OE = VIH, VI/O = 0V to Vcc uA Vcc=3V VOL Output Low Voltage Vcc = Max, IOL = 2mA Vcc=5V 0.4 V Vcc=3V VOH Output High Voltage Vcc = Min, IOH = -1mA Vcc=5V 2.4 V 70ns Vcc=3V ICC(4) Operating Power Supply Current CE1= VIL, CE2= VIH, IDQ = 0mA, F = Fmax(2) 70ns Vcc=5V mA Vcc=3V ICCSB Standby Current-TTL CE1 = VIH or CE2= VIL, IDQ = 0mA Vcc=5V mA Vcc=3V 1.5 ICCSB1(5) Standby Current-CMOS CE1≧Vcc-0.2V or CE2≦0.2V VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V Vcc=5V 8.0 110 uA LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled ) CE2 Data Retention Mode Vcc t CDR Vcc t R VIL VIL Vcc VDR ≧1.5V CE2 ≦0.2V
Revision 2.1 Jan. 2004 JEDEC PARAMETER NAME NAME
DESCRIPTION
CYCLE TIME : 70ns UNIT tAVAX tRC Read Cycle Time ns tAVQV tAA Address Access Time ns tE1LQV tACS1 Chip Select Access Time (CE1) ns tE2LQV tACS2 Chip Select Access Time (CE2) ns tGLQV tOE Output Enable to Output Valid ns tELQX tCLZ Chip Select to Output Low Z ns tGLQX tOLZ Output Enable to Output in Low Z ns tEHQZ tCHZ Chip Deselect to Output in High Z ns tGHQZ tOHZ Output Disable to Output in High Z ns tAXOX tOH Data Hold from Address Change ns R0201-STC62WV1M8 AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) READ CYCLE AC TEST CONDITIONS (Test Load and Input/Output Reference) KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS MUST BE STEADY MAY CHANGE FROM H TO L DON T CARE: ANY CHANGE PERMITTED DOES NOT APPLY MUST BE STEADY WILL BE CHANGE FROM H TO L CHANGE : STATE UNKNOWN CENTER LINE IS HIGH IMPEDANCE ”OFF ”STATE MAY CHANGE FROM L TO H WILL BE CHANGE FROM L TO H STC STC62WV1M8 PARAMETER Input Pulse Levels Vcc / 0V Input Rise and Fall Times 1V/ns Input and Output Timing Reference Level 0.5Vcc Output Load CL = 30pF+1TTL CL = 100pF+1TTL MIN. TYP. MAX. Vcc=2.7~5.5V MIN. TYP. MAX. Vcc=3.0~5.5V CYCLE TIME : 55ns
Revision 2.1 Jan. 2004 R0201-STC62WV1M8 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC t OH t AA D OUT ADDRESS t OH NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2 = VIH. 3. Address valid prior to or coincident with CE1 transition low and CE2 transition high. 4. OE = VIL . 5. The parameter is guaranteed but not 100% tested. STC STC62WV1M8 READ CYCLE2 (1,3,4) t CLZ t CHZ (5) D OUT CE1 (5) t ACS1 CE2 t ACS2 READ CYCLE3 (1,4) t OH t RC t OE D OUT CE1 OE ADDRESS t CLZ (5)t ACS1 t CHZ (1,5) t OHZ (5) t OLZ t AA CE2 t ACS2
Revision 2.1 Jan. 2004 R0201-STC62WV1M8 AC ELECTRICAL CHARACTERISTICS ( TA = -40oC to + 85oC ) WRITE CYCLE SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) STC STC62WV1M8 JEDEC PARAMETER NAME PARAMETER NAME CYCLE TIME : 70ns UNIT tAVAX tWC Write Cycle Time ns t E1LWH tCW Chip Select to End of Write ns tAVWL tAS Address Set up Time ns tAVWH tAW Address Valid to End of Write ns tWLWH tWP Write Pulse Width ns tWHAX tWR Write Recovery Time (CE2,CE1 , WE) ns tWLOZ tWHZ Write to Output in High Z ns tDVWH tDW Data to Write Time Overlap ns tWHDX tDH Data Hold from Write Time ns tGHOZ tOHZ Output Disable to Output in High Z ns tWHQX tOW End of Write to Output Active ns t WR t WC (3) t CW (11) (2) t WP t AW t OHZ (4,10) t AS (3) t DH t DW D IN D OUT WE CE1 OE ADDRESS (5) CE2 (5) MIN. TYP. MAX. MIN. TYP. MAX. (Vcc=2.7~5.5V) (Vcc=3.0~5.5V) CYCLE TIME : 55ns
Revision 2.1 Jan. 2004 R0201-STC62WV1M8 WRITE CYCLE2 (1,6) STC STC62WV1M8 NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write. t WC t CW (11) (2) t WP t AW t WHZ (4,10) t AS t WR (3) t DH t DW D IN D OUT WE CE1 ADDRESS t OW (7) (8) (8,9) CE2 (5)
Revision 2.1 Jan. 2004 ORDERING INFORMATION STC PACKAGE DIMENSIONS STC62WV1M8 R0201-STC62WV1M8 TSOP2-44 Note: STC (STC International Limited.) assumes no responsibility for the application or use of any product or circuit described herein. STC does not authorize its products for use as critical components in any application in which the failure of the STC product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. STC62WV1M8 X X Z Y Y GRADE C: +0oC ~ +70oC I: -40oC ~ +85oC SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free PACKAGE E: TSOP2-44 F: BGA-48-0912
Revision 2.1 Jan. 2004 STC62WV1M8 STC R0201-STC62WV1M8 E 0.1 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. N E D NOTES: 12.0 9.0 e 3.75 5.25 0.75 SIDE VIEW D 0.1 1.4 Max. e 0.25±0.05 SOLDER BALL 0.35±0.05 VIEW A 3.375 2.625 PACKAGE DIMENSIONS (continued) 48 mini-BGA (9mm x 12mm)