STC3117 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 34
Technical content
Datasheet sections
- 1 Block diagram
- 2 Pin assignment
- 3 Absolute maximum ratings and operating conditions
- 4 Electrical characteristics
- 5 Application information
- 6 Functional description
- 6.1 Battery monitoring functions
- 6.1.1 Operating modes
- 6.1.2 Battery voltage monitoring
- 6.1.3 Internal temperature monitoring
- 6.1.4 Current sensing in mixed mode
- 6.1.5 SOC change rate in voltage mode
- 6.2 STC3117 gas gauge architecture
- 6.2.1 Coulomb counter
- 6.2.2 Voltage gas gauge algorithm
- 6.2.3 Mixed mode gas gauge system
- 6.3 Alarm output
- 6.4 Current monitoring
- 6.5 Power-up and battery swap detection
- 7.1 Read and write operations
- 7.2 Register map and description
- 7.2.1 Register map
- 7.2.2 Register description
- 7.2.3 REG_MODE and REG_CTRL register description
- 7.2.4 OCV table register description
- 8 Package information
Features
- Patented OptimGauge™ algorithm for accurate battery capacity calculation
- Robust initial open-circuit-voltage (OCV) measurement at power up
- Programmable low battery alarm
- Missing/swapped battery detection
- Average current internal calculation
- End-of-charge detection
- Internal temperature sensor
- Battery swap detection with protection against false battery insertion
- Low power: 40 µA in voltage-only mode, 2 µA max in standby mode
- 1.49 x 1.594 mm 9-bump CSP package
Applications
- Mobile phones, multimedia players, digital cameras
- Portable medical equipment
Description
The STC3117 includes the STMicroelectronics OptimGauge™ algorithm. It provides accurate battery state-of-charge (SOC) monitoring, tracks battery parameter changes with operation conditions, temperature, and aging, and allows the application to get a battery state-of-health (SOH) indication. An alarm output signals low SOC or low voltage conditions and also indicates fault conditions like a missing or swapped battery.CSP (1.49 x 1.594 mm)
8.1 Flip Chip CSP 1.49 x 1.594 x 0.4 mm (N5) with coating ball printing
1 Block diagram
Figure 1. STC3117 internal block diagram
2 Pin assignment
Figure 2. STC3117 pin connections (top view) Table 1. STC3117 pin description
- I = input, 0 = output, OD = open drain, A = analog, D = digital, NC = not connected
3 Absolute maximum ratings and operating conditions
Table 2. Absolute maximum ratings
- Tested in compliance with MIL-883-H, AEC-Q100-002D and JEDEC JESD22-A114F
- Tested in compliance with MIL-883-H, AEC-Q100-003E and JEDEC JESD22-A115A
Table 3. Operating conditions
4 Electrical characteristics
Table 4. Electrical characteristics (2.7 V < VCC < 4.5 V, -20 ° C to 70 ° C)
Table 4. Electrical characteristics (2.7 V < VCC < 4.5 V, -20 ° C to 70 ° C) (continued)
Figure 3. I2C timing diagram Table 5. I2C timing - VIO = 2.8 V, Tamb = -20 °C to 70 ° C (unless otherwise specified)
5 Application information
Figure 4. Example of an application schematic Table 6. External component list
6 Functional description
6.1 Battery monitoring functions
6.1.1 Operating modes
Table 7. Mode selection is made by the VMODE bit in register 0 (refer to Table 12 for highest accuracy from the gas gauge. temperature conversion every 16 s. This mode provides the lowest power consumption.
6.1.2 Battery voltage monitoring
Battery voltage is measured by using one conversion cycle of the A/D converter every 4 s. conversion cycle time is 250 ms. from the battery open-circuit voltage. The result is stored in the REG_VOLTAGE register (see Table 11). Table 7. STC3117 operating modes
0 Mixed mode, Coulomb counter is active , voltage gas gauge runs in parallel
1 Voltage gas gauge with power saving
Coulomb counter is not used. No current sensing.
Functional description STC3117
6.1.3 Internal temperature monitoring
The chip temperature (close to the battery temperature) is measured using one conversion cycle of the A/D converter every 16 s. The conversion cycle takes 213 = 8192 clock cycles. Using the 32768 Hz internal clock, the conversion cycle time is 250 ms. Resolution is 1° C and range is -40 to +125 °C. The result is stored in the REG_TEMPERATURE register (see Table 11).
6.1.4 Current sensing in mixed mode
Current sensing is available only in mixed mode (VMODE=0). The voltage drop across the sense resistor is integrated during a conversion period and is input to the 14-bit sigma-delta A/D converter. Using the 32768 Hz internal clock, the conversion cycle time is 500 ms for a 14-bit resolution. The LSB value is 5.88 µV. The A/D converter output is in two’s complement format. When a conversion cycle is completed, the result is added to the Coulomb counter accumulator and the number of conversions is incremented in a 16-bit counter. The current register is updated after each conversion (that is: once per 500-ms measurement cycle). The result is stored in the REG_CURRENT register (see Table 11). Average current register In mixed mode, an average value of the current measurement is calculated after each current measurement with a time constant of 2 s. The register REG_AVG_CURRENT (2 bytes) holds the average current when VMODE=0. The LSB of REG_AVG_CURRENT is 1/4 the LSB of REG_CURRENT, that is 1.47 µV.
6.1.5 SOC change rate in voltage mode
Current sensing is not available in voltage mode (VMODE=1). Instead, an estimation of the SOC change rate is provided in the REG_AVG_CURRENT register. The SOC change rate is updated after each SOC calculation (that is: once per 4-s measurement cycle) and is averaged with a time constant of 64 seconds. It is possible to write an initial estimation into the REG_AVG_CURRENT register to speed-up the SOC change rate settling time. The REG_AVG_CURRENT register (2 bytes) holds the SOC change rate when VMODE=1. The LSB of REG_AVG_CURRENT is 0.008789 C (by definition, 1 C means 100% SOC change in 1 h).
6.2 STC3117 gas gauge architecture
6.2.1 Coulomb counter
counting) for the calculation of the relative SOC value based on the configuration register. through the I2C control registers. Figure 5. Coulomb counter block diagram on-reset (POR) or reset (VMODE bit = 1). gas gauge algorithm to restart from this new SOC value. Rsense is in mΩ and Cnom is in mAh.
6.2.2 Voltage gas gauge algorithm
nature of the Li-Ion and Li-Po batteries. results for most battery chemistries used in hand-held applications. Figure 6. Voltage gas gauge block diagram 160 mΩ internal battery impedance and 1957 mAh Cnom battery capacity). type; the default power-up values can be updated at software initialization. Ri is in mΩ and Cnom is in mAh.
6.2.3 Mixed mode gas gauge system
commonly found in CC-only solutions. without jumps in any application conditions. GG_VM=1 means the reported SOC is the VM SOC, otherwise the SOC is the CC SOC. stays active, the CC is stopped, and the power consumption is reduced. Figure 7. Mixed mode gas gauge block diagram
- REG_CC_ADJ = REG_SOC – (unadjusted CC SOC)
- REG_VM_ADJ = REG_SOC – (unadjusted VM SOC) These registers can be used by the system application to implement more sophisticated algorithms for improved performance and accuracy. Writing to the REG_SOC or REG_OCV initializes the two VM and CC algorithms to the corresponding SOC value and clears REG_VM_ADJ and REG_CC_ADJ. It is possible to write to the REG_SOC, REG_OCV, REG_VM_CNF and REG_CC_CNF registers when the STC3117 is running without disturbing SOC management. Note: When writing to the REG_SOC or REG_OCV re gisters, the resulting SOC value is rounded to the nearest 1/64 % value (the least three bits of REG_SOC are zero). Voltage mode (VM) REG_SOC register Alarm management Parameter tracking Coulomb counter REG_VM_ADJ register REG_CC_ADJ register (CC) SOC management gas gauge
Functional description STC3117
6.3 Alarm output
The ALM pin provides an alarm signal in case of low battery or fault condition. The output is an open drain, and an external pull-up resistor is needed in the application. Writing the IO0DATA bit to 0 forces the ALM output low; writing the IO0DATA bit to 1 lets the ALM output reflect the battery condition. Reading the IO0DATA bit gives the state of the ALM pin. When the IO0DATA bit is 1, the ALM pin is driven low if any of the following conditions are met:
- the battery SOC estimation from the mixed algorithm is less than the programmed threshold (if the alarm function is enabled by the ALM_ENA bit)
- the battery voltage is less than the programmed low voltage level (if the ALM_ENA bit is set)
- the BATFAIL bit is set (if the ALM_ENA bit is set) Low-voltage or low-SOC alarms When a low-voltage or low-SOC condition is triggered, the STC3117 drives the ALM pin low and sets the ALM_VOLT or ALM_SOC bit in REG_CTRL. The ALM pin remains low (even if the conditions disappear) until the software writes the ALM_VOLT and ALM_SOC bits to 0 to clear the interrupt. Clearing the ALM_VOLT or ALM_SOC while the corresponding low-voltage or low-SOC condition is still true does not generate another interrupt; this condition must disappear first and must be detected again before another interrupt (ALM pin driven low) is generated for this alarm. The other alarm condition, if not yet triggered, can still generate an interrupt. Usually, the low-SOC alarm occurs first to warn the application of a low battery condition, then if no action is taken and the battery discharges further, the low-voltage alarm signals a nearly-empty battery condition. At power-up, or when the STC3117 is reset, the SOC and voltage alarms are enabled (ALM_ENA bit = 1). The ALM pin is in high-impedance directly after a POR and is driven low if the SOC and/or the voltage is below the default thresholds (1% SOC, 3.00 V), after the first OCV measurement and SOC estimation. The REG_SOC_ALM register holds the relative SOC alarm level in 0.5 % units (0 to 100 %). Default value is 2 (i.e. 1 % SOC). The REG_ALARM_VOLTAGE holds the low voltage threshold and can be programmed over BATFAIL alarm The BATFAIL bit in REG_CTRL reflects the battery swap event: BATFAIL bit is set when the BATD signal rises above the BATD threshold (1.61 V typ) for more than 0.5 s. and is reset by writing 0 to the BATFAIL bit if the BATD signal is below the BATD threshold (if BATD is still above 1.61 V, then BATFAIL bit can not be cleared). The STC3117 drives the ALM pin low when the BATFAIL bit is set and releases the ALM pin when the BATFAIL bit is cleared.
STC3117 Functional description
6.4 Current monitoring
The battery average current is monitored and is used in conjunction with a timer to implement a battery relaxation timer. Battery relaxation timer The battery relaxation timer is used to detect a light-load, low-power condition. The REG_CMONIT_COUNT register is an 8-bit, read-only counter that is incremented every 4 s when the average current is inside a window defined by positive and negative thresholds set by the REG_CURRENT_THRES register, and decremented every 500 ms when the current is outside the thresholds. When the counter reaches its maximum value set by the REG_CMONIT_MAX register, a low-power condition is reported to the mixed mode algorithm causing VM mode to be used. When the counter reaches its minimum value (0), a high-power condition is reported and CC mode is used. The REG_CMONIT_MAX register sets the maximum value of the counter. With the default value (120 dec), the counter provides an 8-minute delay when switching from CC to VM mode and a 1-minute delay when switching from VM to CC mode. The REG_CURRENT_THRES register is an 8-bit R/W register set by the gas gauge firmware from the I2C. It holds the threshold amplitude in bits 0 to 6 (unsigned value applicable for both positive and negative thresholds). Bit 7 of REG_CURRENT_THRES is reserved and must be set to zero for operation of the current monitoring counter as a relaxation timer. The LSB value of the REG_CURRENT_THRES is 47.04 µV and provides a range of 0 to 6 mV. It is possible to set the counter to zero or the maximum value using the FORCE_CC and FORCE_VM bits in the REG_MODE register. These bits are self-clearing.
6.5 Power-up and ba ttery swap detection
temperature measurement cycle is made immediately after startup and debounce delay. higher than a threshold (Vin > Vinmin_cd) at the beginning of the restart sequence. The BATD pin senses the presence of the battery independently of the battery voltage. Figure 8. BATD and CD internal architecture overview The BATD pin is an analog I/O. The input detection threshold is typically 1.61 V.
Figure 9. Timing diagram details of the power-up and restart sequence
- the battery voltage drops below the undervoltage lockout (UVLO) for more than tdel
- the BATD signal rises above the BATD threshold (1.61 V typ) for more than tdel The tdel delay is 0.5 s. Using the 0.5 s filter provides robust battery swap detection and prevents false battery swap detection if short contact bouncing occurs at the battery terminals due to mechanical vibrations or shocks. This also prevents false detections in case of short battery voltage drops and protects the application against high surge currents at low temperatures. Following a battery swap detection and after the battery voltage goes back above UVLO and the BATD level returns to low level, the STC3117 is on hold with new voltage and current measurements in the corresponding registers. The system has to restart the STC3117 by doing a device soft reset i.e. by setting the PORDET bit to 1 in the REG_CTRL register and restoring the parameters (if needed). To recover the event, either use the measured voltage and current to define a new OCV voltage, or restore a previous SOC state. The occurrence of the battery swap event is indicated by the BATFAIL and UVLOD bits in the REG_CTRL register. VCC UVLO Internal 1mA sink current Voltage measurement delay CD pin (low means HiZ) OCV meas. Application can start, charge is enabled Current measurement Temperature measurement 125 ms Conversion counter X 0 1 23 Vinmin_cd Ibat meas. (arbitrary Vcc waveforms only to illustrate the function) “Dead” battery “Good” battery GAMS1601141520CB “Good” battery “Dead” battery 375 ms 125 ms 125 ms 250 ms 100 ms
Figure 10. Restart in case of battery swap
7 I 2C interface
7.1 Read and write operations
data line (SDA) and a serial clock line (SCL).
- SCL: input clock used to shift data
- SDA: input/output bidirectional data transfers A filter rejects the potential spikes on the bus data line to preserve data integrity. The bidirectional data line supports transfers up to 400 Kbit/s (fast mode). The data are shifted to and from the chip on the SDA line, MSB first. The first bit must be high (START) followed by the 7-bit device address and the read/write control bit. The default device address value is 1110 000. The STC3117 then sends an acknowledge at the end of an 8-bit long sequence. The next eight bits correspond to the register address followed by another acknowledge. The data field is the last 8-bit long sequence sent, followed by a final acknowledge.
Figure 11. Read operation Table 8. Device address format
1110000 R / W
Table 9. Register address format Table 10. Register data format
Figure 12. Write operation
7.2 Register map and description
7.2.1 Register map
Table 11. Detailed descriptions of registers 0 (REG_MODE) and 1 (REG_CTRL) power-on reset. Table 14 gives a detailed description of the internal OCV table registers. Table 11. Register map
7.2.2 Register description
possible to read multiple values in one I2C access. All values must be consistent. is coded in 2’s complement format and the LSB value is 1°C. Table 11. Register map (continued)
7.2.3 REG_MODE and REG_CT RL register description
Table 12. REG_MODE - address 0 monitor functions are in standby.
7 Unused
Table 13. REG_CTRL - address 1 GG_RST is a self-clearing bit. Battery removal (BATD high). ALM_SOC 5 R/W 0 Set with a low-SOC condition. ALM_VOLT 6 R/W 0 Set with a low-voltage condition. UVLOD 7 R/W 0 UVLO event detection.
7.2.4 OCV table register description
Table 14. Default OCV table and OCV table registers
8 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.
Figure 13. Flip Chip CSP 1.49 x 1.594 x 0.4 mm (N5) package mechanical drawing
- The terminal A1 on the bump side is i dentified by a distinguishing feature - for instance, by a circular “clear
area” typically 0.1 mm in diameter and/or a missing bump.
- The terminal A1, on the back side, is identified by a distinguishing feature - for instance, by a circular “clear
area” typically 0.2 mm in diameter depending on the die size.
Table 15. Flip Chip CSP 1.49 x 1.594 x 0.4 mm (N5) package mechanical data
Figure 14. Flip Chip CSP 1.49 x 1.594 x 0.4 mm (N5) package footprint
Figure 15. Flip Chip CSP 1.49 x 1.594 x0.4 mm (N5) package reflow profile
9 Ordering information
Table 16. Order code Table 17. Document revision history