STAC9200 IDT | Alldatasheet
Document overview
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Technical content
Features
- High performance SD technology
- 100dB DAC SNR
- Intel HD Audio Interface
- Two Channel DACs and ADCs with 24-bit resolution
- Sample rates up to 192 KHz
- Mixer-less design
- Low-latency Karaoke Mode Supported
- Integrated Headphone Amplifiers
- Stereo Microphone
- Supports Stereo Microphone
- Microphone Boost 0, 10, 20, 30, 40dB
- Direct CDROM Recording Mixerless Design
- S/PDIF In and Out
- Universal JacksTM Functionality for jack retasking
- Adjustable VREF Out
- Digital PC Beep to all outputs
- +3.3 V, +4 V and +5 V analog power supply options (The +4 V Analog voltage is supported by the +5 V version of the STAC9200 or STAC9200D. Request +4 V configuration of the driver.)
- 32-pad QFN (5mm x 5mm) and 48-pin LQFP package options
- Dolby Sound Room Compliant (STAC9200D only) (System manufacturers must obtain system license from Dolby.)
- Dolby Home Theater Compliant (STAC9200D only) (System manufacturers must obtain system license from Dolby.)
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 2 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL Table of Contents
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 3 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 4 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 11 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL 1. DESCRIPTION The STAC9200/9200D is a high quality, 2-channel audio CODEC compatible with the Intel High Definition (HD) Audio Interface (formerly known as “Azalia”). The STAC9200/9200D provides high quality, HD Audio capability to notebook and cost sensitive de sktop PC applications. The STAC 9200/9200D has been designed as a drop-in replacement for the STAC9772/73 Dual Mode (HD Audio and AC97) 2-channel CODEC once the need to support AC97 is eliminated. The STAC9200/9200D incorporates IDT's proprietary SD technology to achieve a DAC SNR in excess of 100dB. The higher performance and quality of IDT’s audio solutions brings consumer device level performance to the notebook, desktop and media center PCs. The STAC9200/9200D provides Stereo 24-Bit, full duplex resolution supporting sample rates up to 192 KHz by the DAC and ADC. The STAC9200/9200D DAC, ADC and SPDIF In/Out support sample rates of 96 KHz, 48 KHz and 44.1 KHz. Additionally, the SPDIF Out suppo rts 32 KHz. The CODEC’s driver supports additional sample rate options. The STAC9200/9200D supports all desired two channel configurations, including switchable Headphone Out, and Universal Jacks TM functionality for automatic jack detection sensing and retasking. The SPDIF interface provides connectivity to Consumer Electronic equipment lik e Dolby Digital decoders, powered speakers, mini disk drives or to a home entertainment system. All analog I/O pairs support LINE_IN, LINE_OUT and MIC. MIC inputs can be programmed with 0/10/20/30/40dB boost. For more advanced configurations, the STAC9200/9200D has four General Purpose I/O (GPIO) pins. The STAC9200/9200D also provides a single ended CD input to avoid DRM incompatibility and to support legacy OS issues. The STAC9200/9200D integrates a headphone amplifier which is available on Ports A and D. The headphone amplifier is switchable between these two outputs fo r increased flexibility, enh anced user experience, and reduced implementation costs. The Universal Jack capabilities allow the CODEC to detect when audio devices are connected to the CODEC, sense the type of device (LINE_IN, LINE_OUT, MIC, Headphone) that is inserted, and to allow the CODEC to be reconfigured to support these devices wherever they are plugged into the system. SPDIF input sensing is also supported. The fully parametric IDT SoftEQ can be initiated upon headphone jack insertion and removal for protection of notebook speakers. The STAC9200/9200D operates with a 3.3V digital supply and is available in either 5V, 4V or 3.3V analog sup- ply. The +4V Analog voltage is supported by the +5 V version of the STAC9200 or STAC9200D appropriate configuration settings of the driver. The STAC9200/9200D is available in 48-pin LQFP and 32-pad QFN package options. The 32-pad QFN pack- age can be co-located inside the stand ard 48-pin footprint allowing systems to be designed to accept either version of the STAC9200/9200D or be compatible with existing 48-pin CODECs. Both the 48-pin LQFP and the 32-pad QFN are available in the ROHS compliant Lead (Pb) free package. The STAC9200/9200D is supported with IDT’s high qua lity software solutions whic h include drivers for all major Windows operating systems from Microsoft Para metric SoftEQ, and Digital Rights Management. Third party plugin capability is easily achieved with the IDT Ke rnel Processing Interface, to support high valued third party technologies like SRS WOW ®, Knowles® Microphone Beam forming, Waves MaxxBASS ®, Dolby Head- phone®, Dolby ProLogic II® and Dolby Virtual Speaker® and more. The STAC9200D is designed to support Dolby Sound Room and Dolby Home Theater levels of Dolby’s PC Entertainments Experience logo program.
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 12 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL 2. PERFORMANCE 2.1. Audio Fidelity 2.2. Electrical Specifications 2.2.1. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the STAC9200/9200D. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. 2.2.2. Recommended Operation Conditions DAC SNR: 100dB ADC SNR: 90dB Item Pin Maximum Rating Analog maximum supply voltage AV d d 6 Volts Digital maximum supply voltage DVdd 5.5 Volts VREFOUT output current 5 mA Voltage on any pin relative to ground Vss - 0.3 V to Vdd + 0.3 V Operating temperature 0 oC to +70oC Storage temperature -55 oC to +125 oC Soldering temperature 260 oC for 10 seconds * Soldering temperature information for all available packages begins on page 122. Parameter Min. Typ. Max. Units Power Supply V oltage Digital - 3.3 V 3.135 3.3 3.465 V Analog - 3.3 V 3.135 3.3 3.465 V (Note: The +4V Analog voltage is supported by the +5V version of the STAC9200 or STAC9200D.) Analog - 4 V 3.8 4 4.2 V Analog - 5 V 4.75 5 5.25 V Ambient Operating Temperature 0 +70 °C Case Temperature Tcase (48-LQFP) +90 °C
Table 1. Digital Power Consumption Table 2. Analog Power Consumption
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 14 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL 2.4. STAC9200/9200D 5V Analog Performance Characteristics (Tambient = 25 ºC, AVdd = 5.0V ± 5%, DVdd = 3.3V ± 5%, AVss=DVss=0V; 1 KHz input sine wave; Sample Frequency = 48 KHz; 0 dB = 1 VRMS, 10 KW/50pF load, Testbench Characterization BW: 20 Hz – 20 KHz, 0 dB settings on all gain stages) Min and Max performance targets are not included here, as specific system characteristics, such as layout, routing and external CODEC component selection, influence the perfor mance of the CODEC. To receive min/max levels for your system, please send us a unit and IDT will perform a full audio test suite and provide you with the results. Contact IDT for more information. Parameter Min Typ Max Unit Full Scale Input Voltage: All Analog Inputs with out boost -1 . 0 0 -V r m s All Analog Inputs with boost (Note 1) -0 . 0 3 -V r m s Full Scale Output: PCM (DAC) to All Analog Outputs -1 . 0 0 -V r m s HEADPHONE_OUT (32 Ω load) per channel (peak) -5 0 -m W Dynamic Range: -60dB signal level (Note 2) PCM to All Analog Outputs -9 5 - d B All Analog Inputs to A/D (1VRMS Input Referenced) - 85 -d B Analog Frequency Response (Note 3) 10 - 30,000 Hz Total Harmonic Distortion + Noise (-3dB): (Note 4) PCM to All Analog Outputs -- 90 -d B All Analog Inputs to A/D (-3dBV input Level) -- 8 5 - d B HEADPHONE_OUT (32 Ω load) -- 8 5 - d B HEADPHONE_OUT (10 KΩ load) -- 8 8 - d B SNR (idle channel) (Note 5) DAC to All Analog Outputs -1 0 0 - d B All Analog Inputs to A/D with High Pass Filter enabled - 85 -d B A/D & D/A Digital Filter Pass Band (Note 6) 20 - 19,200 Hz A/D & D/A Digital Filter Transition Band 19,200 - 28,800 Hz A/D & D/A Digital Filter Stop Band 28,800 - - Hz A/D & D/A Digital Filter Stop Band Rejcn (Note 7) -100 - - dB DAC Out-of-Band Rejection (Note 8) -55 - - dB Group Delay (48 KHz sample rate) -- 1 m s Power Supply Rejection Ratio (1 KHz) -- 7 0 - d B Power Supply Rejection Ratio (20 KHz) -- 4 0 - d B Any Analog Input to DAC (1 KHz Signal Frequency) Crosstalk -100 dB
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 15 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL 1. With +30 dB Boost on, 1.00 Vrms with Boost off. 2. Ratio of Full Scale signal to noise output with -60dB signal, measured “A weighted” over a 20 Hz to a 20 KHz bandwidth. 3. ± 1dB limits for Line Output & 0 dB gain, at -20dBV 4. Ratio of Full Scale signal to THD+N output with -3dB si gnal, measured “A weighted” over a 20 Hz to a 20 KHz bandwidth. Sample Frequency = 48 KHz. 5. Ratio of Full Scale signal to idle channel noise outp ut is measured “A weighted” over a 20 Hz to a 20 KHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 6. Peak-to-Peak Ripple over Passband meets ± 0.25dB limits, 48 KHz Sample Frequency. 7. Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise. 8. The integrated Out-of-Band noise generated by the DA C process, during normal PCM audio playback, over a bandwidth 28.8 to 100 KHz, with respect to a 1 Vrms DAC output. Any Analog Input to ADC (10 KHz Signal Frequency) Crosstalk -- 8 5 - d B Any Analog Input to ADC (1 KHz Signal Frequency) Crosstalk -- 8 0 - d B Spurious Tone Rejection - -100 - dB Attenuation, Gain Step Size ANALOG -1 . 5 - d B Attenuation, Gain Step Size DIGITAL -0 . 7 5 - d B Input Impedance -5 0 -K Ω Input Capacitance -1 5 - p F VREFout - 0.5 X AVdd - V VREF - 0.45X AVdd 0.5 V Interchannel Gain Mismatch ADC -- 0 . 5 d B Interchannel Gain Mismatch DAC -- - d B Gain Drift - 100 - ppm/ºC DAC Offset Voltage -5 1 0 m V Deviation from Linear Phase - 10 1 deg. All Analog Outputs Load Resistance -1 0 -K Ω All Analog Outputs Load Capacitance - - 50 pF HEADPHONE_OUT Load Resistance -3 2 - W HEADPHONE_OUT Load Capacitance -1 0 0 - p F Mute Attenuation -- - d B PLL lock time - 96 200 μsec PLL (or Azalia Bit CLK) 24.576 MHz clock jitter - 100 300 psec Parameter Min Typ Max Unit
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 16 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL 2.5. STAC9200/9200D 4V Analog Performance Characteristics (Tambient = 25 ºC, AVdd = 4.0V ± 5%, DVdd = 3.3V ± 5%, AVss=DVss=0V; 1 KHz input sine wave; Sample Frequency = 48 KHz; 0 dB = 1 VRMS, 10 KW/50 pF load, Testbench Characterization BW: 20 Hz – 20 Hz, 0 dB settings on all gain stages) Min and Max performance targets are not included here, as specific system characteristics, such as layout, routing and external CODEC component selection, influence the perfor mance of the CODEC. To receive min/max levels for your system, please send us a unit and IDT will perform a full audio test suite and provide you with the results. Contact IDT for more information. Parameter Min Typ Max Unit Full Scale Input Voltage: All Analog Inputs with out boost -1 . 0 0 - V r m s All Analog Inputs with boost (Note 1) -0 . 0 3 - V r m s Full Scale Output: PCM (DAC) to All Analog Outputs -1 . 0 0 - V r m s HEADPHONE_OUT (32 Ω load) per channel (peak) -5 0 - m W Dynamic Range: -60dB signal level (Note 2) PCM to All Analog Outputs -9 5 - d B All Analog Inputs to A/D (1VRMS Input Referenced) - 85 -d B Analog Frequency Response (Note 3) 10 - 30,000 Hz Total Harmonic Distortion + Noise (-3dB): (Note 4) PCM to All Analog Outputs -- 90 -d B All Analog Inputs to A/D (-3dBV input Level) -- 8 5 -d B HEADPHONE_OUT (32 Ω load) -- 8 5 -d B HEADPHONE_OUT (10 KΩ load) -- 8 8 -d B SNR (idle channel) (Note 5) DAC to All Analog Outputs -1 0 0 -d B All Analog Inputs to A/D with High Pass Filter enabled - 85 -d B A/D & D/A Digital Filter Pass Band (Note 6) 20 - 19,200 Hz A/D & D/A Digital Filter Transition Band 19,200 - 28,800 Hz A/D & D/A Digital Filter Stop Band 28,800 - - Hz A/D & D/A Digital Filter Stop Band Rejcn (Note 7) -100 - - dB DAC Out-of-Band Rejection (Note 8) -55 - - dB Group Delay (48 KHz sample rate) -- 1 m s Power Supply Rejection Ratio (1 Hz) -- 7 0 -d B Power Supply Rejection Ratio (20 Hz) -- 4 0 -d B Any Analog Input to ADC (10 KHz Signal Frequency) Crosstalk -- 8 5 -d B
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 17 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL 1. With +30dB Boost on, 1.00 Vrms with Boost off. 2. Ratio of Full Scale signal to noise output with -60dB signal, measured “A weighted” over a 20 Hz to a 20 KHz bandwidth. 3. ± 1dB limits for Line Output & 0 dB gain, at -20dBV 4. Ratio of Full Scale signal to THD+N output with -3dB si gnal, measured “A weighted” over a 20 Hz to a 20 KHz bandwidth. Sample Frequency = 48 KHz. 5. Ratio of Full Scale signal to idle channel noise outp ut is measured “A weighted” over a 20 Hz to a 20 KHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 6. Peak-to-Peak Ripple over Passband meets ± 0.25dB limits, 48 KHz Sample Frequency. 7. Stop Band rejection determines filter requiremen ts. Out-of-Band rejection determines audible noise. 8. The integrated Out-of-Band noise generated by the DA C process, during normal PCM audio playback, over a bandwidth 28.8 to 100 KHz, with respect to a 1 Vrms DAC output. Any Analog Input to ADC (1 KHz Signal Frequency) Crosstalk -- 8 0 -d B Spurious Tone Rejection -- 1 0 0 - d B Attenuation, Gain Step Size ANALOG -1 . 5 -d B Attenuation, Gain Step Size DIGITAL -0 . 7 5 - d B Input Impedance -5 0 - K Ω Input Capacitance -1 5 - p F VREFout - 0.5 X AVdd - V VREF - 0.45X AVdd 0.5 V Interchannel Gain Mismatch ADC -- 0 . 5 d B Interchannel Gain Mismatch DAC -- - d B Gain Drift 100 - ppm/ºC DAC Offset Voltage -5 1 0 m V Deviation from Linear Phase - 10 1 deg. All Analog Outputs Load Resistance -1 0 - K Ω All Analog Outputs Load Capacitance - - 50 pF HEADPHONE_OUT Load Resistance -3 2 - W HEADPHONE_OUT Load Capacitance -100 - pF Mute Attenuation -- - d B PLL lock time - 96 200 μsec PLL (or Azalia Bit CLK) 24.576 MHz clock jitter - 100 300 psec Parameter Min Typ Max Unit
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 18 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL 2.6. STAC9200/9200D 3.3V Analog Performance Characteristics (Tambient = 25 ºC, AVdd = 3.3V ± 5%, DVdd = 3.3V ± 5%, AVss=DVss=0V; 1 KHz input sine wave; Sample Frequency = 48 KHz; 0 dB = 1 VRMS, 10 KW/50 pF load, Testbench Characterization BW: 20 Hz – 20 KHz, 0 dB settings on all gain stages) Min and Max performance targets are not included here, as specific system characteristics, such as layout, routing and external CODEC component selection, influence the perfor mance of the CODEC. To receive min/max levels for your system, please send us a unit and IDT will perform a full audio test suite and provide you with the results. Contact IDT for more information. Parameter Min Typ Max Unit Full Scale Input Voltage: All Analog Inputs with out boost -0 . 7 - V r m s All Analog Inputs with boost (Note 1) -0 . 0 3 - V r m s Full Scale Output: PCM (DAC) to All Analog Outputs -1 . 0 0 - V r m s HEADPHONE_OUT (32 Ω load) per channel (peak) -5 0 - m W Dynamic Range: -60dB signal level (Note 2) PCM to All Analog Outputs -9 5 -d B All Analog Inputs to A/D (1VRMS Input Referenced) - 80 -d B Analog Frequency Response (Note 3) 10 - 30,000 Hz Total Harmonic Distortion + Noise (-3dB): (Note 4) PCM to All Analog Outputs -- 90 -d B All Analog Inputs to A/D (-3dBV input Level) -- 7 5 - d B HEADPHONE_OUT (32 Ω load) -- 8 5 - d B HEADPHONE_OUT (10 KΩ load) -- 8 8 - d B SNR (idle channel) (Note 5) DAC to All Analog Outputs -1 0 0 - d B All Analog Inputs to A/D with High Pass Filter enabled - 85 -d B A/D & D/A Digital Filter Pass Band (Note 6) 20 - 19,200 Hz A/D & D/A Digital Filter Transition Band 19,200 - 28,800 Hz A/D & D/A Digital Filter Stop Band 28,800 - - Hz A/D & D/A Digital Filter Stop Band Rejcn (Note 7) -100 - - dB DAC Out-of-Band Rejection (Note 8) -55 - - dB Group Delay (48 KHz sample rate) -- 1 m s Power Supply Rejection Ratio (1 KHz) -- 7 0 - d B Power Supply Rejection Ratio (20 KHz) -- 4 0 - d B Any Analog Input to ADC (10 KHz Signal Frequency) Crosstalk -- 8 5 - d B
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 19 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL 1. With +30 dB Boost on, 1.00 Vrms with Boost off. 2. Ratio of Full Scale signal to noise output with -60dB signal, measured “A weighted” over a 20 Hz to a 20 KHz bandwidth. 3. ± 1dB limits for Line Output & 0 dB gain, at -20dBV 4. Ratio of Full Scale signal to THD+N output with -3dB si gnal, measured “A weighted” over a 20 Hz to a 20 KHz bandwidth. Sample Frequency = 48 KHz. 5. Ratio of Full Scale signal to idle channel noise outp ut is measured “A weighted” over a 20 Hz to a 20 KHz bandwidth. (AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio). 6. Peak-to-Peak Ripple over Passband meets ± 0.25dB limits, 48 KHz Sample Frequency. 7. Stop Band rejection determines filter requiremen ts. Out-of-Band rejection determines audible noise. 8. The integrated Out-of-Band noise generated by the DA C process, during normal PCM audio playback, over a bandwidth 28.8 to 100 KHz, with respect to a 1 Vrms DAC output. Any Analog Input to ADC (1 KHz Signal Frequency) Crosstalk -- 7 5 - d B Spurious Tone Rejection - -100 - dB Attenuation, Gain Step Size ANALOG -1 . 5 -d B Attenuation, Gain Step Size DIGITAL -0 . 7 5 - d B Input Impedance -5 0 - K Ω Input Capacitance -1 5 -p F VREFout - 0.5 X AVdd - V VREF - 0.45X AVdd 0.5 V Interchannel Gain Mismatch ADC -- 0 . 5 d B Interchannel Gain Mismatch DAC -- - d B Gain Drift 100 - ppm/ºC DAC Offset Voltage -5 1 0 m V Deviation from Linear Phase - 10 1 deg. All Analog Outputs Load Resistance -1 0 - K Ω All Analog Outputs Load Capacitance -- 5 0 p F HEADPHONE_OUT Load Resistance -3 2 - W HEADPHONE_OUT Load Capacitance -1 0 0 - p F Mute Attenuation -- - d B PLL lock time - 96 200 μsec PLL (or Azalia Bit CLK) 24.576 MHz clock jitter - 100 300 psec Parameter Min Typ Max Unit
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 20 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL 3. EXTENDED FEATURE EXPLANATION 3.1. SPDIF Input SPDIF IN can run at 44.1 KHz, 48 KHz and 96 KHz, and has internal Jack Sensing. A sophisticated digital PLL allows automatic rate detection and accurate data recovery. The ability to directly accept consumer SPDIF vo ltage levels eliminates the need for costly external receiver ICs. Advanced features such as record slot select a nd SPDIF_IN routing to the DAC allows for simulta- neous record and play. 3.2. SPDIF Output SPDIF Output can run at 44.1 KHz, 48 KHz, and 96 KHz at bit rates up to 24 bits, as defined in the Intel High Definition Audio Specification. This insures compatibility with all consumer audio gear and allows for convenient integration into home theater systems and multi-media centers. 3.3. Universal Jacks TM IDT’s Universal JacksTM technology allows for the greatest flexibility in board design and implemen- tation. For the STAC9200/9200D the Universal JacksTM capabilities are as follows
- All of the STAC9200/9200D ports support:
- Line Out
- Line In
- Mic with 0/10/20/30/40 dB Mic Boost
- Ports A and D also support
- Headphone Out 1Headphone capabilities are available on pins 39 /41 and 35/36, but one should not put headphone loads on both sets of pins at the same time. Note: On the STAC9200/9200D only one function can be selected at a time, you cannot have an input and output at the same time on the same set of pins. This function can be changed at any time. 3.4. Audio Jack Presence Detect Sense_A pin is used to detect the presence of plug s in ports A, B, C, and D. Refer to the reference design for port detect circuitry. Select the precision of the resistors used as follows: Includes pull-up resistors on Sense A and series resistors between jack switch and Sense A. AVDD Nominal Voltage (+- 5%) Resistor Tolerance (If Port D is used) Resistor Tolerance (If Port D is not used) 5V 1% 1% 4.5V 1% 1% 4V 0.50% 1% 3.3V 0.10% 1%
- BLOCK DIAGRAMS AND TYPICAL HOOKUPS
Figure 1. Functional Block Diagram
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 22 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL 4.2. STAC9200/9200D Ty pical Connection Diagram for 48-pin LQFP Please see the reference design for this information. 4.3. STAC9200/9200D Split Independ ent Power Supply for 48-pin LQFP Please see the reference design for this information. 4.4. STAC9200/9200D Ty pical Connection Diagram for 32-pad QFN Please see the reference design for this information. 4.5. STAC9200/9200D Split Independ ent Power Supply for 32-pad QFN Please see the reference design for this information.
Figure 2. Widget Diagram
Table 3. High Definition Audio Widget
Table 4. Root PnpID Command Verb Format Table 5. Root PnpID Command Response Format Table 6. Root RevID Command Verb Format Table 7. Root RevID Command Response Format [23.:20] Major R 0x1 Major rev number of compliant Azalia spec. [19.:16] Minor R 0x0 Minor rev number of compliant Azalia spec.
Table 8. Root NodeInfo Command Verb Format Table 9. Root NodeInfo Command Response Format Table 10. AFG Reset Command Verb Format Table 11. AFG Reset Command Response Format [31.:0] Response R 0x0 Reserved. Overlaps Execute.
Table 12. AFG NodeInfo Command Verb Format Table 13. AFG NodeInfo Command Response Format [7.:0] TotalNodes R 0x13 Total number of nodes. Table 14. AFG Type Command Verb Format Table 15. AFG Type Command Response Format Unsolicited Response verb (Verb ID 708h). Table 16. AFG GrpCap Command Verb Format
Table 17. AFG GrpCap Command Response Format Table 18. AFG FrmtCap Command Verb Format Table 19. AFG FrmtCap Command Response Format
Table 20. AFG StreamCap Command Verb Format Table 21. AFG StreamCap Command Response Format [2] NonPCM R 0x0 No support for non-PCM (AC3) data. [1] Float32 R 0x0 No support for single-precision floating-point data. [0] PCM R 0x1 PCM-formatted data supported.
Table 22. AFG PwrCap Command Verb Format Table 23. AFG PwrCap Command Response Format subsequent Power State command). can return to fully on state within 10 ms. Table 24. AFG GPIOCap Command Verb Format
Table 25. AFG GPIOCap Command Response Format a change in level on the pin. Table 26. AFG OutAmpCap Command Verb Format Table 27. AFG OutAmpCap Command Response Format
Table 28. AFG PwrState Command Verb Format Table 29. AFG PwrState Command Response Format [7.:4] Act R 0x2 PS-Act: Actual power state of referenced node. PS-Set: Current power setting of referenced node. Table 30. AFG UnsolResp Command Verb Format
Table 31. AFG UnsolResp Command Response Format [7] En RW 0x0 Allow generation of Unsolicited Responses. Response generated by this node. Table 32. AFG GPIO Command Verb Format Table 33. AFG GPIO Command Response Format
Table 34. AFG GPIOEn Command Verb Format Table 35. AFG GPIOEn Command Response Format
Table 36. AFG GPIODir Command Verb Format Table 37. AFG GPIODir Command Response Format Table 38. AFG GPIOWake Command Verb Format
Table 39. AFG GPIOWake Command Response Format Change Request event on the link. Change Request event on the link. Change Request event on the link. Change Request event on the link. Table 40. AFG GPIOUnsolEn Command Verb Format Table 41. AFG GPIOUnsolEn Command Response Format GPIO3 is configured as input and changes state.
GPIO2 is configured as input and changes state. GPIO1 is configured as input and changes state. GPIO0 is configured as input and changes state. Table 42. AFG GPIOSticky Command Verb Format Table 43. AFG GPIOSticky Command Response Format corresponding bit of GPIO Data register. corresponding bit of GPIO Data register.
corresponding bit of GPIO Data register. corresponding bit of GPIO Data register. Table 44. AFG SysID Command Verb Format Table 45. AFG SysID Command Response Format
Table 46. DAC0Cnvtr Frmt Command Verb Format Table 47. DAC0Cnvtr Frmt Command Response Format
Table 48. DAC0Cnvtr WCap Command Verb Format Table 49. DAC0Cnvtr WCap Command Response Format
Table 50. DAC0Cnvtr PwrState Command Verb Format Table 51. DAC0Cnvtr PwrState Command Response Format [7.:4] Act R 0x3 PS-Act: Actual power state of referenced node.
Table 52. DAC0Cnvtr Stream Command Verb Format Table 53. DAC0Cnvtr Stream Command Response Format convention stream 0 is reserved as unused. Table 54. ADC0Cnvtr Frmt Command Verb Format Table 55. ADC0Cnvtr Frmt Command Response Format
Table 56. ADC0Cnvtr WCap Command Verb Format
Table 57. ADC0Cnvtr WCap Command Response Format Table 58. ADC0Cnvtr ConnLen Command Verb Format
Table 59. ADC0Cnvtr ConnLen Command Response Format [31.:8] Rsvd R 0x0 Reserved. [6.:0] N R 0x01 Number of NID entries in connection list. Table 60. ADC0Cnvtr ConnLst Command Verb Format Table 61. ADC0Cnvtr ConnLst Command Response Format [31.:24] Entry3 R 0x00 Unused list entry. [23.:16] Entry2 R 0x00 Unused list entry. [15.:8] Entry1 R 0x00 Unused list entry. [7.:0] Entry0 R 0x0A ADC Mux widget. Table 62. ADC0Cnvtr ProcState Command Verb Format
Table 63. ADC0Cnvtr ProcState Command Response Format ADC high pass filter is enabled. Table 64. ADC0Cnvtr PwrState Command Verb Format Table 65. ADC0Cnvtr PwrState Command Response Format [7.:4] Act R 0x3 PS-Act: Actual power state of referenced node.
Table 66. ADC0Cnvtr Stream Command Verb Format Table 67. ADC0Cnvtr Stream Command Response Format convention stream 0 is reserved as unused. Table 68. SPDIFinCnvtr Frmt Command Verb Format Table 69. SPDIFinCnvtr Frmt Command Response Format
Table 70. SPDIFinCnvtr WCap Command Verb Format Table 71. SPDIFinCnvtr WCap Command Response Format
Table 72. SPDIFinCnvtr FrmtCap Command Verb Format Table 73. SPDIFinCnvtr FrmtCap Command Response Format
Table 74. SPDIFinCnvtr StreamCap Command Verb Format
Table 75. SPDIFinCnvtr StreamCap Command Response Format [2] NonPCM R 0x1 Non-PCM data supported. [1] Float32 R 0x0 No support for Float32 data. [0] PCM R 0x1 PCM-formatted data supported. Table 76. SPDIFinCnvtr ConnLen Command Verb Format Table 77. SPDIFinCnvtr ConnLen Command Response Format [31.:8] Rsvd R 0x0 Reserved. [7] LongForm R 0x0 Connection list uses short-form (7-bit) NID entries. [6.:0] N R 0x01 Number of NID entries in connection list. Table 78. SPDIFinCnvtr ConnLst Command Verb Format Table 79. SPDIFinCnvtr ConnLst Command Response Format [31.:24] Entry3 R 0x00 Unused list entry. [23.:16] Entry2 R 0x00 Unused list entry.
[15.:8] Entry1 R 0x00 Unused list entry. [7.:0] Entry0 R 0x08 SPDIF-In Pin widget. Table 80. SPDIFinCnvtr Stream Command Verb Format Table 81. SPDIFinCnvtr Stream Command Response Format stream 0 is reserved as unused. Table 82. SPDIFinCnvtr DigCtl Command Verb Format Table 83. SPDIFinCnvtr DigCtl Command Response Format
Table 84. SPDIFoutCnvtr Frmt Command Verb Format Table 85. SPDIFoutCnvtr Frmt Command Response Format
Table 86. SPDIFoutCnvtr WCap Command Verb Format
Table 87. SPDIFoutCnvtr WCap Command Response Format Table 88. SPDIFoutCnvtr FrmtCap Command Verb Format
Table 89. SPDIFoutCnvtr FrmtCap Command Response Format Table 90. SPDIFoutCnvtr StreamCap Command Verb Format
Table 91. SPDIFoutCnvtr StreamCap Command Response Format [2] NonPCM R 0x1 Non-PCM data supported. [1] Float32 R 0x0 No support for Float32 data. [0] PCM R 0x1 PCM-formatted data supported. Table 92. SPDIFoutCnvtr Stream Command Verb Format Table 93. SPDIFoutCnvtr Stream Command Response Format convention stream 0 is reserved as unused. Table 94. SPDIFoutCnvtr DigCtl Command Verb Format
Table 95. SPDIFoutCnvtr DigCtl Command Response Format Table 96. DAC0Mux WCap Command Verb Format Table 97. DAC0Mux WCap Command Response Format
[6] ProcWidget R 0x0 No Processing Controls parameter. Table 98. DAC0Mux ConnLen Command Verb Format Table 99. DAC0Mux ConnLen Command Response Format [31.:8] Rsvd R 0x0 Reserved. [7] LongForm R 0x0 Connection list uses short-form (7-bit) NID entries. [6.:0] N R 0x03 Number of NID entries in connection list.
Table 100. DAC0Mux ConnSel Command Verb Format Table 101. DAC0Mux ConnSel Command Response Format [1.:0] Index RW 0x0 Connection select control index. Table 102. DAC0Mux ConnLst Command Verb Format Table 103. DAC0Mux ConnLst Command Response Format [31.:24] Entry3 R 0x00 Unused list entry. [23.:16] Entry2 R 0x0A ADC Mux widget. [15.:8] Entry1 R 0x08 SPDIF-In Pin widget. [7.:0] Entry0 R 0x02 DAC Analog converter widget. Table 104. DAC0Mux LR Command Verb Format
Table 105. DAC0Mux LR Command Response Format [2] SwapEn RW 0x0 1= swap left and right channels of this Widget. Table 106. DigInPin WCap Command Verb Format Table 107. DigInPin WCap Command Response Format
Table 108. DigInPin Cap Command Verb Format Table 109. DigInPin Cap Command Response Format [15.:8] VRefCntrl R 0x00 VRef generation not supported by this pin complex. [6] BalancedIO R 0x0 Pin complex does not have balanced pins. [5] InCap R 0x1 Pin complex is input capable. [4] OutCap R 0x0 Pin complex is not output capable. [3] HPhnDrvCap R 0x0 Pin does not have a headphone amplifier. [2] PresDtctCap R 0x1 Pin complex can perform Presence Detect. [0] ImpSenseCap R 0x0 Pin complex does not support impedance sense.
Table 110. DigInPin PwrState Command Verb Format Table 111. DigInPin PwrState Command Response Format [7.:4] Act R 0x3 PS-Act: Actual power state of referenced node. Table 112. DigInPin Ctl Command Verb Format Table 113. DigInPin Ctl Command Response Format
Table 114. DigInPin UnsolResp Command Verb Format Table 115. DigInPin UnsolResp Command Response Format Allow generation of Unsolicited Responses. loss-of-lock by SPDIF-in clock recovery circuit. Table 116. DigInPin Sense Command Verb Format
Table 117. DigInPin Sense Command Response Format Table 118. DigInPin EAPD Command Verb Format Table 119. DigInPin EAPD Command Response Format EAPD value reflected on the EAPD pin. 1= power up external amp if PwrState < 0x2. when Pin Widget is powered down. Table 120. DigInPin Config Command Verb Format
Table 121. DigInPin Config Command Response Format [31.:30] Port RW 0x0 External Port Connectivity of the Pin Complex. [23.:20] Device RW 0xC Default Device, indicating intended use of jack. [11.:8] Misc RW 0x0 Misc[0] == Jack Detect override. Default Association for Pin Complex groups. Reserved value 0000b should not be used. Value 1111b indicates lowest priority. Table 122. DigOutPin WCap Command Verb Format
Table 123. DigOutPin WCap Command Response Format Table 124. DigOutPin Cap Command Verb Format
Table 125. DigOutPin Cap Command Response Format [15.:8] VRefCntrl R 0x00 VRef generation N/A since pin complex is not input capable. [6] BalancedIO R 0x0 Pin complex does not have balanced pins. [5] InCap R 0x0 Pin complex is not input capable. [4] OutCap R 0x1 Pin complex is output capable. [3] HPhnDrvCap R 0x0 Pin does not have a headphone amplifier. [2] PresDtctCap R 0x0 Pin complex cannot perform Presence Detect. [0] ImpSenseCap R 0x0 Pin complex does not support impedance sense. Table 126. DigOutPin ConnLen Command Verb Format Table 127. DigOutPin ConnLen Command Response Format [31.:8] Rsvd R 0x0 Reserved. [7] LongForm R 0x0 Connection list uses short-form (7-bit) NID entries. [6.:0] N R 0x02 Number of NID entries in connection list.
Table 128. DigOutPin ConnSel Command Verb Format Table 129. DigOutPin ConnSel Command Response Format [1.:0] Index RW 0x0 Connection select control index. Table 130. DigOutPin ConnLst Command Verb Format Table 131. DigOutPin ConnLst Command Response Format [31.:24] Entry3 R 0x00 Unused list entry. [23.:16] Entry2 R 0x00 Unused list entry. [15.:8] Entry1 R 0x0A ADC Mux widget. [7.:0] Entry0 R 0x05 SPDIF Out converter widget. Table 132. DigOutPin Ctl Command Verb Format
Table 133. DigOutPin Ctl Command Response Format Table 134. DigOutPin Config Command Verb Format Table 135. DigOutPin Config Command Response Format [31.:30] Port RW 0x0 External Port Connectivity of the Pin Complex. [23.:20] Device RW 0x4 Default Device, indicating intended use of jack. [11.:8] Misc RW 0x0 Misc[0] == Jack Detect override.
Default Association for Pin Complex groups. Reserved value 0000b should not be used. Value 1111b indicates lowest priority. Table 136. ADC0Mux VolRight Command Verb Format Table 137. ADC0Mux VolRight Command Response Format Table 138. ADC0Mux VolLeft Command Verb Format
Table 139. ADC0Mux VolLeft Command Response Format Table 140. ADC0Mux WCap Command Verb Format Table 141. ADC0Mux WCap Command Response Format [6] ProcWidget R 0x0 No Processing Controls parameter.
[3] AmpParamOvrd R 0x1 This widget contains its own amplifier parameters. Table 142. ADC0Mux OutAmpCap Command Verb Format Table 143. ADC0Mux OutAmpCap Command Response Format Table 144. ADC0Mux ConnLen Command Verb Format
Table 145. ADC0Mux ConnLen Command Response Format [7] LongForm R 0x0 Connection list uses short-form (7-bit) NID entries. [6.:0] N R 0x01 Number of NID entries in connection list. Table 146. ADC0Mux ConnLst Command Verb Format Table 147. ADC0Mux ConnLst Command Response Format [31.:24] Entry3 R 0x00 Unused list entry. [23.:16] Entry2 R 0x00 Unused list entry. [15.:8] Entry1 R 0x00 Unused list entry. [7.:0] Entry0 R 0x0C Input Port (UnivJack) Mux widget. Table 148. ADC0Mux LR Command Verb Format Table 149. ADC0Mux LR Command Response Format
[2] SwapEn RW 0x0 1= swap left and right channels of this Widget. Table 150. MasterVol Right Command Verb Format Table 151. MasterVol Right Command Response Format Table 152. MasterVol Left Command Verb Format
Table 153. MasterVol Left Command Response Format Table 154. MasterVol WCap Command Verb Format Table 155. MasterVol WCap Command Response Format [6] ProcWidget R 0x0 No Processing Controls parameter.
Table 156. MasterVol ConnLen Command Verb Format Table 157. MasterVol ConnLen Command Response Format [7] LongForm R 0x0 Connection list uses short-form (7-bit) NID entries. [6.:0] N R 0x01 Number of NID entries in connection list. Table 158. MasterVol ConnLst Command Verb Format Table 159. MasterVol ConnLst Command Response Format [31.:24] Entry3 R 0x00 Unused list entry. [23.:16] Entry2 R 0x00 Unused list entry.
[15.:8] Entry1 R 0x00 Unused list entry. [7.:0] Entry0 R 0x07 DAC Mux widget. Table 160. InPortMux VolRight Command Verb Format Table 161. InPortMux VolRight Command Response Format Table 162. InPortMux VolLeft Command Verb Format Table 163. InPortMux VolLeft Command Response Format
Table 164. InPortMux WCap Command Verb Format Table 165. InPortMux WCap Command Response Format [6] ProcWidget R 0x0 No Processing Controls parameter. [3] AmpParamOvrd R 0x1 This widget contains its own amplifier parameters.
Table 166. InPortMux ConnLen Command Verb Format Table 167. InPortMux ConnLen Command Response Format [7] LongForm R 0x0 Connection list uses short-form (7-bit) NID entries. [6.:0] N R 0x05 Number of NID entries in connection list. Table 168. InPortMux AmpCap Command Verb Format Table 169. InPortMux AmpCap Command Response Format
Table 170. InPortMux ConnSel Command Verb Format Table 171. InPortMux ConnSel Command Response Format [2.:0] Index RW 0x0 Connection select control index. Table 172. InPortMux ConnLst0 Command Verb Format Table 173. InPortMux ConnLst0 Command Response Format [31.:24] Entry3 R 0x0D Port A pin widget. [23.:16] Entry2 R 0x0E Port D pin widget. [15.:8] Entry1 R 0x0F Port C pin widget. [7.:0] Entry0 R 0x10 Port B pin widget. Table 174. InPortMux ConnLst4 Command Verb Format
Table 175. InPortMux ConnLst4 Command Response Format [31.:24] Entry3 R 0x00 Unused list entry. [23.:16] Entry2 R 0x00 Unused list entry. [15.:8] Entry1 R 0x00 Unused list entry. [7.:0] Entry0 R 0x12 CDin pin widget. Table 176. PortAPin WCap Command Verb Format Table 177. PortAPin WCap Command Response Format
parameters from Audio Function node instead. Table 178. PortAPin Cap Command Verb Format Table 179. PortAPin Cap Command Response Format [15.:8] VRefCntrl R 0x00 VRef generation not supported by this pin complex. [6] BalancedIO R 0x0 Pin complex does not have balanced pins. [5] InCap R 0x1 Pin complex is input capable. [4] OutCap R 0x1 Pin complex is output capable. [3] HPhnDrvCap R 0x1 Pin complex has headphone amplifier. [2] PresDtctCap R 0x1 Pin complex can perform Presence Detect. [0] ImpSenseCap R 0x1 Pin complex supports impedance sense.
Table 180. PortAPin ConnLen Command Verb Format Table 181. PortAPin ConnLen Command Response Format [31.:8] Rsvd R 0x0 Reserved. [7] LongForm R 0x0 Connection list uses short-form (7-bit) NID entries. [6.:0] N R 0x01 Number of NID entries in connection list. Table 182. PortAPin ConnLst Command Verb Format Table 183. PortAPin ConnLst Command Response Format [31.:24] Entry3 R 0x00 Unused list entry. [23.:16] Entry2 R 0x00 Unused list entry. [15.:8] Entry1 R 0x00 Unused list entry. [7.:0] Entry0 R 0x0B Master Volume widget. Table 184. PortAPin Ctl Command Verb Format
Table 185. PortAPin Ctl Command Response Format Table 186. PortAPin UnsolResp Command Verb Format Table 187. PortAPin UnsolResp Command Response Format Allow generation of Unsolicited Responses.
Table 188. PortAPin Sense Command Verb Format Table 189. PortAPin Sense Command Response Format Table 190. PortAPin Config Command Verb Format
Table 191. PortAPin Config Command Response Format [11.:8] Misc RW 0x0 Misc[0] = Jack Detect override. Table 192. PortDPin WCap Command Verb Format Table 193. PortDPin WCap Command Response Format
parameters from Audio Function node instead. Table 194. PortDPin Cap Command Verb Format Table 195. PortDPin Cap Command Response Format [15.:8] VRefCntrl R 0x00 VRef generation not supported by this pin complex. [6] BalancedIO R 0x0 Pin complex does not have balanced pins.
[5] InCap R 0x1 Pin complex is input capable. [4] OutCap R 0x1 Pin complex is output capable. [3] HPhnDrvCap R 0x1 Pin complex has headphone amplifier. [2] PresDtctCap R 0x1 Pin complex can perform Presence Detect. [0] ImpSenseCap R 0x1 Pin complex supports impedance sense. Table 196. PortDPin ConnLen Command Verb Format Table 197. PortDPin ConnLen Command Response Format [31.:8] Rsvd R 0x0 Reserved. [7] LongForm R 0x0 Connection list uses short-form (7-bit) NID entries. [6.:0] N R 0x01 Number of NID entries in connection list. Table 198. PortDPin ConnLst Command Verb Format
Table 199. PortDPin ConnLst Command Response Format [31.:24] Entry3 R 0x00 Unused list entry. [23.:16] Entry2 R 0x00 Unused list entry. [15.:8] Entry1 R 0x00 Unused list entry. [7.:0] Entry0 R 0x0B Master Volume widget. Table 200. PortDPin Ctl Command Verb Format Table 201. PortDPin Ctl Command Response Format Table 202. PortDPin UnsolResp Command Verb Format
Table 203. PortDPin UnsolResp Command Response Format of every Unsolicited Response generated by this node. Table 204. PortDPin Sense Command Verb Format Table 205. PortDPin Sense Command Response Format
Table 206. PortDPin Config Command Verb Format Table 207. PortDPin Config Command Response Format [31.:30] Port RW 0x0 External Port Connectivity of the Pin Complex. [23.:20] Device RW 0x0 Default Device, indicating intended use of jack. [11.:8] Misc RW 0x0 Misc[0] = Jack Detect override. Default Association for Pin Complex groups. 1111b indicates lowest priority. Table 208. PortCPin WCap Command Verb Format
Table 209. PortCPin WCap Command Response Format parameters from Audio Function node instead. Table 210. PortCPin Cap Command Verb Format
Table 211. PortCPin Cap Command Response Format [15.:8] VRefCntrl R 0x00 VRef generation not supported by this pin complex. [6] BalancedIO R 0x0 Pin complex does not have balanced pins. [5] InCap R 0x1 Pin complex is input capable. [4] OutCap R 0x1 Pin complex is output capable. [3] HPhnDrvCap R 0x0 Pin does not have a headphone amplifier. [2] PresDtctCap R 0x1 Pin complex can perform Presence Detect. [0] ImpSenseCap R 0x1 Pin complex supports impedance sense. Table 212. PortCPin ConnLen Command Verb Format Table 213. PortCPin ConnLen Command Response Format [7] LongForm R 0x0 Connection list uses short-form (7-bit) NID entries. [6.:0] N R 0x01 Number of NID entries in connection list.
Table 214. PortCPin ConnLst Command Verb Format Table 215. PortCPin ConnLst Command Response Format [31.:24] Entry3 R 0x00 Unused list entry. [23.:16] Entry2 R 0x00 Unused list entry. [15.:8] Entry1 R 0x00 Unused list entry. [7.:0] Entry0 R 0x0B Master Volume widget. Table 216. PortCPin Ctl Command Verb Format Table 217. PortCPin Ctl Command Response Format
Table 218. PortCPin UnsolResp Command Verb Format Table 219. PortCPin UnsolResp Command Response Format Allow generation of Unsolicited Responses. OR completion of a Jack-Sense cycle. Table 220. PortCPin Sense Command Verb Format Table 221. PortCPin Sense Command Response Format
Table 222. PortCPin Config Command Verb Format Table 223. PortCPin Config Command Response Format [31.:30] Port RW 0x0 External Port Connectivity of the Pin Complex. [29.:24] Location RW 0x01 Physical location of the jack. [23.:20] Device RW 0x8 Default Device, indicating intended use of jack. [11.:8] Misc RW 0x0 Misc[0] = Jack Detect override.
Default Association for Pin Complex groups. Reserved value 0000b should not be used. Value 1111b indicates lowest priority. Table 224. PortBPin WCap Command Verb Format Table 225. PortBPin WCap Command Response Format
parameters from Audio Function node instead. Table 226. PortBPin Cap Command Verb Format Table 227. PortBPin Cap Command Response Format [6] BalancedIO R 0x0 Pin complex does not have balanced pins. [5] InCap R 0x1 Pin complex is input capable. [4] OutCap R 0x1 Pin complex is output capable. [3] HPhnDrvCap R 0x0 Pin does not have a headphone amplifier. [2] PresDtctCap R 0x1 Pin complex can perform Presence Detect. [0] ImpSenseCap R 0x1 Pin complex supports impedance sense.
Table 228. PortBPin ConnLen Command Verb Format Table 229. PortBPin ConnLen Command Response Format [31.:8] Rsvd R 0x0 Reserved. [7] LongForm R 0x0 Connection list uses short-form (7-bit) NID entries. [6.:0] N R 0x01 Number of NID entries in connection list. Table 230. PortBPin ConnLst Command Verb Format Table 231. PortBPin ConnLst Command Response Format [31.:24] Entry3 R 0x00 Unused list entry. [23.:16] Entry2 R 0x00 Unused list entry. [15.:8] Entry1 R 0x00 Unused list entry. [7.:0] Entry0 R 0x0B Master Volume widget. Table 232. PortBPin Ctl Command Verb Format
Table 233. PortBPin Ctl Command Response Format take the value of 000b (Hi-Z). Table 234. PortBPin UnsolResp Command Verb Format Table 235. PortBPin UnsolResp Command Response Format Allow generation of Unsolicited Responses. jack-insertion OR completion of a Jack-Sense cycle.
Table 236. PortBPin Sense Command Verb Format Table 237. PortBPin Sense Command Response Format measurement is busy if it has been recently triggered. Table 238. PortBPin Config Command Verb Format
Table 239. PortBPin Config Command Response Format [31.:30] Port RW 0x0 External Port Connectivity of the Pin Complex. [11.:8] Misc RW 0x0 Misc[0] = Jack Detect override. should not be used. Value 1111b indicates lowest priority. [3.:0] Sequence RW 0x0 All Widgets in an association must have unique sequence number. Table 240. MonoOutPin Vol Command Verb Format Table 241. MonoOutPin Vol Command Response Format
Table 242. MonoOutPin WCap Command Verb Format Table 243. MonoOutPin WCap Command Response Format parameters from Audio Function node instead.
Table 244. MonoOutPin Cap Command Verb Format Table 245. MonoOutPin Cap Command Response Format [6] BalancedIO R 0x0 Pin complex does not have balanced pins. [5] InCap R 0x0 Pin complex is not input capable. [4] OutCap R 0x1 Pin complex is output capable. [3] HPhnDrvCap R 0x0 Pin does not have a headphone amplifier. [2] PresDtctCap R 0x0 Pin complex cannot perform Presence Detect. Table 246. MonoOutPin ConnLen Command Verb Format
Table 247. MonoOutPin ConnLen Command Response Format [6.:0] N R 0x01 Number of NID entries in connection list. Table 248. MonoOutPin ConnLst Command Verb Format Table 249. MonoOutPin ConnLst Command Response Format [31.:24] Entry3 R 0x00 Unused list entry. [23.:16] Entry2 R 0x00 Unused list entry. [15.:8] Entry1 R 0x00 Unused list entry. [7.:0] Entry0 R 0x13 MonoOut Mix widget. Table 250. MonoOutPin Ctl Command Verb Format
Table 251. MonoOutPin Ctl Command Response Format Table 252. MonoOutPin Config Command Verb Format Table 253. MonoOutPin Config Command Response Format [31.:30] Port RW 0x1 External Port Connectivity of the Pin Complex. [23.:20] Device RW 0x1 Default Device, indicating intended use of jack. [11.:8] Misc RW 0x0 Misc[0] = Jack Detect override.
Default Association for Pin Complex groups. Reserved value 0000b should not be used. Value 1111b indicates lowest priority. Table 254. CDPin WCap Command Verb Format Table 255. CDPin WCap Command Response Format
parameters from Audio Function node instead. Table 256. CDPin Cap Command Verb Format Table 257. CDPin Cap Command Response Format [6] BalancedIO R 0x0 Pin complex does not have balanced pins. [5] InCap R 0x1 Pin complex is input capable. [4] OutCap R 0x0 Pin complex is not output capable. [3] HPhnDrvCap R 0x0 Pin does not have a headphone amplifier. [2] PresDtctCap R 0x0 Pin complex cannot perform Presence Detect.
Table 258. CDPin Ctl Command Verb Format Table 259. CDPin Ctl Command Response Format Table 260. CDPin Config Command Verb Format Table 261. CDPin Config Command Response Format [31.:30] Port RW 0x2 External Port Connectivity of the Pin Complex. [23.:20] Device RW 0x3 Default Device, indicating intended use of jack.
[11.:8] Misc RW 0x0 Misc[0] = Jack Detect override. Default Association for Pin Complex groups. Reserved value 0000b should not be used. Value 1111b indicates lowest priority. Table 262. MonoOutMix WCap Command Verb Format Table 263. MonoOutMix WCap Command Response Format
[6] ProcWidget R 0x0 No Processing Controls parameter. Table 264. MonoOutMix ConnLen Command Verb Format Table 265. MonoOutMix ConnLen Command Response Format [31.:8] Rsvd R 0x0 Reserved. [6.:0] N R 0x01 Number of NID entries in connection list. Table 266. MonoOutMix ConnLst Command Verb Format
Table 267. MonoOutMix ConnLst Command Response Format [31.:24] Entry3 R 0x00 Unused list entry. [23.:16] Entry2 R 0x00 Unused list entry. [15.:8] Entry1 R 0x00 Unused list entry. [7.:0] Entry0 R 0x07 DAC Mux widget. Table 268. PCBeep Vol Command Verb Format Table 269. PCBeep Vol Command Response Format Table 270. PCBeep WCap Command Verb Format
Table 271. PCBeep WCap Command Response Format Table 272. PCBeep OutAmpCap Command Verb Format Table 273. PCBeep OutAmpCap Command Response Format
Table 274. PCBeep Gen Command Verb Format Table 275. PCBeep Gen Command Response Format Enable internal PC-Beep generation.
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 116 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL 6. ORDERING INFORMATION 6.1. STAC9200 Family Options and Part Order Numbers The +4V Analog voltage is supported by the +5 V version of the STAC9200 or STAC9200D. *Dolby requires the 5 V version of this part except for Dolby Digital Live (DDL). NOTE: When ordering these pa rts the “yy” will be replaced with the CODEC revision. Add an “R” to the end of any of these part numbers for delivery on Tape and Reel. The minimum order quantity for Tape and Reel is 2,000 units for both package options. Part Order Number Voltage DAC SNR Dolby* Pkg Pins STAC9200D5TAEyy 5 V 100dB Yes 48 LQFP STAC9200D5NAEyy 5 V 100dB Yes 32 QFN STAC9200X5TAEyy 5 V 100dB No 48 LQFP STAC9200X5NAEyy 5 V 100dB No 32 QFN STAC9200D3TAEyy 3.3 V 100dB Yes (DDL) 48 LQFP STAC9200D3NAEyy 3.3 V 100dB Yes (DDL) 32 QFN STAC9200X3TAEyy 3.3 V 100dB No 48 LQFP STAC9200X3NAEyy 3.3 V 100dB No 32 QFN
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 117 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL 7. PIN INFORMATION 7.1. Pin Out 32 pad QFN28HP_R 27HP_L 26AVDD2 25MONO_OUT 29AVSS 30GPIO2 32SPDIF_OUT SPDIF_IN/EAPD/GPIO3 4DVSS2 3BIT_CLK 2SDATA_OUT 1N.C. 5SDATA_IN 6DVDD 8RESET# SYNC
13 MIC 1
14 MIC 2
15 LINE_IN_L
16 LINE_IN_R
12 CD_R
11 N.C.
9 SENSE_A
CD_L
21 GPIO0
22 GPIO1
23 LINE_OUT_L
24 LINE_OUT_R
20 CAP2
19 VREF_OUT
17 AVSS1
VREF_IN 48 pin LQFP
21 MIC_L
22 MIC_R
23 LINE_IN_L
24 LINE_IN_R
20 CD_R
19 N.C.
18 CD_L
17 N.C. 16 N.C. 15 N.C. 14 N.C.
13 SENSE_A
33 GPIO0
34 GPIO1
35 LINE_OUT_L
36 LINE_OUT_R
32 CAP2
31 N.C. 30 N.C. 29 N.C.
28 VREF_OUT
27 VREF_IN
26 AVSS1
25 N.C. 40N.C. 39HP_OUT_L 38AVDD2 37MONO_OUT 41HP_OUT_R 42AVSS2 43N.C. 44N.C. 45GPIO2 46N.C. 47SPDIF_IN/EAPD/GPIO3 48SPDIF_OUT 4N.C. 3N.C. 2N.C. 1N.C. 5SDATA_OUT 6BIT_CLK 7DVSS 8SDATA_IN 9DVDD 10SYNC 11RESET# 12PC BEEP N.C. = No Connect
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 118 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL 7.2. Pin Table for 48-pin LQ FP and 32-pad QFN Packages Pin Name Pin Function I/O Internal Pull-up/ Pull-down LQFP 48-pin Location QFN 32-pin Location NC No Connect - - 1 - NC No Connect - - 2 1 NC No Connect - - 3 - NC No Connect - - 4 - SDATA_OUT High Definition Audio “Azalia” Serial Data output (inbound stream) I/O (Digital) None 5 2 BIT_CLK High Definition Audio “Azalia” Bit Clock I(Digital) Pull-down 6 3 DVSS Digital Ground I(Digital) None 7 4 SDATA_IN High Definition Audio “Azalia” Serial Data input (outbound stream) O(Digital) Pull-down 8 5 DVDD_CORE3 Digital Vdd = 3.3 V I(Digital) None 9 6 SYNC High Definition Audio “Azalia”Frame Sync I(Digital) Pull-down 10 7 RESET# High Definition Audio “Aza lia” Reset I(Digital) Pull-down 11 8 PC Beep PC Beep I(Analog) - 12 - Sense A Jack insertion detection Ports A, B, C, D I(Analog) None 13 9 NC No Connect - - 14 - NC No Connect - - 15 - NC No Connect - - 16 - NC No Connect - - 17 - CD-L CD Audio Left Channel I(Analog) None 18 10 NC No Connect - - 19 11 CD-R CD Audio Right Channel I(Analog) None 20 12 Port B-L Analog I/O I/O(Analog) None 21 13 Port B-R Analog I/O I/O(Analog) None 22 14 Port C-L Analog I/O I/O(Analog) None 23 15 Port C-R Analog I/O I/O(Analog) None 24 16 NC No Connect - - 25 - AVSS1 Analog Ground I(Analog) None 26 17 VREF IN Reference Voltage In drive I(Analog) None 27 18 VREFOUT Reference Voltage Out drive O(Analog) None 28 19 NC No Connect - - 29 - NC No Connect - - 30 - NC No Connect - - 31 - CAP2 ADC reference Cap O(Analog) None 32 20
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 119 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL * GPIO Pins can also be used for Microphone Bias. GPIO0* General Purpose I/O/Mic Bias I/O(Analog) Pull-up 50 K Ω 33 21 GPIO1* General Purpose I/O/Mic Bias I/O(Analog) Pull-up 50 K Ω 34 22 Port D-L Analog I/O with HP support I/O(Analog) None 35 23 Port D-R Analog I/O with HP support I/O(Analog) None 36 24 MONO Mono Out from DAC O(Analog) None 37 25 AVDD2 Analog Vdd = 5.0 V or 3.3 V I(Analog) None 38 26 Port A-L Analog I/O with HP support I/O(Analog) None 39 27 NC No Connect - - 40 - Port A-R Analog I/O with HP support I/O(Analog) None 41 28 AVSS2 Analog Ground I(Analog) None 42 29 NC No Connect - - 43 - NC No Connect - - 44 - GPIO2* General Purpose I/O /Mic Bias I/O(Digital) Pull-up 50 K Ω 45 30 NC No Connect - - 46 - S/PDIFIN/EAPD/ GPIO3* SPDIF Input, External Amplifier Power Down, General Purpose I/O /Mic Bias I/O(Digital) None 47 31 S/PDIF-OUT SPDIF digital output (50 KΩ internal pull-down) O(Digital) 50 KΩ internal pull-down 48 32 Pin Name Pin Function I/O Internal Pull-up/ Pull-down LQFP 48-pin Location QFN 32-pin Location
Figure 3. 32-Pad QFN Package Outline and Package Dimensions NOTE: For more information on the QFN please see IDT QFN Application Note.
Figure 4. 48-Pin LQFP Package Outline and Package Dimensions
Note: These devices can be hand soldered at 360 oC for 3 to 5 seconds. Mount Devices” (www.jedec.org/download). Figure 5. Solder Reflow Profile Note: All temperatures refer to topside of the package, measured on the package body surface.
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 123 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL 9.2. Pb Free Process - Package Classi fication Reflow Temperatures Package Type MSL Reflow Temperature LQFP 48-pin 3 260 oC* QFN 32-pad 3 260 oC*
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 124 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL 10.REVISION HISTORY Revision Date Description of Change For STAC9200/9200D Revision CA1 0.5 September 2004 Initial release.
0.6 November 2004 Updated the Connection Diagrams
0.7 November 2004 Added Widget Tables
0.8 December 2004 Added 5V Analog Performance Characteristics Table
FOR STAC9200/9200D Revision CB1 0.9 January 2005 Updated LQFP Package Drawing. Updated QFN Drawing. Updated Reflow profile information. Updated Widget Information- This is for the B1 revision of STAC9200/9200D. 0.91 February 2005 Added Ordering Information. Updated Reflow profile.
0.92 April 2005
Added Dolby part numbers, description and differences section, Added 5V Analog Performance Numbers with note about min/max, Added Power Consumption, Added 4V Analog supply information, Added comment for allowing GPIO to be used as microphone bias
0.93 July 2005
Added in 3.3V Analog performance numbers. Added in 4V performance numbers. Replaced reflow profile- this was only for visual purposes. No changes were made to the Data.
1.0 Updated logo
1.1 Removed “Preliminary”. Added Section 7.4 “Audio Jack Presence Detect.”
1.2 June 2006 Updated 32-pad Package Drawing
1.3 10 October 2006 Released in IDT format.
1.4 December 2006 Updated AIDD Max spec
1.5 April 2007 Corrected 32QFN diagram, removed typical connection diagrams as the reference design should be used instead. Updated table of contents, list of tables and figures.
2-CHANNEL HIGH DEFINITION AUDIO CODEC PC AUDIO IDT™ 2-CHANNEL HIGH DEFINITION AUDIO CODEC 125 STAC9200/9200D V 1.4 12/06 IDT CONFIDENTIAL
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