STA8135G STMICROELECTRONICS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 41

Technical content

Datasheet sections

  • 1 Overview
  • 2 Block diagram and pin description
  • 2.1 Block diagram
  • 2.2 Package
  • 2.3 Ball list
  • 3 General description
  • 3.1 Multi-constellation and multi-band
  • 3.2 RF front end (G5RF)
  • 3.3 Multi-band multi-constellation base band (G5BB) processor
  • 3.4 L-band reception path
  • 3.5 MCU sub system
  • 3.5.1 Caches
  • 3.5.2 TCM
  • 3.5.3 Nested vector interrupt controller (NVIC)
  • 3.5.4 AXI bus
  • 3.6 APB peripherals
  • 3.6.1 APB bridge 2 peripherals
  • 3.6.2 APB bridge 1 peripherals
  • 3.6.3 APB bridge 0 peripherals
  • 3.6.4 AHB slave devices
  • 3.8 Serial flash memory controller (SFC)
  • 3.9 SSP
  • 3.10 UART
  • 3.11 Watchdog timer (WDT)
  • 3.12 GPIO
  • 3.13 Multi timer unit (MTU)
  • 3.13.1 MTU feature overview
  • 3.14 RTC
  • 3.15 MSP
  • 3.16 Direct memory access (DMA)
  • 3.17 Temperature sensor
  • 3.18 Serial boot pins
  • 3.19 Reset
  • 3.20 CAN interface

Features

  • STMicroelectronics 5th generation positioning receiver with 80 tracking channels and 4 fast acquisition channels compatible with 6 constellations: GPS, Galileo, GLONASS, BeiDou, QZSS, NAVIC (former IRNSS)
  • Triple band L1, L2, L5, E6 and L-band single package solution
  • SBAS systems: WAAS, EGNOS, MSAS, GAGAN, BeiDou
  • Code phase, carrier phase, doppler frequency measurement
  • Antenna sensing
  • PPS output
  • Notch filter for anti-jamming
  • ARM® Cortex® M7 core: – Maximum clock frequency 314 MHz – 16 kB I-cache and 16 kB D-cache – 64 kB I-TCM and 384 kB D-TCM, core clock speed – Nested vector interrupt controller – JTAG debugging capability – 256 Kbyte system RAM
  • 32-channel DMA
  • Memory interfaces: – SFC (Octal/Quad serial flash controller, SDR) – SD multimedia card
  • Serial interfaces: – 3 x UART – Synchronous serial port (SPI supported) – I2C – 2x multimode serial interfaces – 2x CAN controllers
  • Core peripherals: – 2x multi-timer units – Watchdog timer – 1x extended function timers – 32 kHz oscillator real-time clock – AES decipher hardware accelerator
  • Power management unit, with separate power supply domain and on-chip LDO and high voltage/low voltage monitors: – Backup voltage domain 1.62 to 3.6 V with LDO for always-on core supply and HV/LV detectors, and dedicated IO-ring0 – Main voltage domain 1.62 to 3.6 V with LDO for switchable logic domain and HV/LV detectors for 85 °C maximum ambient temperature operations – Separate RF domain with dedicated LDO – IO-ring1 1.8 or 3.3 V capable, and dedicated 1.8 V LDO – IO-ring2 3.3 V ±10% capable – Fail-safe GPIOs available TFBGA160 7x11x1.2 mm 0.65 mm ball pitch Product status link STA8135G Product summary Order code STA8135GTR Temperature range -40 °C to +85 °C Package TFBGA160 7x11x1.2 mm Packing Tray, Tape and reel Teseo V family industrial triple-band multi-constellation GNSS precise engine receiver STA8135G Datasheet DS14788 - Rev 1 - March 2025 For further information, contact your local STMicroelectronics sales office.
  • Secure-digital multimedia memory card interfaces (SDMMC)
  • USB 2.0 full speed (12 Mb/s) with integrated physical layer transceiver
  • ESD: 2 kV (HBM) and 500 V (CDM)

Description

The STA8135G is part of the Teseo V family and it is a multi-band multi-constellation positioning receiver IC able to manage all the GNSS constellations such as GPS, Galileo, GLONASS, BeiDou, NAVIC (former IRNSS) and QZSS, in L1, L2, L5, and E6 frequency bands. STA8135G DS14788 - Rev 1 page 2/41

1 Overview

The STA8135G is part of the Teseo V family: it is a MultiChipModule (MCM) combining both STA8100GA and STA5635A in a single package. It is a multi-band multi-constellation positioning receiver IC able to manage all the GNSS constellations such as GPS, Galileo, GLONASS, BeiDou, NAVIC (former IRNSS) and QZSS, in L1, L2, L5, and E6 frequency bands. The STA8135G is able to manage most of the GNSS bands (L1, L2, L5, E6) allowing even to receive simultaneously three frequencies L1/L2/L5 or L1/L5/E6 in a single package without the need of any external RF front-end. The STA5635A integrated RF front-end supports L-band corrections signal reception. It provides the precise raw measurements of all the visible GNSS satellites to the main host via serial interface to let any possible precise position algorithm run. STA8135G also provides an autonomous precision positioning calculation to the main host using all the satellites constellations. It embeds separated LDOs to supply the analog parts, the digital core, and the IO ring of the device facilitating requirements to external power supply. The chip is manufactured in CMOS technology and housed in a TFBGA package 160 balls 7x11 mm body size 0.65 mm pitch. STA8135G Overview DS14788 - Rev 1 page 3/41

2 Block diagram and pin description

2.1 Block diagram

Figure 1. STA8135G block diagram

2.2 Package

TFBGA160 balls with 7x11x1.2 mm body size and 0.65 mm ball pitch.

2.3 Ball list

Note: All balls have alternate functionalities, which can be selected by relevant registers. Table 1. Power supply pins

  1. Backup power shall be applied at the same time or before VCORE_IN, not after.
  2. Pins names with trailing _0 are related to RF chip.

Table 2. Main function pins an external power through VDD_EXT_REG balls.

  1. In standby mode , if VIO1 and VIO2 are powered, GPIOs have no driving capabilities and no PD/PU is active.
  2. If VCORE_IN is removed before STANDBY_IN has switched from high to low, STANDBY_OUT remains high level, even if

device enters in standby mode.

Table 3. RF front-end pins Table 4. RF chip reserved Table 5. Communication interface pins

Symbol I/O voltage(1) I/O AF Function Description Ball Reset GPIO32 IO ring 2 (FS) O ALT A - - - O ALT B UART0_TX UART0 transmitter - O ALT C PPS_OUT Pulse per second output - MSP1_clk_out IO ring 1 (FS) I/O Default GPIO 91 - PD O ALT A MSP1_clk_out MSP1 master clock - I ALT B SPI_CLK SPI clock - O ALT C CLK_OUT Clock output - MSP1_CS IO ring 1 (FS) I/O Default GPIO 90 - PD I/O ALT A MSP1_CS MSP1 master chip select - I ALT B SPI_CSn SPI chip select - I ALT C UART2_RX UART2 receiver - MSP1_Din IO ring 1 (FS) I/O Default GPIO 94 - PD I ALT A MSP1_Din MSP1 data input - I ALT B SPI_SI SPI chip select - O ALT C OCTOSPI_CLKn Octo SPI clock inverted - MSP1_Dout IO ring 1 (FS) I/O Default GPIO 95 - PD O ALT A MSP1_Dout MSP1 data output - O ALT B SPI_SO SPI data output - O ALT C UART2_TX UART2 transmitter - JTAG-TRSTn IO ring 2 (FS) I/O Default JTAG-TRSTn/GPIO 0 JTAG reset PD O ALT A PPS_OUT Pulse per second output - I ALT B - - - I ALT C Timer_OCMPA Timer A input - JTAG-TCK IO ring 2 (FS) I/O Default JTAG-TCK/GPIO 1 JTAG clock PD I ALT A SPI_CK SPI slave clock - O ALT B MSP0_clk_out MSP0 master clock - I ALT C Timer_ICAPA1 Timer A input - JTAG-TMS IO ring 2 (FS) I/O Default JTAG-TMS/GPIO 2 JTAG TMS PU I ALT A SPI_CS SPI slave chip select - O ALT B MSP0_Din MSP0 data input - O ALT C UART0_RTS UART0 RTS - JTAG-TDI IO ring 2 (FS) I/O Default JTAG-TDI/GPIO 3 JTAG data input PU I ALT A SPI_SI SPI data input - I/O ALT B MSP0_Dout MSP0 data output - O ALT C UART0_CTS UART0 CTS - JTAG-TDO IO ring 2 (FS) I/O Default JTAG-TDO/GPIO 4 JTAG data output PD O ALT A SPI_SO SPI data output - O ALT B MSP0_CS MSP0 chip select - I ALT C PPS_IN PPS input - UART1_RX IO ring 2 I/O Default USB_DM USB minus PD I ALT A UART1_RX UART1 receiver - STA8135G Block diagram and pin description DS14788 - Rev 1 page 7/41

Symbol I/O voltage(1) I/O AF Function Description Ball Reset UART1_RX IO ring 2 I/O ALT B I2C_SDA I2C data - I ALT C CAN1_RX CAN1 receiver - UART1_TX IO ring 2 I/O Default USB_DP USB positive PD O ALT A UART1_TX UART1 transmitter - I/O ALT B I2C_CLK I2C clock - O ALT C CAN1_TX CAN1 transmitter - UART2_RX IO ring 2 (FS) I/O Default GPIO 89 - PD I ALT A UART2_RX UART2 receiver - I/O ALT B - - - O ALT C - - - UART2_TX IO ring 2 (FS) I/O Default GPIO 88 - PD O ALT A UART2_TX UART2 transmitter - I/O ALT B - - - O ALT C - - - GPIO67 IO ring 2 I/O Default GPIO 67 - PD O ALT A - - - I/O ALT B UART0_RX UART0 receiver - I ALT C PPS_IN Pulse per second input - GPIO8 IO ring 2 I/O Default GPIO 8 - PD I ALT A MII_TX_EN - - O ALT B i_g5rf_MONITOR_LDO_sig - - O ALT C I_sign2 - - GPIO7 IO ring 2 I/O Default GPIO 7 - PD O ALT A MII_TX_CLK - - O ALT B i_g5rf_MONITOR_PLL_sig - - O ALT C I_sign - - GPIO43 IO ring 2 I/O Default GPIO 43 - PD O ALT A Timer_ICAPA - - - ALT B - - - - ALT C - - - GPIO92 IO ring 2 I/O Default GPIO 92 - F10 PD I ALT A MSP1_clk_in - - - ALT B - - - - ALT C - - - GPIO77 IO ring 2 I/O Default GPIO 77 - PD I ALT A CAN1_RX - - - ALT B MII_PTP_AUX_TS_TRIG0 - - - ALT C - - - GPIO48 IO ring 2 I/O Default GPIO 48 - PD O ALT A MSP0_clk_out - - - ALT B - - - STA8135G Block diagram and pin description DS14788 - Rev 1 page 8/41

Symbol I/O voltage(1) I/O AF Function Description Ball Reset GPIO48 IO ring 2 - F7ALT C - - - GPIO76 IO ring 2 I/O Default GPIO 76 - PD O ALT A CAN1_TX - - - ALT B MII_MDC_O - - - ALT C - - - GPIO47 IO ring 2 I/O Default GPIO 47 - PD O ALT A MSP0_CS - - - ALT B - - - - ALT C - - - GPIO51 IO ring 2 I/O Default GPIO 51 - PD I ALT A MSP0_Din - - - ALT B - - - - ALT C - - - GPIO52 IO ring 2 I/O Default GPIO 52 - PD O ALT A MSP0_Dout - - - ALT B - - - - ALT C - - - GPIO86 IO ring 2 I/O Default GPIO 86 - PD O ALT A UART1_TX UART1 transmitter - - ALT B - - - - ALT C - - - GPIO87 IO ring 2 I/O Default GPIO 87 - PD I ALT A UART1_RX UART1 receiver - - ALT B MII_PTP_AUX_TS_TRIG1 - - - ALT C - - - GPIO78 IO ring 2 I/O Default GPIO 78 - PD O ALT A MMC_CLK - - I ALT B TCXO_CLK - - O ALT C CLK_64_FO - - GPIO50 IO ring 2 I/O Default GPIO 50 - PD O ALT A MSP0_L/R - - - ALT B - - - - ALT C - - - GPIO37 IO ring 2 I/O Default GPIO 37 - PD I ALT A UART0_RX UART0 receiver - - ALT B - - - - ALT C - - - GPIO42 IO ring 2 I/O Default GPIO 42 - PD - ALT A - - - - ALT B - - - - ALT C - - - STA8135G Block diagram and pin description DS14788 - Rev 1 page 9/41

Symbol I/O voltage(1) I/O AF Function Description Ball Reset GPIO38 IO ring 2 I/O Default GPIO 38 - PD O ALT A UART0_TX UART0 transmitter - - ALT B - - - - ALT C - - - GPIO44 IO ring 2 I/O Default GPIO 44 - PD O ALT A Timer_OCMPA - - - ALT B - - - - ALT C - - - GPIO49 IO ring 2 I/O Default GPIO 49 - PD O ALT A MSP0_clk_in - - - ALT B - - - - ALT C - - - GPIO23 IO ring 2 I/O Default GPIO 23 - PD O ALT A SFC_SIO1 - - - ALT B - - - I/O ALT C OCTOSPI_SIO1 - - GPIO24 IO ring 2 I/O Default GPIO 24 - PD O ALT A SFC_SIO2 - - - ALT B GPIO 24 - - I/O ALT C OCTOSPI_SIO2 - - GPIO26 IO ring 2 I/O Default GPIO 26 - PD O ALT A SFC_SIO4 - - - ALT B MMC_CLK - - I/O ALT C OCTOSPI_SIO4 - - GPIO27 IO ring 2 I/O Default GPIO 27 - PD O ALT A SFC_SIO5 - - - ALT B MMC CMD - - I/O ALT C OCTOSPI_SIO5 - - GPIO22 IO ring 2 I/O Default GPIO 22 - PD O ALT A SFC_SIO0 - - - ALT B - - - - ALT C OCTOSPI_SIO0 - - GPIO25 IO ring 2 I/O Default GPIO 25 - PD O ALT A SFC_SIO3 - - - ALT B - - - I/O ALT C OCTOSPI_SIO3 - - GPIO61 IO ring 2 I/O Default GPIO 61 - PD O ALT A SFC_CSN - - - ALT B - - - O ALT C OCTOSPI_RWDS - - GPIO62 IO ring 2 I/O Default GPIO 62 - T1 PD STA8135G Block diagram and pin description DS14788 - Rev 1 page 10/41

Table 6. RF chip SPI interface Table 7. Reserved

Table 8. ADC

3 General description

3.1 Multi-constellation and multi-band

  • GPS (L1 C/A, L2C, and L5)
  • GLONASS (L1OF, L2OF)
  • BeiDou (B1C, B1I, B2a, B2I)
  • GALILEO (E1, E5a, E5b, E6)
  • QZSS (L1 C/A, L2C, L5)
  • NAVIC - former IRNSS (L5) Carrier phase raw measurements are also provided. STA8135G supports a wide range of combinations of such signals and bands without the need of external RF front end. The most important GNSS user cases that can be supported by STA8135G are listed in the below table. Each of those cases would require a dedicated firmware.

Table 9. GNSS user cases Note: Maximum 80 satellites tracked simultaneously.

3.2 RF front end (G5RF)

flexible RF-IF chain driven by a fractional PLL. MAG0) bit. The MAG bit is internally integrated in order to control the variable gain amplifiers.

3.3 Multi-band multi-constellation base band (G5BB) processor

NAVIC (former IRNSS) and QZSS systems.

3.4 L-band reception path

The STA8135G can manage L-band signals for correction service through the integrated STA5635.

demodulation and signal processing. Figure 2. RF chip DDC block diagram

3.5 MCU sub system

through the AXI, AHB and APB interconnections present in the SOC.

3.5.1 Caches

The size of instruction and data cache used for ARM® sub-system in STA8135G is 16 KB each.

3.5.2 TCM

KB ITCM memory and 384 KB of DTCM memory. the ARM® sub-system and the G5BB module. the AMBA infrastructure in STA8135G so that DMA present on the bus can access the TCM memories MCU.

3.5.3 Nested vector interrupt controller (NVIC)

3.5.4 AXI bus

3.6 APB peripherals

3.6.1 APB bridge 2 peripherals

be accessed by AHB masters connected to AHB bus matrix 0. The peripherals connected to APB 2 are: UART2, MSP1, GPIO PORT 2, MTU1.

3.6.2 APB bridge 1 peripherals

accessed by AHB masters connected to AHB bus matrix0.

3.6.3 APB bridge 0 peripherals

accessed by AHB masters connected to AHB bus matrix0. The peripherals connected to APB 0 are the ones on the always on domain: PRCC always ON, RTC.

3.6.4 AHB slave devices

There are some AHB slave devices which are connected to AHB bus matrix 0. 256 KB of embedded RAM are available on top of the TCM RAM. The eSRAM is directly connected to the MCU through the AXI bus. It can be used for data and instruction.

3.8 Serial flash memory controller (SFC)

execution thanks to direct memory mapping. Table 10. SQI memory interface (power fail-safe IOs)

Symbol I/O voltage I/O Description Ball Reset state SFC_SIO5 IO ring1 I/O Serial flash memory controller data IO 5 M2 Hi-Z/PD SFC_SIO6 IO ring1 I/O Serial flash memory controller data IO 6 T4 Hi-Z/PD SFC_SIO7 IO ring1 I/O Serial flash memory controller data IO 7 P1 Hi-Z/PD Note: These interface IOs are alternate functions A of GPIOs.

3.9 SSP

STA8135G has one synchronous serial ports (SSPs). The SSP is a master or slave interface that enables synchronous serial communication with slave or master peripherals having one of the following:

  • Serial peripheral interface bus standards
  • Synchronous serial protocol bus standards
  • Micro-wire interface bus standards
  • Unidirectional interface In both master and slave configurations, the SSP has the following features:
  • Parallel-to-serial conversion on data written to an internal 32-bit wide, 32-location deep transmit FIFO
  • Serial-to-parallel conversion on received data, buffering it in a 32-bit wide, 32-location deep receive FIFO
  • Programmable data frame size from 4 to 32 bits
  • Programmable clock bit rate and pre-scaler
  • Programmable clock phase and polarity in SPI mode
  • Support for direct memory access (DMA)

3.10 UART

The UARTx performs serial-to-parallel conversion on data asynchronously received from a peripheral device on UARTx_RX pin, and parallel-to-serial conversion on data written by CPU for transmission on UARTx_TX pin. The transmit and receive paths are buffered with internal FIFO memories allowing up to 64 data byte for transmission, and 64 data byte with 4-bit status (break, frame, parity, and overrun) to receive. FIFOs may be burst-loaded or emptied by the system processor or DMA, from one to sixteen words per transfer.

3.11 Watchdog timer (WDT)

Watchdog timer (WDT) provides a way of recovering from software crashes. The watchdog clock is used to generate a regular interrupt (Irq_wdt), depending on a programmed value. The watchdog monitors the interrupt and asserts a reset signal (WDOGRES) if the interrupt remains unserviced for the entire programmed period. The WDT is counting down at a fixed frequency of 32.768 kHz. The watchdog timer peripheral can be used as free-running timer or as watchdog to resolve processor malfunctions due to hardware or software failures. Feature set overview:

  • 16-bit down counter
  • 8-bit clock pre-scaler
  • Safe reload sequence
  • Free-running timer mode
  • End of counting interrupt generation STA8135G General description DS14788 - Rev 1 page 16/41

3.12 GPIO

There are 34 GPIOs in this device. The GPIO block provides programmable inputs or outputs. Each input or output can be controlled in two modes:

  • Software mode through an APB bus interface
  • Alternate function mode, where GPIO becomes a peripheral input or output line Any GPIO input can be independently enabled or disabled (masked) for interrupt generation. User can select for each GPIO which edge (rising, falling, both) will trigger an interrupt. A de-bouncing logic can be enabled for each GPIO to filter glitches on IOs before going to the Interrupt generation and CPU read value. All GPIOs are fail safe to avoid leakage consumption in any condition even when the ring is off and the external line is logic level high.

3.13 Multi timer unit (MTU)

Multi timer unit consists of eight timers. Each timer is clocked by MXTAL frequency divided by 8 (which means 2.4 MHz with a 19.2 MHz crystal) or REFCLK (32.768 kHz) inputs.

3.13.1 MTU feature overview

  • The Multi timer unit provides access to four interrupt generating programmable 32-bit free-running decrementing counters (FRCs) allowing up to four counts to be performed in parallel.
  • The FRCs have their own clock input, allowing the counters to run from a much slower clock than the system clock.
  • In each FRC the 32-bit counter is split up into two 16-bit counters.

3.14 RTC

This is an always-on power domain dedicated to RTC logic (backup system) with 256 bytes SRAM and supplied with a dedicated voltage regulator. The RTC provides a high resolution clock which can be used for GPS. It keeps the time when the system is inactive and can be used to wake up the system when a programmed alarm time is reached. It has a clock trimming feature to compensate for the accuracy of the 32.768 kHz crystal and a secured time update. RTC features:

  • 47-bit counter clocked by 32.768 kHz clock
  • 32-bit for the integer part (seconds) and 15-bit for the fractional part
  • The integer part and the fractional part are readable independently
  • The counter, once enabled, can be stopped
  • Integer part load register (32-bit)
  • Fractional part load register (15-bit)
  • Load bit to transfer the content of the entire load register (integer + fractional part) to the 47-bit counter Once set by the MCU this bit is cleared by the hardware to signal to the MCU that the RTC has been updated.

3.15 MSP

STA8135G has one multi mode serial port (MSP). The following section describes the functionalities of the MSP unit. The multi mode serial port (MSP) is a synchronous transmitter serial interface. The MSP provides:

  • Element (data) sizes of 8, 10, 12, 14, 16, 20, 24, and 32 bits, LSB or MSB first
  • Programmable frequency shift clock for data transfer
  • Direct interface to SPI compliant devices
  • Transmit first-in, first-out memory buffers (FIFOs), 32 bits wide, 8 locations deep STA8135G General description DS14788 - Rev 1 page 17/41

3.16 Direct memory access (DMA)

peripheral. The DMAC is an AMBA AHB module, and connects to the advanced high-performance bus (AHB).

  • Eight DMA channels. Each channel can support an unidirectional transfer.
  • The DMAC provides 32 peripheral DMA request lines.
  • Single DMA and burst DMA request signals.
  • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers.
  • Scatter or gather DMA support through the use of linked lists.
  • Hardware DMA channel priority. DMA channel 0 has the highest priority and channel 31 has the lowest priority.
  • If requests from two channels become active at the same time, the channel with the highest priority is serviced first.
  • AHB slave DMA programming interface to the DMA control registers.
  • Two AHB bus masters for transferring data.
  • Programmable DMA burst size.
  • Working on AHB clock.

3.17 Temperature sensor

Temperature measurement range is -40 to 85 °C. It uses integrated bandgap reference and 8-bit ADC. threshold register or lower than the lower threshold register, it generates an interrupt if enabled. Table 11. Temperature sensor

  1. Best accuracy is at calibrated temperature.
  2. Limited by manufacturing calibration environment.

3.18 Serial boot pins

Table 12. Boot peripheral selection

3.19 Reset

After a reset, the Cortex® M7 is woken-up by the ROM code. fetch the first instruction of the user application code.

  • Pad reset: SoC will have active low chip reset (RESET) pad. Low (zero) status on this pad will keep device in the reset. Assertion of this pin low should be minimum of 5 ms. STA8135G General description DS14788 - Rev 1 page 18/41
  • Power on reset: the power on reset circuitry is embedded in the main voltage regulator built on HV supply (VCORE_IN) of the regulator. It ensures all voltage monitors are under reset state until the VCORE_IN (or VDD_EXT_REG) minimum voltage is reached.
  • Hardware resets: the internal voltage regulator embeds multiple LVD (low voltage detector) and HVD (high voltage detector) which are used in the reset sequence.
  • Soft reset: different peripherals present on STA8135G can be reset independently through the registers present inside the PRCC module.

3.20 CAN interface

CAN sub-system comprises two fully independent FD-CAN controllers: CAN0 and CAN1. Both controllers conform with CAN protocol version 2.0 part A, B and ISO 11898-1: 2015. Maximum data bit rate supported is 1 Mbit/s.

3.21 I2C high speed controller

One I2C high speed controller interface is capable of master/slave modes in multi-master environment. It is DMA capable and the multiple baud rates supported are: 100/400/1000/3400 Kbits/s. 3.22 Full speed USB 2.0 It supports 12 Mbps (full speed) and 1.5 Mbps (low speed) serial data transmission according to USB 2.0 OTG controller specification.

3.23 SDMMC (secure digital multi media card controller)

The SDMMC card host interface provides an interface between the APB peripheral bus and Multi Media cards (MMC), SD memory cards, SDIO cards, and CE-ATA devices. STA8135G General description DS14788 - Rev 1 page 19/41

4 Electrical specifications

4.1 Main chip

4.1.1 Absolute maximum ratings

Table 13. Absolute maximum ratings

  1. RFA_IN ESDCDMMax is ±50 V. LNA_IN ESDCDM Max is ±250 V.

4.1.2 Electrical characteristics

Table 14. Operating junction temperature range Table 15. VDD_EXT_REG - external core power supply Table 16. Backup PMU - Functional specifications

  1. Specified by design, not tested in production.

Table 17. Main PMU - Functional specifications

  1. Specified by design, not tested in production.

Table 18. Current consumption VCC_PLL connected to VRF_OUT on PCB.

  1. Maximum current at VCORE is limited by maximum junction temperature at 125 °C (which depends on application printed

Table 19. RF Electrical characteristics

  1. Specified by design, not tested in production.

Table 20. Electrical characteristics of digital input and output buffers

  1. Specified by design, not tested in production.

4.2 RF chip (integrated STA5635)

4.2.1 Parameter conditions

Unless otherwise specified, all voltages are referred to GND.

4.2.2 Minimum and maximum values

temperature, supply voltage and frequencies by tests in production on 100% of the devices. STA8135G parts are tested at T = -40 °C and T =85 °C.

4.2.3 Typical values

Table 21. Electrical characteristics (TJ = 25 °C unless otherwise noted)

  1. Specified by design, not tested in production.

4.3 Power management unit (PMU) - main chip

Table 22. LDO on-chip regulators Figure 3. LDO on-chip regulators dependencies

4.3.1 Power regions

  • Always on backup region: 1.2 V – prcc_backup – RTC – Backup RAM 256 bytes
  • Switchable region: 1.2 V – ARM® core – Other digital IPs
  • RF: 1.15 V
  • OTP: 2.5 V
  • IO ring1: 1.8 V or 3.3 V
  • IO ring2: 3.3 V IO ring1 is set at 1.8 V when supplied by the internal IO LDO. If a 3.3 V supply is applied at VIO1_EXT the IO ring1 is set at 3.3 V (bypassing the internal IO LDO). The switchable power region can be supplied by an external voltage regulator directly at pin VDD_EXT_REG. The integrated LDO CORE has to be switched off by forcing EXT_REG_SEL to high voltage. It is not possible to use the internal Core LDO at +85 °C ambient with application where 3.3 V is used as the input voltage of LDO Core (VCORE_IN).

4.4 Power management and start-up strategy RF chip

in order to delay the enable of the internal LDOs in respect to 3.3 V supply rise. Figure 4. Power configuration

Figure 5. Power-up strategy characteristics as per Table 23) as shown in the Figure 6. Table 23. Crystal recommended specifications

  1. Specified by design, not tested in production.

The following table provides the oscillator amplifier specifications. Table 24. Oscillator amplifier specifications

  1. Specified by design, not tested in production.

Figure 6. 32.768 kHz crystal connection

  • Disable the oscillator (bit28-OSCI_EN = 0b in PRCC_BACKUP_REG0 register). This disables the internal inverter, thus reducing the power consumption to minimum.
  • Drive the RTC_XTI pin with a square signal or a sine wave.

Table 25. Characteristics of external slow clock input

4.6 Power up timing sequence

Figure 7. Power up timing diagram Table 26. Power up timing data

  1. The simultaneous power-on of VBK_IN and VCORE_IN or VDD_EXT_REG is allowed and tested.
  2. The simultaneous power-on of VBK_IN and other supplies is allowed and tested

4.7 Digital interface AC timing characteristics

Figure 8. Clock block diagram

Table 27. Clock data

4.7.1 SQIO

Table 28. SQIOSDR mode (feedback mode) Note: Specified by design, not tested in production. Table 29. SQIODTR mode (DQS mode for flash memory read operations) Note: Specified by design, not tested in production.

4.7.2 SPI

Table 30. SPI (controller mode) Note: Specified by design, not tested in production.

4.7.3 MSP controller mode

Table 31. MSP0 controller mode Note: Specified by design, not tested in production. Table 32. MSP0 target mode Note: Specified by design, not tested in production. Table 33. MSP1 target mode Note: Specified by design, not tested in production.

4.7.4 JTAG

Table 34. JTAG characteristics

Type Symbol Min. Max. Unit Cload Notes Input TIH 5.5 - ns - - Output Todly -3 15 ns 25 pF - Note: Specified by design, not tested in production. STA8135G Electrical specifications DS14788 - Rev 1 page 32/41

5 Antenna sensing

voltage range must be between VRF_IN and GND. Figure 9. Antenna sensing configuration antenna, the antenna sensing block must be connected as illustrated in the above figure.

6 Package information

To meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions, and product status are available at: www.st.com. ECOPACK is an ST trademark. 6.1 TFBGA160 (7x11x1.2 mm) package information Figure 10. TFBGA160 (7x11x1.2 mm) package outline

Package information

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Table 35. TFBGA160 (7x11x1.2 mm) package mechanical data

  1. TFBGA stands for Thin Profile Fine Pitch Ball Grid Array.
  • Thin Profile: The total profile height (Dim A) is measured from the seating plane to the top of the component.
  • The maximum total package height is calculated by the following methodology: A Max. = A1 Typ + A3 Typ + A4 Typ + √ (A1²+A3²+A4² tolerance values).
  • Thin profile: 1.00 mm < A ≤ 1.20 mm / Fine pitch: e < 1.00 mm pitch. 2. The typical ball diameter before mounting is 0.35 mm. 3. The tolerance of position that controls the location of the pattern of balls with respect to datums A and B. For each ball there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. 4. The tolerance of position that controls the location of the balls within the matrix with respect to each other. For each ball there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is contained entirely in the respective zone eee above The axis of each ball must lie simultaneously in both tolerance zones. STA8135G

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Revision history

Table 36. Document revision history 03-Mar-2025 1 Initial release.

Contents

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