STA8100GA STMICROELECTRONICS | Alldatasheet

Document overview

  • Manufacturer or author: STMICROELECTRONICS
  • PDF pages: 42

Technical content

Datasheet sections

  • 1 Overview
  • 2 Pin description
  • 2.1 Block diagram
  • 2.2 Package
  • 2.3 Ball list
  • 3 General description
  • 3.1 Multi-constellation and multi-band
  • 3.2 RF front end (G5RF)
  • 3.3 Multi-band multi-constellat ion base band (G5BB) processor
  • 3.4 MCU sub system
  • 3.4.1 Caches
  • 3.4.2 TCM
  • 3.4.3 Nested Vector Interrupt Controller (NVIC)
  • 3.4.4 AXI bus
  • 3.5 APB peripherals
  • 3.5.1 APB bridge 2 peripheral s
  • 3.5.2 APB bridge 1 peripheral s
  • 3.5.3 APB bridge 0 peripheral s
  • 3.5.4 AHB slave devices
  • 3.7 Serial Flash Memory Controller (SFC)
  • 3.8 SSP
  • 3.9 UART
  • 3.10 Watchdog Timer (WDT)
  • 3.11 GPIO
  • 3.12 Multi Timer Unit (MTU)
  • 3.12.1 MTU feature overview
  • 3.13 RTC
  • 3.14 MSP
  • 3.15 Direct Memory Access (DMA)

Datasheet sections

  • 3.16 Antenna sensing
  • 3.17 Temperature sensor
  • 3.18 Serial boot pins
  • 3.19 Reset
  • 3.20 Power Management Unit (PMU)
  • 3.20.1 Power regions
  • 3.21 CAN interface
  • 3.22 I2C high speed controller
  • 4 Electrical specifications
  • 4.1 Absolute maximum ratings
  • 4.2 Thermal data
  • 4.3 Electrical characteristics
  • 4.5 Power up timing sequence
  • 4.6 Digital interface AC timing c haracteristics (specified by design)
  • 4.6.1 SQIO
  • 4.6.2 SPI
  • 4.6.3 MSP master mode
  • 4.6.4 JTAG
  • 4.6.5 USB - low speed and full speed mode
  • 5 Package information
  • 5.1 LFBGA81 package information
  • 6 Ordering information
  • 7 Revision history

Features

  • AEC-Q100 qualified
  • STMicroelectronics 5th generation positioning receiver with 80 tracking channels and 4 fast acquisition channels compatible with 6 constellations: GPS, Galileo, GLONASS, BeiDou, QZSS, NAVIC (former IRNSS)
  • Dual band L1 and L5 single chip solution
  • Triple band capability with external RF STA5635A
  • ST-DRAW (Dead Reckoning Automotive Way) is supported on STA8100GAD and STA8100GADS only
  • SBAS systems: WAAS, EGNOS, MSAS, GAGAN, BeiDou
  • Code phase, carrier phase, doppler frequency measurement
  • Antenna sensing
  • PPS output
  • Notch filter for anti-jamming
  • ARM ® Cortex® M7 core: – Maximum clock frequency 314 MHz – 16 KB I-cache and 16 KB D-cache – 64 KB I-TCM and 384 KB D-TCM, core clock speed – Nested vector interrupt controller – JTAG debugging capability – 256 Kbyte system RAM
  • Hardware Security Module (HSM) with HW cryptographic co-processor is enabled for STA8100GAS only
  • 32 channels DMA
  • Memory interfaces: – SFC (Octal/Quad serial flash controller, SDR) – SD multimedia card
  • Serial interfaces: –3 x U A R T – Synchronous serial port (SPI supported) – 2 x multi mode serial interfaces – 2 x CAN controllers
  • Core peripherals: – 2 x multi timer units – Watchdog timer – 1 x extended function timers – 32 kHz oscillator real time clock – AES decipher hardware accelerator
  • Power management unit, with separate power supply domain and on-chip LDO and high voltage/low voltage monitors: – Backup voltage domai n 1.7 to 3.6 V with LDO for always-on core supply and HV/LV detectors, and dedicated IO-ring0 – Main voltage domain 1.7 to 3.6 V with LDO for switchable logic domain and HV/LV detectors for 85 °C maximum ambient temperature operations or 1.2 V +/ - 5 % external voltage supply for 105 °C maximum ambient temperature operations – Separate RF domain with dedicated LDO

– IO-ring1 1.8 or 3.3 V capable, and dedicated 1.8 V LDO – IO-ring2 3.3 V +/ -10 % capable – Fail safe GPIOs available

  • USB2.0 full speed (12 Mb/s) with integrated physical layer transceiver
  • ESD: 2 kV (HBM) and 500 V (CDM)
  • Automotive grade 105 °C option

Description

STA8100GA is part of the Teseo V family. STA8100GA is a multi-band multi-constellation positioning receiver IC able to manage all the GNSS constellations such as GPS, Galileo, Glonass, BeiDou, NAVIC (former IRNSS) and QZSS, in L1, L2, L5 and E6 frequency bands. Security feature (enabled only for STA8100GAS) is implemented in a dedicated sub-system, embedding cryptographic HW accelerator with protected access. STA8100GAD and STA8100GADS are offered with STMicroelectronics dead reckoning firmware called TESEO-DRAW.

1 Overview

STA8100GA is part of the Teseo V family. STA8100GA is a multi-band multi-constellation positioning receiver IC able to manage all the GNSS constellations such as GPS, Galileo, Glonass, BeiDou, NAVIC (former IRNSS) and QZSS, in L1, L2, L5 and E6 frequency bands. STA8100GA is able to receive GPS, Galileo plus Beidou on L1 and L5 bands simultaneously without the need of an external RF front-end. A dedicated interface allows receiving GNSS data from the external RF front-end STA5635A in order to manage the other GNSS bands (L2, L5, E6 bands) simultaneously with the L1 band signals, allowing also a triple frequency mode L1/L2/L5 or L1/L5/E6. STA8100GA provides to the main host via serial interface the precise raw measurements of all the visible GNSS satellites to let run any possible precise position algorithm. STA8100GA provides also an autonomous precision positioning calculation to main host using all the satellites constellations. STA8100GA is compliant with ST Automotive Grade qualification which includes in addition to AEC-Q100 requirements a set of production flow methodologies targeting zero defect per million. STA8100GAD and STA8100GADS are offered with STMicroelectronics dead reckoning firmware called TESEO-DRAW. With the help of HSM, STA8100GAS supports a secure boot and secure firmware upgrade procedures which allow only properly signed binaries to run on STA8100GAS. STA8100GA is fulfilling high quality and service level requirements of the Automotive market, is the ideal solution for in-dash navigation, smart antenna, car to car, V2X, OEM telematics, marine, drone, lawnmower and many other applications requiring a precise position. STA8100GA embeds separated LDOs to supply, the analog parts, the digital core and the IO ring of the device facilitating requirements to external power supply. The chip is manufactured in CMOS technology and housed in a LFBGA package 81 balls 8x8 mm body size 0.8 mm pitch.

2 Pin description

2.1 Block diagram

Figure 1. STA8100GAS block diagram Note: (*) Security modu les are only available for STA8100GAS version.

2.2 Package

LFBGA 81 balls with 8 x 8 x 1.7 mm body size and 0.8 mm ball pitch.

2.3 Ball list

Note: Balls all have alternate fu nctionalities, which can be selected by relevant registers. Figure 2. Device ballout

Table 1. Power supply pins

  1. Refer to Section 4: Electrical specifications.
  2. Backup power shall be applied at the same time or before VCOR E_IN, not after.

Table 2. Main function pins by an external power source. the reference for real time clock counter circuitry. Standby_in pin. Wakeup from Standby mode.

  1. In Standby mode, if VIO1 and VIO2 are powered, GPIOs have no driving capabilities and no PD/PU is active.
  2. If VCORE_IN is removed before STANDBY_IN has switched from h igh to low, STANDBY_OUT remains high level, even if

device enters in Standby mode. Table 2. Main function pins (continued) Table 3. RF front-end pins Table 4. Memory interface (power fail safe IOs) Table 5. External RF interface (power fail safe IOs)

Table 5. External RF interface (power fail safe IOs) (continued) Table 6. Communication interface pins

Table 6. Communication interface pins (continued)

  1. JTAG pins can be configured a s GPIO in a dedicated alternate function mode as: TRSTn=GPIO0, TCK=GPIO1,

3 General description

3.1 Multi-constellati on and multi-band

  • GPS (L1 C/A, L2C, and L5)
  • GLONASS (L1OF, L2OF)
  • BeiDou (B1C, B1I, B2a, B2I)
  • GALILEO (E1, E5a, E5b, E6)
  • QZSS (L1 C/A, L2C, L5)
  • NAVIC - former IRNSS (L5) Carrier phase raw measurements are also provided. STA8100GA supports the simultaneous usage of all constellations in parallel on L1 band: GPS, GLONASS, GALILEO, BeiDou, and QZSS in addition to SBAS. STA8100GA also supports all the other bands in combination with the external STA5635A radio frequency front end. The most important GNSS user cases that can be supported by STA8100GA and STA5635A are listed in the below table. Each of those cases would require a dedicated firmware: Note: Maximum 64 satellites tracked simultaneously. I= Internal STA8100GA RF Section E= External STA5635A RF Receiver

Table 7. GNSS user cases

STA8100GA General description

3.2 RF front end (G5RF)

The integrated RF front-end is able to support different bands (L1, L2, L5, and E6) thanks to a programmable and flexible RF-IF chain driven by a fractional PLL. The RF_IF chain is followed by a 3-bit ADC able to convert the IF signal to Sign (SIGN) and Magnitude (MAG1, MAG0) bit. The MAG bit is internally integrated in order to control the variable gain amplifiers. The embedded fractional PLL allows supporting a wide range of reference clocks (10 to 55 MHz).

3.3 Multi-band multi-constella tion base band (G5BB) processor

STA8100GA integrates G5BB proprietary IP, which is the STMicroelectronics latest generation high-sensitivity baseband processor fully compliant with all different constellations and bands: GPS, Galileo, Glonass, BeiDou, NAVIC (former IRNSS) and QZSS systems.

3.4 MCU sub system

The Cortex® M7 core masters the system resources (memories, registers, and external memory controllers) through the AXI, AHB and APB interconnections present in the SOC.

3.4.1 Caches

The size of the instruction and data cache used for ARM® sub-system in STA8100GA is 16 KB each.

3.4.2 TCM

ARM® Cortex® M7 has a TCM Control Unit (TCU) with TCM interfaces and an AHB slave (AHBS) interface for system access to TCMs. These TCM memories are integrated outside the ARM® sub-system. STA8100GA has a 64 KB ITCM memory and 384 KB of DTCM memory. In the DTCM memory 160 KB is dedicated for ARM® usage and the remaining 224 KB DTCM is shared between the ARM® sub-system and the G5BB module. ARM® provides access to the TCM memories through an AHB slave interface. This AHBS interface is connected to the AMBA infrastructure in STA8100GA so that DMA present on the bus can access the TCM memories MCU.

3.4.3 Nested Vector Inter rupt Controller (NVIC)

This Nested Vectored Interrupt Controller (NVIC) allows the operative system interrupt handler to quickly dispatch interrupt service routines in response to peripheral interrupts. It provides a software interface to the interrupt system. ARM® Cortex® M7 has an NVIC module for handling the interrupts. The NVIC supports 128 interrupts with 16 levels of priority, which can be changed dynamically. The software can control each request line to generate software interrupts.

General description STA8100GA 14/42 DS13006 Rev 4

3.4.4 AXI bus

AXI Bus matrix handles major high bandwidth transactions for STA8100GA. It connects the SRAM, boot ROM and external memory controllers, which provide access to the external Flash. ARM® acts as a master on this bus with the highest priority.

3.5 APB peripherals

3.5.1 APB bridge 2 peripherals

AHB to APB Bridge 2 sits on AHB bus matrix 0 as a slave and is used to connect peripherals. These slaves will be accessed by AHB masters connected to AHB bus matrix 0. The peripherals connected to APB 2 are: UART2, MSP1, GPIO PORT 2, MTU1.

3.5.2 APB bridge 1 peripherals

AHB to APB bridge 1 sits on AHB bus matrix 0 as a slave and is used to connect peripherals. These slaves will be accessed by AHB masters connected to AHB bus matrix0. The peripherals connected to APB 1 are UART1, EFT0, EFT1, GPIO PORT 0 and 1, MTU0, OTP, SSP , Thermal sensor, Watchdog timer.

3.5.3 APB bridge 0 peripherals

AHB to APB bridge 0 sits on AHB bus matrix 0 as a slave and is used to connect peripherals. These slaves will be accessed by AHB masters connected to AHB bus matrix0. The peripherals connected to APB 0 are the ones on the always on domain: PRCC always ON, RTC.

3.5.4 AHB slave devices

There are some AHB slave devices which are connected to AHB bus matrix 0. 3.6 eSRAM 256 KB of embedded RAM are available on top of the TCM RAM. The eSRAM is directly connected to the MCU through the AXI bus. It can be used for data and instruction.

3.7 Serial Flash Mem ory Controller (SFC)

The Serial Flash Memory Controller supports single, quad and octal memories. It can be used for in place execution thanks to direct memory mapping.

STA8100GA General description

3.8 SSP

STA8100GA has one Synchronous Serial Ports (SSPs). The SSP is a master or slave interface that enables synchronous serial communication with slave or master peripherals having one of the following:

  • Serial peripheral interface bus standards
  • Synchronous serial protocol bus standards
  • Micro-wire interface bus standards
  • Unidirectional interface In both master and slave configurations, the SSP has the following features:
  • Parallel-to-serial conversion on data written to an internal 32-bit wide, 32-location deep transmit FIFO
  • Serial-to-parallel conversion on received data, buffering it in a 32-bit wide, 32-location deep receive FIFO
  • Programmable data frame size from 4 to 32 bits
  • Programmable clock bit rate and pre-scaler
  • Programmable clock phase and polarity in SPI mode
  • Support for direct memory access (DMA)

3.9 UART

The UARTx performs serial-to-parallel conversion on data asynchronously received from a peripheral device on UARTx_RX pin, and parallel-to-serial conversion on data written by CPU for transmission on UARTx_TX pin. The transmit and receive paths are buffered with internal FIFO memories allowing up to 64 data byte for transmission, and 64 data byte with 4-bit status (break, frame, parity, and overrun) for receive. FIFOs may be burst-loaded or emptied by the system processor or DMA, from one to sixteen words per transfer.

3.10 Watchdog Timer (WDT)

Watchdog Timer (WDT) provides a way of recovering from software crashes. The watchdog clock is used to generate a regular interrupt (Irq_wdt), depending on a programmed value. The watchdog monitors the interrupt and asserts a HW reset signal (WDOGRES) if the interrupt remains unserviced for the entire programmed period. The WDT is counting down at a fixed frequency of 32.768 kHz. The watchdog timer peripheral can be used as free-running timer or as watchdog to resolve processor malfunctions due to hardware or software failures. Feature set overview:

  • 16-bit down counter
  • 8-bit clock pre-scaler
  • Safe reload sequence
  • Free-running timer mode
  • End of counting interrupt generation

General description STA8100GA 16/42 DS13006 Rev 4

3.11 GPIO

There are 34 GPIOs in this device. The GPIO block provides programmable inputs or outputs. Each input or output can be controlled in two modes:

  • Software mode through an APB bus interface
  • Alternate function mode, where GPIO becomes a peripheral input or output line Any GPIO input can be independently enabled or disabled (masked) for interrupt generation. User can select for each GPIO which edge (rising, falling, both) will trigger an interrupt. A de-bouncing logic can be enabled for each GPIO to filter glitches on IOs before going to the Interrupt generation and CPU read value. All GPIOs are fail safe to avoid leakage consumption in any condition even when the ring is off and the external line is logic level high.

3.12 Multi Timer Unit (MTU)

Multi Timer Unit consists of eight timers. Each timer is clocked by MXTAL frequency divided by 8 (which means 2.4 MHz with a 19.2 MHz crystal) or REFCLK (32.768 kHz) inputs.

3.12.1 MTU feature overview

  • The Multi Timer Unit provides access to four interrupt generating programmable 32-bit Free-Running decrementing Counters (FRCs) allowing up to four counts to be performed in parallel.
  • The FRCs have their own clock input, allowing the counters to run from a much slower clock than the system clock.
  • In each FRC the 32-bit counter is split up into two 16-bit counters.

3.13 RTC

This is an always-on power domain dedicated to RTC logic (backup system) with 256 bytes SRAM and supplied with a dedicated voltage regulator. The RTC provides a high resolution clock which can be used for GPS. It keeps the time when the system is inactive and can be used to wake the system up when a programmed alarm time is reached. It has a clock trimming feature to compensate for the accuracy of the 32.768 kHz crystal and a secured time update.

STA8100GA General description RTC features:

  • 47-bit counter clocked by 32.768 kHz clock
  • 32-bit for the integer part (seconds) and 15-bit for the fractional part
  • The integer part and the fractional part are readable independently
  • The counter, once enabled, can be stopped
  • Integer part load register (32-bit)
  • Fractional part load register (15-bit)
  • Load bit to transfer the content of the entire load register (integer + fractional part) to the 47-bit counter Once set by the MCU, this bit is cleared by the hardware to signal to the MCU that the RTC has been updated.

3.14 MSP

STA8100GA has one Multi mode Serial Port (MSP). The following section describes the functionalities of the MSP unit. The Multi mode Serial Port (MSP) is a synchronous transmitter serial interface. The MSP provides:

  • Element (data) sizes of 8, 10, 12, 14, 16, 20, 24, and 32 bits, LSB or MSB first
  • Programmable frequency shift clock for data transfer
  • Direct interface to SPI compliant devices
  • Transmit first-in, first-out memory buffers (FIFOs), 32 bits wide, 8 locations deep

3.15 Direct Memo ry Access (DMA)

The DMAC is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on- Chip (SoC) peripheral. The DMAC is an AMBA AHB module, and connects to the Advanced High-performance Bus (AHB).

  • Eight DMA channels. Each channel can support a unidirectional transfer.
  • The DMAC provides 32 peripheral DMA request lines.
  • Single DMA and burst DMA request signals.
  • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to- peripheral transfers.
  • Scatter or gather DMA support through the use of linked lists.
  • Hardware DMA channel priority. DMA channel 0 has the highest priority and channel 31 has the lowest priority.
  • If requests from two channels become active at the same time, the channel with the highest priority is serviced first.
  • AHB slave DMA programming interface to the DMA control registers.
  • Two AHB bus masters for transferring data.
  • Programmable DMA burst size.
  • Working on AHB clock.

3.16 Antenna sensing

input voltage range must be between VRF_IN and GND. Figure 3. Antenna sensing configuration when antenna is supplied with 3.3 V

3.17 Temperature sensor

measurement range is -40 to 125 °C. It uses integrated bandgap reference and 8-bit ADC. register, it generates an interrupt if enabled.

3.18 Serial boot pins

already latched the UART2-TX pin (C8 ball) status after latch reset. Table 8. Antenna sensing current - power rising Table 9. Antenna sensing current - power falling Table 10. Temperature sensor

  1. Best accuracy is at calibrated temperature.
  2. Limited by manufacturi ng calibration environment.

3.19 Reset

After a reset, the Cortex® M7 is woken-up by the ROM code. device and prepare it to fetch the first instruction of the user application code.

  1. Pad reset: SoC will have active low chip reset (RESET) pad. Low (zero) status on this

pad will keep device in the reset. Assertion of this pin low should be minimum of 5 ms.

  1. Power on reset: The power on reset circuitry is embedded in the main voltage regulator

reset state until VCORE_IN (or VDD_EXT_REG) minimum voltage is reached.

  1. Hardware resets: The internal voltage regulator embeds multi ple LVD (Low Voltage

Detector) and HVD (High Voltage Detector) which are used in the reset sequence.

  1. Soft reset: Different peripherals present on STA8100GA can b e reset independently

through registers present inside PRCC module.

3.20 Power Management Unit (PMU)

Table 11. Boot peripheral selection Table 12. LDO on-chip regulators

Figure 4. LDO on-chip regulators dependencies

3.20.1 Power regions

  1. Always on backup region: 1.2 V

General description STA8100GA 22/42 DS13006 Rev 4 By default IO ring1 is at 1.8 V supplied by internal LDO IO. If IO ring1 has to be at 3.3 V then external supply must be applied on VIO1 at 3.3 V. The switchable power region can be supplied by an external voltage regulator directly at pin VDD_EXT_REG. The integrated LDO CORE has to be switched off by forcing EXT_REG_SEL to high voltage. The usage of the external regulator to supply the switchable power region is mandatory in applications that require to sustain 105 °C.

3.21 CAN interface

CAN sub-system comprises two fully independent FD-CAN controllers: CAN0 and CAN1. Both controllers conform with CAN protocol version 2.0 part A, B and ISO 11898-1: 2015. Maximum data bit rate supported is 1Mbit/s.

3.22 I2C high spe ed controller

One I2C high speed controller interface is capable of master/slave modes in multi-master environment. It is DMA capable and multiple baud rates are supported: 100/ 400/ 1000/ 3400 Kbits/s. 3.23 Full speed USB 2.0 It supports 12 Mbps (full speed) and 1.5 Mbps (low speed) serial data transmission according to USB 2.0 OTG controller specification.

4 Electrical specifications

4.1 Absolute maximum ratings

4.2 Thermal data

Table 13. Absolute maximum ratings with on chip LDO voltage regulation

  1. RFA_IN ESDCDM Max is +/-150V. LNA_IN ESDCDM Max is +/-250V

Table 14. Thermal data

  1. Multilayer 2s2p as per JEDEC JESD51-2

4.3 Electrical c haracteristics

Table 15. Operating junction temperature range Table 16. VDD_EXT_REG - external core power supply Table 17. PMU11 - Functional specifications

10 Ohm serial

Table 18. PMU12 - Functional specifications

Table 19. Current consumption (Tj = 125 °C)

  1. Maximum current at VCORE is limited by maximum junction tempe rature at 125 °C and θJA 33 °C/W (which depends on

application printed circuit board). Table 20. RF Electrical characteristics (Tj = 125 °C)

Table 20. RF Electrical characteristics (Tj = 125 °C) (continued) Table 21. Electrical characteristics of digital input and output buffers

18 pF (a) as shown in Figure 5. connected to RTC_XTI/RTC_XTO pins. Table 21. Electrical characteristics of digital input and output buffers (continued) a. Using crystal with recomm ended characteristics as per Table 22. Table 22. Crystal recommended specifications Table 23. Oscillator amplifier specifications

  1. Not tested in production.

Figure 5. 32.768 kHz crystal connection

  • Disable the oscillator (bit28-OSCI_EN = 0b in PRCC_BACKUP_REG0 register). This disables the internal inverter, thus reducing the power consumption to minimum.
  • Drive the RTC_XTI pin with a square signal or a sine wave.

4.5 Power up timing sequence

Figure 6. Power up timing diagram Table 24. Characteristics of external slow clock input

4.6 Digital interface AC timing characteristics (specified by

Figure 7. Clock block diagram

4.6.1 SQIO

Table 25. Power up timing data Table 26. Clock data Table 27. SQIO SDR mode (feedback mode)

4.6.2 SPI

4.6.3 MSP master mode

Table 28. SQIO DTR mode (DQS mode for flash read) Table 27. SQIO SDR mode (feedback mode) (continued) Table 29. SPI (master mode) Table 30. MSP0 master mode

4.6.4 JTAG

Table 31. MSP0 slave mode Table 32. MSP1 slave mode Table 33. Default JTAG mode

4.6.5 USB - low speed and full speed mode

Table 34. Low speed and full speed mode

5 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark.

5.1 LFBGA81 package information

Figure 8. LFBGA81 package outline

Table 35. LFBGA81 package mechanical data

  1. LFBGA stands for Thin profile Fine Pitch Ball Grid Array:

Thin profile: 1.2 mm < A Max≤ 1.7 mm / Fine pitch: e < 1.00 mm. The total profile height (Dim A) is measured from the seating plane “C” to the top of the component. A Max = A1 Typ + A3 Typ + A4 Typ + √ (A12 + A32 + A42 tolerance values).

  1. The typical ball diameter before mounting is 0.40 mm.
  2. The tolerance of position that controls the location of the p attern of balls with respect to datums A and B.

must lie within this tolerance zone.

  1. The tolerance of position that controls the location of the b alls within the matrix with respect to each other.

must lie simultaneously in both tolerance zones.

6 Ordering information

Figure 9. Ordering information scheme

7 Revision history

Table 36. Document revision history – Changed AEC-Q100 qualification to Qualified.

3.3 V value

Updated Min. value and added a second footnote. updated min, typ and max values. TIH” to “TJS and TJH” respectively. Table 36. Document revision history (continued)