STA5620 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 29
Technical content
Datasheet sections
- 1 Block diagram
- 2 Pins description
- 3 Functional description
- 3.1 RFA and MIXER section
- 3.2 IF section
- 3.3 Variable gain amplifiers
- 3.4 A/D converter
- 3.5 PLL synthesizer and VCO
- 3.6 Crystal oscillator
- 3.7 Output buffers
- 3.8 SPI interface
- 3.9 Power control modes
- 4 Electrical specifications
- 4.1 Absolute maximum ratings
- 4.2 Thermal data
- 4.3 Electrical characteristics
- 5 Pin and I/O cells
- 5.1 Mode
- 5.2 RF_EN
- 5.3 CHIP_EN
- 5.4 TEST_EN1, TEST_EN2 and TEST_CLK
- 6 SPI bus protocol
- 6.1 SPI_CS/
- 6.2 SPI_CLK
- 6.3 SPI_DI
- 6.4 SPI_DO
- 7 Registers
Features
■ Low IF architecture (fIF = 4fO) ■ Minimum external components ■ VGA gain internally regulated ■ On chip programmable PLL ■ Typ. 2.7V supply voltage ■ SPI interface ■ 2kV HBM ESD protected ■ Compatible with GPS L1 ■ Standard QFN-32 package ■ Low power for portable designs
Description
The chip is a fully integrated RF front-end able to down-convert the GPS L1 signal from 1575.42MHz to 4.092MHz. The IF signal is converted by a two bit ADC. Sign (SIGN), Magnitude (MAG) and the 16.368MHz sampling clock (GPS_CLK) are provided to the baseband. The magnitude data is internally integrated in order to control the variable gain amplifiers in accordance to the RF input signal strength. An excellent quality of reception in critical environments is ensured by the good noise figure and linearity of the receiver. The on-chip oscillator supports crystal frequencies in the range of 10MHz to 40MHz. It is able to support TCXO providing also a buffered copy of the oscillator frequency. The chip, using STMicroelectronics BiCMOS SiGe technology, is housed in a QFN-32 package. VFQFPN-32L Table 1. Device summary
1 Block diagram
Figure 1. Block diagram
2 Pins description
Table 2. Pins list description
2 AGC_CTRL Automatic Gain Control Pin Analog – input
4 RF_IN RF section input Analog – RF input
6 GND Negative Supply Pin Gnd
7 GND Negative Supply Pin Gnd
10 V CC VCO power supply Supply pin
11 V CC Crystal oscillator power supply Supply pin
12 XTAL_IN Input Side of Crystal Osc illator or TCXO Input Analog – input
13 XTAL_OUT Output Side of Cryst al Oscillator Analog – output
15 CHIP_EN Chip Enable Digital – input
16 RF_EN RF/IF Receiver Chain Enable Digital – input
17 MODE Power-On Default Configuration Selector Digital – input
18 XTAL_CLK Crystal Oscillator Buffered Output Digital – output
19 GPS_CLK GPS Reference Clock Digital – output
21 TEST_EN2
22 SPI_DI Serial Parallel Interface Data Input Digital – input
23 SPI_CLK Serial Parallel Interface Clock Digital – input
24 SPI_CS/ Serial Parallel Interface Chip Select (Active Low) Digital – input
25 SPI_DO Serial Parallel Interface Data Output Digital – output
26 MAG Magnitude Data Digital – output
27 SIGN Sign Data Digital – output
28 GND_IO Output Drivers Ground Gnd
30 V CC SPI power supply Supply pin
31 V CC A/D converter power supply Supply pin
32 IF_TEST RF/IF Receiver Chain Test Output Analog – output
Figure 2. Pins connection diagram (bottom view)
STA5620 Functional description
3 Functional description
3.1 RFA and MIXER section
The 1575.42 MHz RF signal at the output of the external SAW filter is amplified by a RF amplifier (RFA) and then down converted by an image rejection mixer. The good performances of the cascade configuration and the technology choice guarantee a noise figure better than 4.5dB in typical conditions. In fact, the RFA gain is high enough to minimize the effects on the noise figure of the following integrated stages. The linearity of the RFA and Mixer section ensures immunity to RF blockers close to the GPS signal. Then it allows the use of low quality external pre-selection filters. Two ninety degrees out of phase signals are derived from the VCO and send to the input of the image rejection mixer. A minimum image rejection ratio of 20dB is guaranteed. The chosen IF frequency is 4f o = 4.092MHz.
3.2 IF section
The output of the mixer combiner is processed through an integrated filter able to select the GPS L1 bands. The IF filter cuts any out-of-band signal including the mixer products. In addition it acts as an anti-aliasing filter for the A/D converter. An attenuation of 20dB is guaranteed at 12f o = 12.276 MHz. The IF filter characteristic is calibrated by an internal loop which compensates process, temperature and voltage variations. In order to let the baseband reconstruct the received information, the IF filter must not introduce an excessive phase shift within the signal bandwidth.
3.3 Variable gain amplifiers
A cascade of variable gain amplifiers and the relevant control circuit balance the system gain in relationship to the RF input signal strength. In that way the signal level at the input of the A/D converter is suitably compensated. The device is able to self-adjust the AGC gain by integrating the MAG output by a dedicated circuit in order to obtain 33% of MAG bit duty cycle. The loop is compensated by an external capacitor connected to the AGC_CTRL pin. The relevant voltage is used to control the variable gain amplifiers. The internal loop can be by-passed by setting a voltage to the AGC_CTRL input pin. A dynamic range of around 55dB is typically achieved.
3.4 A/D converter
The task of the A/D converter is to determine the sign and the magnitude of the received signal. The A/D converter sampling frequency is 16f o = 16.368 MHz. Those baseband chips with just one bit input will use only the sign bit. In that case the AGC_CTRL pin must be connected to ground.
Functional description STA5620
3.5 PLL synthesizer and VCO
The PLL synthesizer is fully integrated on-chip, it is made by the voltage controlled oscillator (VCO), prescaler, dividers, phase-frequency detector (PFD), charge pump (CP) and loop filter. Both the reference divider R and the feedback divider N are programmable helping the user to choose the reference clock. The R divider ranges from 1 to 63 while the N divider from 56 to 4095. In order to achieve good phase noise performances, a LC voltage controlled oscillator has been chosen. Quadrature signals are provided by means of a Polyphase filter. A programmable loop filter is integrated on-chip to reduce the number of external components. The loop stability is guaranteed for any of the supported crystals and comparison frequencies. The charge pump is programmable and the output current can be selected among the following values: 50µA, 100µA, 150µA and 200µA.
3.6 Crystal oscillator
The reference oscillator circuit is a CMOS inverter able to work with external crystals up to 40 MHz. The crystal must be connected between the xtal input and the xtal output pins. The load capacitances must be chosen in accordance to the values specified by the crystal manufacturer. A limiting resistor can be placed at the output of the inverter in order to contain the power dissipated in the crystal within its specified maximum value. When a TCXO is used the external reference clock must be applied to the XTAL_IN terminal.
3.7 Output buffers
The RF front-end provides a set of four different signals to the baseband chip. The SIGN and the MAG outputs are the sampled bit streams of the down-converted received signal. GPS_CLK, nominally equal to 16.368 MHz, is the clock signal used by the baseband. Its source can be chosen among the crystal oscillator signal and the VCO signal by means of a 96 divider. XTAL_CLK is the buffered copy of either the crystal oscillator or the TCXO signal. In order to let the application find the best compromise between electro-magnetic interferences and the drivers speed, the output stages slew-rate can be programmed by SPI.
3.8 SPI interface
A SPI interface manages the communication between the baseband chip and the RF front- end. Four lines are required to accomplish this task: a data input line (SPI_DI), a data output line (SPI_DO), a clock line (SPI_CLK) and a chip select line (SPI_CS/) active low. Any information can be passed to the RF receiver through the SPI interface depending on the CHIP_EN and RF_EN input pins status.
STA5620 Functional description
3.9 Power control modes
Three different power control modes can be chosen by means of the CHIP_EN and the RF_EN pins. If the CHIP_EN pin is forced low the device goes to stand-by mode with very low power consumption. On the other hand, if CHIP_EN is set high, two scenarios are possible: 1. IIf RF_EN = 0 the crystal oscillator and only one output buffer are enabled, XTAL_CLK if MODE = 1 or GPS_CLK if MODE = 0; 2. If RF_EN = 1 the whole chip is active and functional. Only if MODE = 0 the XTAL_CLK output is disabled. A logic reset of the SPI registers is generated by the low to high transitions of the CHIP_EN pin. External pin strapping dominates until some SPI commands reverse the priority and overrides the strapping until next reset.
4 Electrical specifications
4.1 Absolute maximum ratings
4.2 Thermal data
4.3 Electrical characteristics
Table 3. Absolute maximum ratings Table 4. Thermal data Table 5. Electrical characteristics
Table 5. Electrical characteristics (continued)
- This value is guaranteed by design.
5 Pin and I/O cells
5.1 Mode
This pin allows a choice of initial configuration of the registers at reset. This pin will always be an input. In application this pin will be connected either LO or HI. When it is low the chip is configured to use 16.368MHz as reference frequency, otherwise the reference frequency is 19.2MHz. To use other reference frequencies the MODE bit must be overwritten by SPI.
5.2 RF_EN
This pin provides control over the operating state of the RF and PLL sections. When it is low those blocks are off, when high the status of the blocks depends of CHIP_EN. This pin will always be an input.
5.3 CHIP_EN
This pin provides control over the operating state of the chip. When it is low the entire chip is disabled and only a leakage current is present (< 10µA). On the rising edge it provides the SPI with a reset signal, the SPI default status depends on MODE and RF_EN pins status. When it is high the entire chip is enabled. This pin will always be an input.
5.4 TEST_EN1, TEST_EN2 and TEST_CLK
Those PINs are for ST test only. In the application TEST_EN1 must be set LOW, TEST_EN2 must be set HIGH (VCC_IO) and TEST_CLK must be not connected.
6 SPI bus protocol
transfer made of an address cycle and a data cycle. Figure 3. SPI byte write Figure 4. SPI byte read
6.1 SPI_CS/
pin will always be an input.
6.2 SPI_CLK
6.3 SPI_DI
6.4 SPI_DO
7 Registers
7.1 Register map
7.2 PLL N Divider
7.3 PLL R Divider
Note that registers 40, 41 and 42 are delivered on a single 24 bit bus. New register values are delivered synchronously to the bus only after register 42 is written. Table 6. Register map Table 7. PLL N divider XXXX nnnn [0:3] 96 1555 PLL Feedback Divider Division Ratio0x41 nnnn nnnn [0:7] Table 8. PLL R divider 0x42 RDIV XXrr rrrr [0:5] 1 19 Reference Divider Division Ratio
7.4 Radio configuration register
7.5 Test register
Table 9. Radio configuration register Table 10. Test register
7.6 Debug register (sub-circuit enables)
Table 11. Debug register (sub-circuit enables)
7.7 Radio trimming register
7.8 Receiver chain register (enable)
Table 12. Radio trimming register Table 13. Receiver chain register (enable)
8 Chip enable and reset timing
Figure 5. Chip enable and reset timing
8.1 Principle of operation
- The first time period (Clock Out Enable) is long enough to safely enable XTAL_CLK as early as possible by default during oscillator startup.
- The second period (Internal reset) generates an internal reset pulse long enough to guarantee open-loop clock stabilization (driven either by internal oscillator or by off-chip TCXO) and be able to load the chip default configuration. The default initial configurations depend on the state of the MODE input pin. After this phase, the chip configuration may be modified by the baseband unit with a set of SPI commands, allowing a more specific configuration to be set VDD Power Xce (XTAL_CLK enable) reset CHIP_EN MODE MODE Pin setting Power -on Internal reset (min. 4ms) Clock Out Enable (min 1µs) Mode = 0 Mode = 1 Internal Oscillator <chip config> Chip Config setting AC00328
8.1.1 Operating modes
provides the DATA to Base Band. LOW → the device goes to stand-by mode with very low power consumption. Table 14. Operating modes
8.2 Default configuration
This table describes the default configuration of the STA5620 internal registers. Table 15. Default configuration
Note: Disabling a digital output buffer means driving it low. Table 15. Default configuration (continued)
9 Package information
conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 6. VFQFPN 32L (5x5x1.0mm) mechanical data and package dimensions
10 Packing information
Figure 7. Reel, leader and trailer dimensions
Table 16. Document revision history 24-Jul-2007 1 Initial release.