STA533WF_11 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 15
Technical content
Features
■ Multipower BCD technology ■ Low input/output pulse width distortion ■ 200-mΩ RdsON complementary DMOS output stage ■ CMOS-compatible logic inputs ■ Thermal protection ■ Thermal warning output ■ Undervoltage protection ■ Short-circuit protection
Description
The STA533WF is a monolithic quad half-bridge stage in multipower BCD technology. The device can be used as a dual bridge or reconfigured, by connecting pin CONFIG to pins VDD, as a single bridge with double-current capability. The device is designed for the output stage of a stereo Full Flexible Amplifier (FFX™). It is capable of delivering 10 W x 4 channels into 4-Ω loads with 10% THD at V CC =1 8V i n single-ended configuration. It can also deliver 20 W + 20 W into 8-Ω loads with 10% THD at VCC = 18 V in BTL configuration or, in single parallel BTL configuration, 40 W into a 4-Ω load with 10% THD at V CC = 18 V. The input pins have a threshold proportional to the voltage on pin VL. The STA533WF comes in a 36-pin PowerSSO package with exposed pad down (EPD). PowerSSO36 package with exposed pad down Table 1. Device summary
1 Pin description
Figure 1. Pin out Table 2. Pin list
1 GNDSUB PWR Substrate ground
4 VCC2B PWR Positive supply
5 GND2B PWR Negative supply
6 GND2A PWR Negative supply
7 VCC2A PWR Positive supply
12 VCC1B PWR Positive supply
13 GND1B PWR Negative supply
14 GND1A PWR Negative supply
15 VCC1A PWR Positive supply
19 GNDCLEAN PWR Logical ground
20 GNDREG PWR Filtering for regulator; this is an internally generated ground for V
23 VL PWR High logical state setting voltage, V L
24 CONFIG I
25 PWRDN I
26 TRISTATE I
27 FAULT O
28 THWARN O
29 IN1A I Input of half-bridge 1A
30 IN1B I Input of half-bridge 1B
31 IN2A I Input of half-bridge 2A
32 IN2B I Input of half-bridge 2B
Table 2. Pin list (continued)
2 Electrical characteristics
Table 3. Absolute maximum ratings Table 4. Recommended operating conditions Table 5. Thermal data Table 6. Electrical characteristics
Table 6. Electrical characteristics (continued)
3 Applications information
channel into 8 Ω with 10% THD at VCC = 18 V with high efficiency. MOSFET outputs and thermal and short-circuit protection circuitry. damped ternary modulation operation. In binary mode, both full-bridge and half-bridge modes are supported. lockout with automatic recovery. A thermal warning status is also provided. Figure 4. Block diagram for FFX or binary modes Figure 5. Block diagram for binary half-bridge mode
The STA533WF includes protection circuitry for overcurrent and thermal overload conditions. A thermal warning pin (THWARN) is activated low (open-drain MOSFET) when the IC temperature exceeds 130 °C, which is in advance of the thermal shutdown protection. When a fault condition is detected an internal fault signal acts to immediately disable the output power MOSFETs, placing both H-bridges in the high-impedance state. At the same time an open-drain MOSFET connected to pin FAULT is switched on. There are two possible modes subsequent to activating a fault:
- Shutdown mode: with pins FAULT (with pull-up resistor) and TRISTATE independent, an activated fault disables the device, signalling low at pin FAULT. The device may subsequently be reset to normal operation by toggling pin TRISTATE from high to low and back to high using an external logic signal.
- Automatic recovery mode: This is shown in the applications circuit in Figure 6 and Figure 7 on page 10. Pins FAULT and TRISTATE are shorted together and connected to a time constant circuit comprising R59 and C58. An activated fault forces a reset on pin TRISTATE causing normal operation to resume following a delay determined by the time constant of the circuit. If the fault condition is still present this operation continues to repeat until the fault condition is removed. An increase in the time constant of the circuit produces a longer recovery interval. Care must be taken in the overall system design so as not to exceed the protection thresholds under normal operation. Power outputs The STA533WF power and output pins are duplicated to provide a low-impedance path for the device bridged outputs. All duplicated power, ground and output pins must be connected for reliable operation. Pins PWRDN or TRISTATE should be used to set all MOSFETS to the high-impedance state during power-up and until the logic power supply on pin VL has settled. Parallel-output and high-current operation When using FFX mode, the STA533WF outputs can be connected in parallel to increase the output current capability. In this configuration the device can provide 40 W into 4 Ω. This mode of operation is enabled with pin CONFIG connected to V DD. The inputs must be combined to give INLA = INLB and INRA = INRB, then the corresponding outputs can be shorted together to give OUTLA = OUTLB and OUTRA = OUTRB. The snubber RC network shown in the applications figures must be placed as close as possible to the output pins. This reduces ringing, over- and undervoltage effects, and improves the audio quality and EMI performance.
Figure 7. Applications circuit for single-BTL configuration
22 VL23 CONFIG24 PWRDN25 TRISTATE26 FAULT27 THWARN28 IN1A29 IN1B30 IN2A31 IN2B32 VSS33 VSS
34 VCCSIG35 VCCSIG36
4 Heatsink requirements
24 °C/W in natural air convection. Figure 8. Double-layer PCB with copper ground areas and 16 via holes
4 W for 2 x 20 W into 8 Ω at 18 V
Figure 9. Power derating curves for PCB used as heatsink
5 Package mechanical data
The STA533WF comes in a 36-pin PowerSSO package with exposed pad down (EPD). Figure 10 below shows the package outline and Table 8 gives the dimensions. specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Table 8. PowerSSO36 EPD dimensions
Figure 10. PowerSSO36 EPD outline drawing
6 Revision history
Table 9. Document revision history 02-Jul-2010 1 Initial release.