STA500

STA500 STMICROELECTRONICS | Alldatasheet

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Technical content

■ MINIMUM INPUT OUTPUT PULSE WIDTH DISTORTION ■ 200m Ω RdsON COMPLEMENTARY DMOS OUTPUT STAGE ■ CMOS COMPATIBLE LOGIC INPUTS ■ THERMAL PROTECTION ■ THERMAL WARNING OUTPUT ■ OVERVOLTAGE, UNDERVOLTAGE PROTECTION

DESCRIPTION

STA500 is a monolithic quad half bridge stage in Mul- tipower BCD Technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability, and as half bridge (Binary mode) with half current capability. The device is particulary designed to make the output stage of a stereo All-Digital High Efficiency (DDX™) amplifier capable to deliver 30 + 30W output power on 8 Ω load and 60W on 8Ω load in bridge BTL con- figuration or mono 60W on 4Ω load. The input pins have threshold proportional to Ibias pin voltage. PowerSO36 ORDERING NUMBER: STA500 30V 3.5A QUAD POWER HALF BRIDGE AUDIO APPLICATION CIRCUIT (Dual BTL) L18 22mH L19 22mH C30 1mF C20 100nF C99 100nF C101 100nF C107 100nF C106 100nF C23 470nF C55 1000mF C21 100nF C58 100nF C58 100nF R57 10K R59 10K R63 R98 R100 C53 100nF C60 100nF C31 1mF C52 330pF R104 C109 330pF IN1A IN1A IBIAS CONFIG PWRDNPWRDN FAULT TRI-STATE TH_WAR TH_WAR +3.3V IN1B VDD VDD VSS VSS VCC SIGN VCC SIGN GND-Reg GND-Clean IN2A IN1B IN2A IN2B PROTECTIONS LOGIC REGULATORS OUT1A GND1A OUT1A V CC 1A OUT1B GND1B OUT1B VCC 1B L113 22mH L112 22mH C32 1mF +VCC C108 470nF C33 1mF M17 M15 M16 M14 OUT2A GND2A OUT2A V CC 2A OUT2B GND2B D00AU1148B OUT2B VCC 2B GNDSUB IN2B 32 C110 100nF C111 100nF R103 R102 MULTIPOWER BCD TECHNOLOGY

N° Pin Description

1 GND-SUB Substrate ground

35 ; 36 Vcc Sign Signal Positive supply

15 Vcc1A Positive Supply

12 Vcc1B Positive Supply

7 Vcc2A Positive Supply

4 Vcc2B Positive Supply

14 GND1A Negative Supply

13 GND1B Negative Supply

6 GND2A Negative Supply

5 GND2B Negative Supply

16 ; 17 OUT1A Output half bridge 1A 10 ; 11 OUT1B Output half bridge 1B 8 ; 9 OUT2A Output half bridge 2A 2 ; 3 OUT2B Output half bridge 2B

29 IN1A Input of half bridge 1A

30 IN1B Input of half bridge 1B

31 IN2A Input of half bridge 2A

32 IN2B Input of half bridge 2B

21 ; 22 Vdd 5V Regulator referred to ground 33 ; 34 Vss 5V Regulator referred to +Vcc

25 PWRDN Stand-by pin (Control input)

26 TRI-STATE Hi-Z pin (Control input)

27 FAULT Fault pin advisor (Open Collector Output)

24 CONFIG Configuration setting pin

28 TH-WAR Thermal warning advisor (Open Collector Output)

19 GND-clean Logical ground

23 IBIAS High logical state setting voltage

18 NC Not connected

20 GND-Reg Ground for Vdd regulator

(*) : The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. (**:) To put CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd) PIN CONNECTION PIN NAME Logical value IC -STATUS FAULT 0 Fault detected (Short circuit, or Thermal ..) FAULT (*) 1 Normal Operation TRI-STATE 0 All powers in Hi-Z state TRI-STATE 1 Normal operation PWRDN 0 Low absorpion PWRDN 1 Normal operation THWAR 0 Temperature of the IC =130°C THWAR (*) 1 Normal operation CONFIG 0 Normal Operation CONFIG (**) 1 OUT1A=OUT1B ; OUT2A=OUT2B (IF IN1A = IN1B; IN2A = IN2B) GND-SUB OUT2B OUT2B V CC 2B GND1B VCC 1A GND1A OUT1A OUT1A GND-Reg VDD VDD CONFIG IBIAS VSS VSS VCC Sign VCC Sign 19N.C. GND-Clean D00AU1133 OUT1B VCC 1B OUT1B PWRDN FAULT TRI-STATE OUT2A TH_WAR 10 27 GND2B OUT2A VCC 2A IN1A IN2B IN1B GND2A IN2A 13 24

Symbol Parameter Value Unit VCE DC Supply Voltage (Pin 4,7,12,15) 40 V Vmax Maximum Voltage on pins (23 to 32) 5.5 V Top Operating Temperature Range 0 to 70 °C Tstg, Tj Storage and Junction T emperature -40 to 150 °C Symbol Parameter Min. Typ. Max. Unit Tj-case Thermal Resistance Junction to Case (thermal pad) 2.5 °C/W TjSD Thermal shut-down junction temperature 150 °C Twarn Thermal warning temperature 130 °C thSD Thermal shut-down hysteresis 25 °C ELECTRICAL CHARACTERISTCS (Ibias = 3.3V; Vcc = 28V; Tamb = 25°C unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit R dsON Power Pchannel/Nchannel MOSFET R dsON Id=1A; 200 270 m Ω Idss Power Pchannel/Nchannel leakage Idss Vcc=35V 50 µA gN Power Pchannel RdsON Matching (*) Id=1A 95 % gP Power Nchannel RdsON Matching (*) Id=1A 95 % Dt_s Low current Dead Time (static) see test circuit no.1; see fig. 1 10 20 ns Dt_d High current Dead Time (dinamic) L=22µH; C = 470nF; Rl = 8Ω Id = 3.5A; see fig. 3 50 ns td ON Turn-on delay time Resistive load 100 ns td OFF Turn-off delay time Resistive load 100 ns tr Rise time Resistive load; as fig. 1 25 ns tf Fall time Resistive load; as fig. 1 25 ns VCC Supply voltage operating voltage 9 V OV V VIN-H High level input voltage Ibias/2 +300mV V VIN-L Low level input voltage Ibias/2 -300mV V IIN-H Hi level Input current Pin voltage=Ibias 1 µA IIN-L Low level input current Pin voltage = 0.3V 1 µA IPWRDN-H Hi level PWRDN pin input current Ibias = 3.3V 35 µA VL Low logical state voltage VL (pin PWRDN, TRISTATE) (note 1) Ibias = 3.3V 0.8 V VH High logical state voltage VH (pin PWRDN, TRISTATE) (note 1) Ibias = 3.3V 1.7 V

Notes: 1. The following table explains the VL, VH variation with Ibias Note 2: If used in single BTL configuration, the device may be not short circuit protected LOGIC TRUTH TABLE (see fig. 2) IVCC- PWRDN Supply current from Vcc in Power Down PWRDN = 0 3 mA IFAULT Output Current pins FAULT -TH-WARN when FAULT CONDITIONS Vpin = 3.3V 1 mA IVCC-hiz Supply current from Vcc in Tri- state Tri-state=0 22 mA IVCC Supply current from Vcc in operation (both channel switching) Input pulse width = 50% Duty; Switching Frequency = 384Khz; No LC filters; 80 mA I OUT -SH Overcurrent Protection Threshold (short circuit current limit) (note 2) 3.5 6 8 A VOV Overvoltage protection threshold 30 35 40 V VUV Undervoltage protection threshold 7 V tpw_min Output minimum pulse width No Load 70 150 ns Ibias VLmin VHmax Unit 2.7 0.7 1.5 V 3.3 0.8 1.7 V 5 0.85 1.85 V TRI-STATE INxA INxB Q1 Q2 Q3 Q4 OUTPUT MODE

0 X X OFF OFF OFF OFF Hi-Z

1 0 1 OFF ON ON OFF NEGATIVE 1 1 0 ON OFF OFF ON POSITIVE 1 1 1 ON ON OFF OFF Not used ELECTRICAL CHARACTERISTCS (continued) (Ibias = 3.3V; Vcc = 28V; Tamb = 25°C unless otherwise specified) Symbol Parameter Test conditions Min. Typ. Max. Unit

Figure 4. Typical Quad Half Bridge Configuration to the schematic shown in fig. 1).

DIM. mm inch A 3.60 0.141 a1 0.10 0.30 0.004 0.012 a2 3.30 0.130 a3 0 0.10 0 0.004 b 0.22 0.38 0.008 0.015 c 0.23 0.32 0.009 0.012 D (1) 15.80 16.00 0.622 0.630 D1 9.40 9.80 0.370 0.385 E 13.90 14.50 0.547 0.570 e 0.65 0.0256 e3 11.05 0.435 E1 (1) 10.90 11.10 0.429 0.437 E2 2.90 0.114 E3 5.80 6.20 0.228 0.244 E4 2.90 3.20 0.114 0.126 G 0 0.10 0 0.004 H 15.50 15.90 0.610 0.626 h 1.10 0.043 L 0.80 1.10 0.031 0.043 N1 0 °(max.) S8 °(max.) (1): "D" and "E1" do not include mold flash or protrusions - Mold flash or protrusions shall not exceed 0.15mm (0.006 inch) - Critical dimensions are "a3", "E" and "G". PowerSO36 e a2 A E PSO36MEC DETAIL A D 11 8 1936 E1E2 h x 45˚ DETAIL Alead sluga3 S Gage Plane 0.35 L DETAIL B DETAIL B (COPLANARITY) GC - C - SEATING PLANE c NN ¯ M0.12 ABb B A H BOTTOM VIEW OUTLINE AND MECHANICAL DATA

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