STA015

STA015_10 STMICROELECTRONICS | Alldatasheet

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Technical content

„ SINGLE CHIP MPEG2 LAYER 3 DECODER SUPPORTING: – All features specified for Layer III in ISO/IEC 11172-3 (MPEG 1 Audio) – All features specified for Layer III in ISO/IEC 13818-3.2 (MPEG 2 Audio) – Lower sampling frequencies syntax exten- sion, (not specified by ISO) called MPEG 2.5 „ DECODES LAYER III STEREO CHANNELS, DUAL CHANNEL, SINGLE CHANNEL (MONO) „ SUPPORTING ALL THE MPEG 1 & 2 SAMPLING FREQUENCIES AND THE EXTENSION TO MPEG 2.5: 48, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz „ ACCEPTS MPEG 2.5 LAYER III ELEMENTARY COMPRESSED BITSTREAM WITH DATA RATE FROM 8 Kbit/s UP TO 320 Kbit/s „ ADPCM CODEC CAPABILITIES: – sample frequency from 8 kHz to 32 kHz – sample size from 8 bits to 32 bits – encoding algorithm: DVI, ITU-G726 pack (G723-24, G721,G723-40) – Tone control and fast-forward capability „ EASY PROGRAMMABLE GPSO INTERFACE FOR ENCODED DATA UP TO 5Mbit/s (TQFP44 & LFBGA 64) „ DIGITAL VOLUME CONTROL „ DIGITAL BASS & TREBLE CONTROL „ BYPASS MODE FOR EXTERNAL AUDIO SOURCE „ SERIAL BITSTREAM INPUT INTERFACE „ EASY PROGRAMMABLE ADC INPUT INTERFACE „ ANCILLARY DATA EXTRACTION VIA I2C INTERFACE. „ SERIAL PCM OUTPUT INTERFACE (I2S AND OTHER FORMATS) „ PLL FOR INTERNAL CLOCK AND FOR OUTPUT PCM CLOCK GENERATION „ CRC CHECK AND SYNCHRONISATION ERROR DETECTION WITH SOFTWARE INDICATORS „ I2C CONTROL BUS „ LOW POWER 2.4V CMOS TECHNOLOGY „ WIDE RANGE OF EXTERNAL CRYSTALS FREQUENCIES SUPPORTED

APPLICATIONS

„ PC SOUND CARDS „ MULTIMEDIA PLAYERS „ VOICE RECORDERS

DESCRIPTION

The STA015 is a fully integrated high flexibility MPEG Layer III Audio Decoder, capable of decod- ing Layer III compressed elementary streams, as specified in MPEG 1 and MPEG 2 ISO standards. The device decodes also elementary streams compressed by using low sampling rates, as spec- ified by MPEG 2.5. STA015 receives the input data through a Serial input Interface. The decoded signal is a stereo, mono, or dual channel digital output that can be sent directly to a D/A converter, by the PCM Output Interface. This interface is software programmable to adapt the STA015 digital output to the most common DACs architectures used on the market. The func- tional STA015 chip par titioning is described in Fig.1a and Fig.1b. ORDERING NUMBER: STA015$ (SO28) STA015T$ (TQFP44) STA015B$ (LFBGA 8x8) SO28 TQFP44 LFBGA64 MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY Obsolete Product(s) - Obsolete Product(s)

Obsolete Product(s) - Obsolete Product(s) STA015 Figure 1. 1a. Block Diagram for TQFP44 and LFBGA64 package. 1b. BLOCK DIAGRAM for SO28 package I2C CONTROL SERIAL INPUT INTERFACE BUFFER 256 x 8 MPEG L III ADPCM CORE VOLUME & TONE CONTROL OUTPUT BUFFER PCM OUTPUT INTERFACE GPIO INTERFACE GPSO INTERFACE PARSER 31 32 RESET SDA SCL BIT_EN DATA-REQ SCKR SDI ADC INPUT INTERFACE SDI_ADC LRCK_ADC SCK_ADC SDO IODATA [7:0] STROBE SCKT LRCKT GPSO_REQ GPSO_SCKR GPSO_DATA OCLK SYSTEM & AUDIO CLOCKS XTI XTO FILTTESTEN D99AU1116B 15 13 22 12 DSP BASED TQFP44 I2C CONTROL SERIAL INPUT INTERFACE BUFFER 256 x 8 MPEG L III ADPCM CORE VOLUME & TONE CONTROL OUTPUT BUFFER PCM OUTPUT INTERFACE PARSER RESET SDA SCL BIT_EN GPSO_SCKR SCKR SDI ADC INPUT INTERFACE SDI_ADC LRCK_ADC SCK_ADC SDO SCKT LRCKT OCLK SYSTEM & AUDIO CLOCKS XTI XTO FILTTESTEN D99AU1117B 21 20 24 19 DSP BASED SO28

Figure 2. Pin Connection

Obsolete Product(s) - Obsolete Product(s) STA015

1.0 OVERVIEW

1.1 MP3 decoder engine

The MP3 decoder engine is able to decode any La yer III compliant bitstream: MPEG1, MPEG2 and MPEG2.5 streams are supported. Besides audio data decoding the MP3 engine also performs ANCIL- LARY data extraction: these data can be retrieved via I2C bus by the application microcontroller in order to implement specific functions. Decoded audio data goes through a software volume control and a two-band equalizer blocks before feed- ing the output I2S interface. This results in no need for an external audio processor. MP3 bitstream is sent to the decoder using a simple serial input interface (see pins SDI, SCKR, BIT_EN and DATA_REQ), supporting input rate up to 20 Mbit/s. Received data are stored in a 256 bytes long input buffer which provides a feedback line (see DATA_REQ pin) to the bitstream source (tipically an MCU).

1.2 ADPCM encoder/decoder engine

This device also embeds a multistandard ADPCM enc oder/decoder supporting different sample rates (from 8 KHz up to 32 KHz) and different sample sizes (from 8 bit to 32 bits). During encoding process two different interfaces can be used to feed data: the serial input interface (same interface used also to feed MP3 bitstream) or the A DC input interface, which provides a seamless con- nection with an external A/D converter. The currently used interface is selected via I2C bus. Also to retrieve encoded data two different interfaces are available: the I2C bus or the faster GPSO output interface. GPSO interface is able to output data with a bitrate up to 5 Mbit/s and its control pins (GPSO_SCKR, GPSO_DATA and GPSO_REQ) can be configured in order to easily fit the target applica- tion.

1.3 BYPASS functional mode

In order to allow using the device to post-process auxiliary audio sources a special BYPASS mode is avail- able. When the device is configured in BYPASS mode the embedded DSP will process digital audio data coming through the ADC input interface and will output the resulting data to the external DAC. Available processings include volume and a tone ontrols. THERMAL DATA ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit Rth j-amb Thermal resistance Junction to Ambient 85 °C/W Symbol Parameter Value Unit VDD Power Supply -0.3 to 4 V Vi Voltage on Input pins -0.3 to VDD +0.3 V VO Voltage on output pins -0.3 to V DD +0.3 V Tstg Storage Temperature -40 to +150 °C Toper Operative ambient temp -20 to +85 °C

Obsolete Product(s) - Obsolete Product(s) STA015 PIN DESCRIPTION Note: In functional mode TESTEN must be connected to VDD, SO28 TQFP44 LFBGA64 Pin Name Type Function PAD Description 1 29 B5 VDD_1 Supply Voltage 2 30 B4 VSS_1 Ground 33 1 A 4 S D AI / O i 2C Serial Data + Acknowledge CMOS Input Pad Buffer CMOS 4mA Output Drive 43 2 B 3 S C L I I2C Serial Clock CMOS Input Pad Buffer 5 34 A1 SDI I Receiver Serial Data CMOS Input Pad Buffer 6 36 B2 SCKR I Receiver Serial Clock CMOS Input Pad Buffer 7 38 D4 BIT_EN I Bit Enable CMOS Input Pad Buffer with pull up 8 40 D1 SRC_INT/ SCK_ADC I Interrupt Line/ADC Serial Clock CMOS Input Pad Buffer 9 42 E2 SDO O Transmitter Serial Data (PCM Data) CMOS 4mA Output Drive 10 44 F2 SCKT O Transmitter Serial Clock CMOS 4mA Output Drive 11 2 H1 LRCKT O Transmitter Left/Rig ht Clock CMOS 4mA Output Drive 12 3 H3 OCLK I/O Oversampling Clock for DAC CMOS Input Pad Buffer CMOS 4mA Output Drive 13 5 F3 VSS_2 Ground 14 6 E4 VDD_2 Supply Voltage 15 7 G4 VSS_3 Ground 16 8 G5 VDD_3 Supply Voltage 17 10 F5 PVDD PLL Power 18 11 G6 PVSS PLL Ground 19 12 G7 FILT O PLL Filter Ext. Capacitor Conn. 20 13 G8 XTO O Crystal Output CMOS 4mA Output Drive 21 15 F7 XTI I Crystal Input (Clock Input) Specific Level Input Pad (see paragraph 2.1) 22 19 E7 VSS_4 Ground 23 21 C8 VDD_4 Supply Voltage 24 22 D7 TESTEN I Test Enable CMOS Input Pad Buffer with pull up 25 24 A7 SDI_ADC I ADC Data Input CMOS Input Pad Buffer 26 25 B6 RESET I System Reset CMOS Input Pad Buffer with pull up 27 26 A5 LRCK_ADC I ADC left/Right Clock CMOS Output Pad Buffer 28 27 C5 IN_CLK/ DATA_REQ O Buffered Output Clock/ Data Request Signal CMOS 4mA Output Drive

20 C7 IODATA[0] I/O GPIO Data Line CMOS 4mA Schmitt

18 E6 IODATA[1] I/O GPIO Data Line

16 F6 IODATA[2] I/O GPIO Data Line

14 F8 IODATA[3] I/O GPIO Data Line

37 C3 IODATA[4] I/O GPIO Data Line

39 E3 IODATA[5] I/O GPIO Data Line

41 D2 IODATA[6] I/O GPIO Data Line

43 F1 IODATA[7] I/O GPIO Data Line

35 C2 GPIO_STROBE I/O GPIO Strobe Signal

4 G3 GPSO_REQ O GPSO Request Signal CMOS Output Pad Buffer

28 C6 GPSO_SCKR I GPSO Serial Clock CMOS Input Pad Buffer

33 A2 GPSO_DATA O GPSO Serial Data CMOS Output Pad Buffer

Obsolete Product(s) - Obsolete Product(s) STA015 ELECTRICAL CHARACTERISTICS: VDD = 3.3V ±0.3V; Tamb = 0 to 70°C; Rg = 50 Ω unless otherwise specified DC OPERATING CONDITIONS GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Notes: 1. The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electro static stress on the pin. 2. Human Body Model. DC ELECTRICAL CHARACTERISTICS Notes: 1. Takes into account 200mV voltage drop in both supply lines. 2. X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability. Notes: 1. Min. condition: V DD = 2.7V, 125°C Min process Max. condition: VDD = 3.6V, -20°C Max. POWER DISSIPATION Symbol Parameter Value VDD Power Supply Voltage 2.4 to 3.6V Tj Operating Junction Temperature -20 to 125°C Symbol Parameter Test Condition Min. Typ. Max. Unit Note IIL Low Level Input Current Without pull-up device Vi = 0V -10 10 µA1 IIH High Level Input Current Without pull-up device Vi = VDD -10 10 µA1 Vesd Electrostatic Protection Leakage < 1 µA 2000 V 2 Symbol Parameter Test Condition Min. Typ. Max. Unit Note VIL Low Level Input Voltage 0.2*V DD V VIH High Level Input Voltage 0.8*V DD V Vol Low Level Output Voltage I ol = Xma 0.4V V 1, 2 Voh High Level Output Voltage 0.85*V DD V1 , 2 Symbol Parameter Test Condition Min. Typ. Max. Unit Note Ipu Pull-up current Vi = 0V; pin numbers 7, 24 and 26; -25 -66 -125 µA1 Rpu Equivalent Pull-up Resistance 50 k Ω Symbol Parameter Test Condition Min. Typ Max Unit Note PD Power Dissipation @ VDD = 2.4V Sampling_freq ≤24 kHz 76 mW Sampling_freq ≤32 kHz 79 mW Sampling_freq ≤48 kHz 85 mW

Figure 3. Test Circuit Figure 4. Test Load Circuit

2.0 FUNCTIONAL DESCRIPTION

2.1 Clock Signal

generating input frequencies of 10, 14.31818 or 14.7456 MHz. by downloading a specific configuration file, provided by STM XTI is an input Pad with specific levels.

27 LRCK_ADC

2.2 PLL & Clock Generator System

factors. The operation is done by STA015 embedded software and it is transparent to the user. clock, OCLK, obtained dividing the VCO frequency with a software programmable dividers. Figure 5. PLL and Clocks Generation System

2.3 STA015 Operational Modes

This mode can be used to encode the incoming bitstream with 4 different compression algorithms. features refer to the related registers. handling and control flow is the same as in the MP3 Mode.

tuner or some other auxiliary source. controlled by STA015 embedded oftware. The data coming from the serial interface are stored in the input buffer, a 256 bytes long FIFO. speed used to send MP3 data). data is received in this time the buffer will be emptied and this will badly affect the output audio. In this mode the fractional part of the PLL is disabled and the audio clocks are generated at nominal rates. polarity of the DATA_REQ line (register REQ_POL). coder and no more feedback will be generated to the data source. your local ST branch to have more information about. Figure 6. DATA_REQ control line

2.4 STA015 Decoding States

states are described in the STA015 I2C registers description. be initialized during this mode (set MUTE to 1).

first decoded samples are at the output stage of the device. Figure 7. MPEG Decoder Interface Figure 8. Serial Input Interface Clocks

3.0 INTERFACE DESCRIPTION

3.1 Serial Input Interface

nication interface connected to the SDI (Serial Data Input) and SCKR (Receiver Serial Clock). The interface can be configured to receive data sampled on both rising and falling edge of the SCKR clock.

figuration). The possible configurations are described in Fig. 8.

3.2 GPSO Output Interface

configurable 3-lines protocol, as described by figure 10.

3.3 PCM Output Interface

first (MS) or least significant bit first LS), selected by writing into a flag of the PCMCONF register. by STA015 is described in Table 1. line) can be configured as well. Figure 9. PCM Output Formats Table 1. MPEG Sampling Rates (KHz)

Obsolete Product(s) - Obsolete Product(s) STA015

3.4 ADC Inteface

Beside the serial input interface based on SDI and SCKR lines a 3 wire flexible and user configurable input interface is also available, suitable to interface with most A/D converters. To configure this interface 4 spe- cific I2C registers are av ailable (ADC_ENABLE, ADC_CONF, ADC_WLEN and ADC_WPOS). Refer to registers description for more details.

3.5 General Purpose I/O Interface

A new general purpose I/O interface has been added to this device (TQFP44 and LFBGA64 only). Actually only the strobe line is used in ADPCM encoding mode to provide an interrupt; other pins are reserved for future use. The related configuration register is GPIO_CONF. See the following summary for related pin usage:

4.0 ADPCM ENCODING: OVERVIEW

According to the previously described interfaces there are 4 ways to manage ADPCM data stream while encoding. Input interface can be either the serial receiver block (SDI + SCKR + DATA_REQ lines) or the ADC specific interface. Output interfaces can be either the I2C bus (with or without interrupt line) or the GPSO high-speed serial interface (GPSO_REQ + GPSO_ DATA + GPSO_SCKR lines). This result in the following 4 methods to handle encoding flow: (*) STA013 Compatible mode Figure 10. Name Description Dir I/ODATA [0] I/ODATA [7] GPIO data line I/O I/O GPIO_STROBE GPIO strobe line I/O INPUT (data to encode) Output (e ncoded data) Available on package ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC) GPSO I/F (GPSO_REQ + GPSO_DATA + GPSO_SCKR) TQFP44/LFBGA64 ADC I/F (SDI_ADC + LRCK_ADC + SCK_ADC) I2C + Interrupt (SCL + SDA +DATA_REQ) SO28/TQFP44 LFBGA64 SERIAL I/F (SCKR + SDI + DATA_REQ) GPSO I/F (GPSO_REQ + GPSO_DATA + GPSO_SCKR) TQFP44/LFBGA64 SERIAL I/F (SCKR + SDI + DATA_REQ) (*) I2C (polling) (SCL + SDA) SO28/TQFP44 LFBGA64 STA015 MCU GPSO_SCKR GPSO_SCKR GPSO_REQ GPSO_DATA GPSO_DATA GPSO_REQ D00AU1145

Figure 14. Input from BITSTREAM, Output from GPSO Figure 15. Input from ADC, Output from GPSO

5.0 I 2C BUS SPECIFICATION

the serial clock for synchronisation. The STA015 is always a slave device in all its communications.

5.1 COMMUNICATION PROTOCOL

is high are used to identify START or STOP condition.

5.1.1 Start condition

stable in the high state. A START condition must precede any command for data transfer.

5.1.2 Stop condition

in the high state. A STOP condition terminates communications between STA015 and the bus master.

5.1.3 Acknowledge bit

SDA bus low to acknowledge the receipt of 8 bits of data.

5.1.4 Data input

change only when the SCL line is low.

5.2 DEVICE ADDRESSING

corresponding to the I2C bus definition. For the STA015 these are fixed as 1000011. The 8th bit (LSB) is the read or write operation RW, this bit is set to 1 in read mode and 0 for write mode. identification byte is the internal space address. acknowledges this and waits for the byte of internal address. After receiving the internal bytes address the STA015 again responds with an acknowledge.

5.3.1 Byte write

terminates the transfer by generating a STOP condition.

5.3.2 Multibyte write

generating a STOP condition. Figure 16. Write Mode Sequence Figure 17. Read Mode Sequence

Obsolete Product(s) - Obsolete Product(s) STA015 5.4 READ OPERATION (see Fig. 17)

5.4.1 Current byte address read

The STA015 has an internal byte address counter. Each time a byte is written or read, this counter is in- cremented. For the current byte address read mode, following a START condition the master sends the device address with the RW bit set to 1. The STA015 acknowledges this and outputs the byte addressed by the internal byte address counter. The master does not acknowledge the received byte, but terminates the transfer with a STOP condition.

5.4.2 Sequential address read

This mode can be initiated with either a current address read or a random address read. However in this case the master does acknowledge the data byte output and the STA015 continues to output the next byte in sequence. To terminate the streams of bytes the master does not acknowledge the last received byte, but terminates the transfer with a STOP condition. The output data str eam is from consecutive byte ad- dresses, with the internal byte address counter automatically incremented after one byte output.

6.0 I 2C REGISTERS

The following table gives a description of the MPEG Source Decoder (STA015) register list. The first column (HEX_COD) is the hexadecimal code for the sub-address. The second column (DEC_COD) is the decimal code. The third column (DESCRIPTION) is the description of the information contained in the register. The fourth column (RESET) inidicate the reset value if any. When no reset value is specifyed, the default is "undefined". The fifth column (R/W) is the flag to distinguish register "read only" and "read and write", and the useful size of the register itself. Each register is 8 bit wide. The master shall operate reading or writing on 8 bits only. I 2C REGISTERS HEX_COD DEC_COD DESCRIPTION RESET R/W $00 0 VERSION R (8) $01 1 IDENT 0xAC R (8) $05 5 PLLCTL [7:0] 0xA1 R/W (8) $06 6 PLLCTL [20:16] (MF[4:0]=M) 0x0C R/W (8) $07 7 PLLCTL [15:12] (IDF[3:0]=N) 0x00 R/W (8) $0C 12 REQ_POL 0x01 R/W (8) $0D 13 SCLK_POL 0x04 R/W (8) $0F 15 ERROR_CODE 0x00 R (8) $10 16 SOFT_RESET 0x00 W (8) $13 19 PLAY 0x01 R/W(8) $14 20 MUTE 0x00 R/W(8) $16 22 CMD_INTERRUPT 0x00 R/W(8) $18 24 DATA_REQ_ENABLE 0x00 R/W(8) $40 - $51 64 - 81 ADPCM_DATA_1 to ADPCM_DATA_18 0x00 R (8) $40 64 SYNCSTATUS 0x00 R (8) $41 65 ANCCOUNT_L 0x00 R (8) $42 66 ANCCOUNT_H 0x00 R (8) $43 67 HEAD_H[23:16] 0x00 R(8) $44 68 HEAD_M[15:8] 0x00 R(8)

Obsolete Product(s) - Obsolete Product(s) STA015 Notes: 1. The HEX_COD is the hexadecimal adress that the mi crocontroller has to generate to access the information. 2. RESERVED: register used for production test only, or for future use. $45 69 HEAD_L[7:0] 0x00 R(8) $46 70 DLA 0x00 R/W (8) $47 71 DLB 0xFF R/W (8) $48 72 DRA 0x00 R/W (8) $49 73 DRB 0xFF R/W (8) $4D 77 CHIP_MODE 0x00 R/W (2) $4E 78 CRCR 0x00 R/W (1) $50 80 MFSDF_441 0x00 R/W (8) $51 81 PLLFRAC_441_L 0x00 R/W (8) $52 82 ADPCM_DATA_READY 0x00 R/W (1) $52 82 PLLFRAC_441_H 0x00 R/W (8) $53 83 ADPCM_SAMPLE_FREQ 0x00 R/W (4) $54 84 PCM DIVIDER 0x03 R/W (8) $55 85 PCMCONF 0x21 R/W (8) $56 86 PCMCROSS 0x00 R/W (8) $61 97 MFSDF (X) 0x07 R/W (8) $63 99 DAC_CLK_MODE 0x00 R/W (8) $64 100 PLLFRAC_L 0x46 R/W (8) $65 101 PLLFRAC_H 0x5B R/W (8) $67 103 FRAME_CNT_L 0x00 R (8) $68 104 FRAME_CNT_M 0x00 R (8) $69 105 FRAME_CNT_H 0x00 R (8) $6A 106 AVERAGE_BITRATE 0x00 R (8) $71 113 SOFTVERSION R (8) $72 114 RUN 0x00 R/W (8) $77 119 TREBLE_FREQUENCY_LOW 0x00 R/W (8) $78 120 TREBLE_FREQUENCY_HIGH 0x00 R/W (8) $79 121 BASS_FREQUENCY_LOW 0x00 R/W (8) $7A 122 BASS_FREQUENCY_HIGH 0x00 R/W (8) $7B 123 TREBLE_ENHANCE 0x00 R/W (8) $7C 124 BASS_ENHANCE 0x00 R/W (8) $7D 125 TONE_ATTEN 0x00 R/W (8) $7E - B5 126 - 181 ANC_DATA_1 to ANC_DATA_56 0x00 R (8) $B6 182 ISR 0x00 R/W (1) $B8 184 ADPCM_CONFIG 0x00 R/W (2) $B9 185 GPSO_ENABLE 0x00 R/W (1) $BA 186 GPSO_CONF 0x00 R/W (2) $BB 187 ADC_ENABLE 0x00 R/W (1) $BC 188 ADC_CONF 0x00 R/W (5) $BD 189 ADPCM_FRAME_SIZE 0x00 R/W (8) $BE 190 ADPCM_INT_CFG 0x00 R/W (8) $BF 191 GPIO_CONF 0x00 R/W (2) $C0 192 ADC_ WLEN 0x0F R/W (5) $C1 193 ADC_ WPOS 0x00 R/W (5) $C2 194 ADPCM_SKIP_FRAME 0x00 R/W (8) I2C REGISTERS

Obsolete Product(s) - Obsolete Product(s) STA015

6.1 STA015 REGISTERS DESCRIPTION

The STA015 device includes 128 I2C registers. In this document, only the user-oriented registers are de- scribed. The undocumented registers are reserved. These registers must never be accessed (in Read or in Write mode). The Read-Only registers must never be written. The following table describes the meaning of the abbreviations used in the I2C registers description: VERSION Address: 0x00 (00) Type: RO The VERSION register is read-only and it is used to identify the IC on the application board. IDENT Address: 0x01 Type: RO Software Reset: 0xAC Hardware Reset: 0xAC IDENT is a read-only register and is used to identify the IC on an application board. IDENT always has the value "0xAC" PLLCTL Address: 0x05 Type: R/W Software Reset: 0x21 Hardware Reset: 0x21 Symbol Comment NA Not Applicable UND Undefined NC No Charge RO Read Only WO Write Only R/W Read and Write R/WS Read, Write in specific mode MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 V8 V7 V6 V5 V4 V3 V2 V1 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 10101100 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XTO_BUF XTODIS OCLKEN SYS2OCLK PPL DIS XTI2DSPCLK XTI2OCLK UPD_FRAC

Obsolete Product(s) - Obsolete Product(s) STA015 UPD_FRAC: when is set to 1, update FRAC in the switching circuit. It is set to 1 after autoboot. XTI2OCLK: when is set to 1, use the XTI as input of the divider X instead of VCO output. It is set to 0 on HW reset. XTI2DSPCLK: when is to 1, set use the XTI as input of t he divider S instead of VCO output. It is set to 0 on HW reset. PLLDIS: when set to 1, the VCO output is disabled. It is set to 0 on HW reset. SYS2OCLK: when is set to 1, the OCLK frequency is equal to the system frequency. It is useful for testing. It is set to 0 on HW reset. OCLKEN: when is set to 1, the OCLK pad is enable as output pad. It is set to 1 on HW reset. XTODIS: when is set to 1, the XTO pad is disable. It is set to 0 on HW reset. XTO_BUF: when this bit is set, the pin nr. 28 (OUT_CLO CK/DATA_REQ) is enabled. It is set to 0 after autoboot. PLLCTL (M) Address: 0x06 (06) Type: R/W Software Reset: 0x0C Hardware Reset: 0x0C PLLCTL (N) Address: 0x07 (07) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 The M and N registers are used to configure the STA015 PLL by DSP embedded software. M and N registers are R/W type but they are completely controlled, on STA015, by DSP software. REQ_POL Address: 0x0C (12) Type: R/W Software Reset: 0x01 Hardware Reset: 0x00 The REQ_POL registers is used to program the polarity of the DATA_REQ line. D efault polarity (the source sends data when the DATA_REQ line is high) Inverted polarity (the source sends data when the ATA_REQ line is low) MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 00000001 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 00000101

Obsolete Product(s) - Obsolete Product(s) STA015 SCKL_POL Address: 0x0D (13) Type: R/W Software Reset: 0x04 Hardware Reset: 0x04 X = don’t care SCKL_POL is used to select the working polarity of the Input Serial Clock (SCKR). (1) If SCKL_POL is set to 0x00, the data (SDI) are sent with the falling edge of SCKR and sampled on the rising edge. (2) If SCKL_POL is set to 0x04, the data (SDI) are sent with the rising edge of SCKR and sampled on the falling edge. ERROR_CODE Address: 0x0F (15) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 X = don’t care ERROR_CODE register contains the last error occourred if any. The codes can be as follows: MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XXXXX000 ( 1 ) 100 ( 2 ) MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 X X EC5 EC4 EC3 EC2 EC1 EC0 CODE Description 0x00 No error since the last SW or HW Reset 0x01 CRC Failure 0x02 DATA not available 0x04 Ancillary data not read 0x10 Audio synch word not found 0x2X MPEG Header error 0x3X MPEG Decoding errors

Obsolete Product(s) - Obsolete Product(s) STA015 SOFT_RESET Address: 0x10 (16) Type: WO Software Reset: 0x00 Hardware Reset: 0x00 X = don’t care; 0 = normal operation; 1 = reset When this register is written, a soft reset occours. The STA015 core command register and the interrupt register are cleared. The decoder goes in to idle mode. PLAY Address: 0x13 (19) Type: R/W Software Reset: 0x01 Hardware Reset: 0x01 X = don’t care; 0 = normal operation; 1 = play The PLAY command is handled according to the state of the decoder, as described in section 2.5. PLAY only becomes active when the decoder is in DECODE mode. MUTE Address: 0x14 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 X = don’t care; 0 = normal operation; 1 = mute The MUTE command is handled according to the state of the decoder, as described in section 2.5. MUTE sets the clock running. MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XXXXXXX0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XXXXXXX0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XXXXXXX0

Obsolete Product(s) - Obsolete Product(s) STA015 CMD_INTERRUPT Address: 0x16 (22) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 X = don’t care; 0 = normal operation; 1 = write into I 2C/Ancillary Data The INTERRUPT is used to give STA015 the command to write into the I2C/Ancillary Data Buffer (Regis- ters: 0x7E ... 0xB5). Every time the Master has to extract the new buffer content it writes into this register, setting it to a non-zero value. DATA_REQ_ENABLE Address: 0x18 (24) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 The DATA_REQ_ENABLE register is used to configure Pin n. 28 working as buffered output clock or data request signal, used for multimedia mode. The buffered Output Clock has the same frequency than the input clock (XTI) SYNCSTATUS Address: 0x40 (64) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XXXXXXX0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description XXXXX0XXb u f f e r e d o u t p u t c l o c k XXXXX1XX r e q u e s t s i g n a l MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description XXXXXX S S 1 S S 0 0 0 Research of sync word 0 1 Wait for Confirmation 1 0 Synchronised

Obsolete Product(s) - Obsolete Product(s) STA015 ADPCM_DATA BUFFER Address: 0x40 - 0x51 (64 - 81) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 ANCCOUNT_L Address: 0x41 (65) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 ANCCOUNT_H Address: 0x42 (66) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 ANCCOUNT_H ANCCOUNT registers are logically concatenated and indicate the number of Ancillary Data bits available at every correctly decoded MPEG frame. HEAD_H[23:16] x = don’t care MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 ENCODED DATA N to N+18 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 AC15 AC14 AC13 AC12 AC11 AC10 AC9 AC8 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 X X X H20 H19 H18 H17 H16

Obsolete Product(s) - Obsolete Product(s) STA015 HEAD_M[15:8] HEAD_L[7:0] Address: 0x43, 0x44, 0x45 (67, 68, 69) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 Head[1:0] emphasis Head[2] original/copy Head[3] copyrightHead [5:4] mode extension Head[7:6] mode Head[8] private bit Head[9] padding bit Head[11:10] sampling frequency index Head[15:12] bitrate index Head[16] protection bit Head[18:17] layer Head[19] ID Head[20] ID_ex The HEAD registers can be viewed as logically concatenated to store the MPEG Layer III Header content. The set of three registers is updated every time the synchronisation to the new MPEG frame is achieved The meaning of the flags are shown in the following tables: MPEG IDs Layer in Layer III these two flags must be set always to "01". Protection_bit It equals "1" if no redundancy has been added and "0" if redundancy has been added. MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 H15 H14 H13 H12 H11 H10 H9 H8 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 H7 H6 H5 H4 H3 H2 H1 H0 IDex ID 00 M P E G 2 . 5 01 r e s e r v e d 1 0 MPEG 2 1 1 MPEG 1

Obsolete Product(s) - Obsolete Product(s) STA015 Bitrate_index indicates the bitrate (Kbit/sec) depending on the MPEG ID. Sampling Frequency indicates the sampling frequency of the encoded audio signal (KHz) depending on the MPEG ID Padding bit if this bit equals ’1’, the frame contains an additional slot to adjust the mean bitrate to the sampling fre- quency, otherwise this bit is set to ’0’. Private bit Bit for private use. This bit will not be used in the future by ISO/IEC. Mode Indicates the mode according to the following tabl e. The joint stereo mode is intensity_stereo and/or ms_stereo. bitrate index ID = 1 ID = 0 ’0000’ free free ’0001’ 32 8 ’0010’ 40 16 ’0011’ 48 24 ’0100’ 56 32 ’0101’ 64 40 ’0110’ 80 48 ’0111’ 96 56 ’1000’ 112 64 ’1001’ 128 80 ’1010’ 160 96 ’1011’ 192 112 ’1100’ 224 128 ’1101’ 256 144 ’1110’ 320 160 ’1111’ forbidden forbidden Sampling Frequency MPEG1 MPEG2 MPEG2.5 ’00’ 44.1 22.05 11.03 ’01’ 48 24 12 ’10’ 32 16 8 ’11’ reserved reserved reserved mode mode specified ’00’ stereo ’01’ joint stereo (intensity_stereo and/or ms_stereo) ’10’ dual_channel ’11’ single_channel (mono)

If this bit is equal to ’0’, there is no copyright on the bitstream, ’1’ means copyright protected. This bit equals ’0’ if the bitstream is a copy, ’1’ if it is original. Indicates the type of de-emphasis that shall be used. Fig. 18. When the register is set to 255 (0xFF), the maximum attenuation is achieved. A decimal unit correspond to an attenuation step of 1 dB. Figure 18. Volume Control and Output Setup

Obsolete Product(s) - Obsolete Product(s) STA015 DLB Address: 0x47 (71) Type: R/W Software Reset: 0xFF Hardware Reset: 0xFF DLB register is used to re-direct the Left Channel on the Right, or to mix both the Channels. Default value is 0x00, corresponding at the maximum attenuation in the re-direction channel. DRA Address: 0x48 (72) Type: R/W Software Reset: 0X00 Hardware Reset: 0X00 DRA register is used to attenuate the level of audio output at the Right Channel using the butterfly shown in Fig. 11. When the register is set to255 (0xFF), the maximum attenuation is achieved. A decimal unit correspond to an attenuation stepof 1 dB. MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description DLB7 DLB6 DLB5 DLB4 DLB3 DLB2 DLB1 DLB0 OUTPUT ATTENUATION

00000000 N O A T T E N U A T I O N

:::::::: : 01100000 - 9 6 d B MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description DRA7 DRA6 DRA5 DRA4 DRA3 DRA2 DRA1 DRA0 OUTPUT ATTENUATION 0 000000 0 N O A T T E N U A T I O N 0 000000 1 - 1 d B 0 000001 0 - 2 d B : :::::: : : 0 110000 0 - 96dB

Obsolete Product(s) - Obsolete Product(s) STA015 DRB Address: 0x49 (73) Type: R/W Software Reset: 0xFF Hardware Reset: 0xFF DRB register is used to re-direct the Right Channel on the Left, or to mix both the Channels. Default value is 0x00, corresponding at the maximum attenuation in the re-direction channel. CHIP_MODE Address: 0x4D (77) Type: R/W Hardware Reset: 0x00 Using this register it’s possible to select which operation will be performed by the DSP. Possible values are: 0x00 - MP3 decoding 0x01 - Reserved 0x02 - ADPCM Encoder 0x03 - ADPCM Decoder 0x04 - BYPASS mode The DSP will check for the value of this register right after the RUN command has been issued (refer to RUN register). After that no more checks will be performed: therefore a SOFT_RESET must be generated in order to change the device mode. CRCR Address: 0x4E (78) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 The CRC register is used to enable/disable the CRC check. If CRC_EN bit is cleared, the CRC value en- coded in the bitstream is checked against the hardware one. If a discrepance occurs, the current frame is skipped and the decoder is muted. The ERROR_CODE register is affected with the value 0x01. MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description DRB7 DRB6 DRB5 DRB4 DRB3 DRB2 DRB1 DRB0 OUTPUT ATTENUATION 0 000000 0 N O A T T E N U A T I O N 0 000000 1 - 1 d B 0 000001 0 - 2 d B : :::::: : : 0 110000 0 - 96dB MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XXXXXXX CRCEN

Obsolete Product(s) - Obsolete Product(s) STA015 If CRC_EN bit is set, the result of the CRC check is ignored, but the ERROR_CODE register is neverthe- less affected with the value 0x01 if a discrepance has occurred. MFSDF_441 Address: 0x50 (80) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 This register contains the value for the PLL X driver for the 44.1KHz reference frequency. The VCO output frequency, when decoding 44.1KHz bitstream, is divided by (MFSDF_441 +1) PLLFRAC_441_L Address: 0x51 (81) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 ADPCM_DATA_READY Address: 0x52 (82) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 ADR: Adpcm Data Ready This bit signal ADPCM encoded data are ready to be retrieved. PLLFRAC_441_H Address: 0x52 (82) Type: R/W Software Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 X X X M 4M 3M 2M 1M 0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XXXXXXX A D R

Obsolete Product(s) - Obsolete Product(s) STA015 Hardware Reset: 0x00 The registers are considered logi cally concatenated and contain the fr actional values for the PLL, for 44.1KHz reference frequency. (see also PLLFRAC_L and PLLFRAC_H registers) ADPCM_SAMPLE_FREQ Address: 0x53 (83) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 ADPCM_SF: Adpcm Sample Frequency PCMDIVIDER Address: 0x54 (84) Type: RW Software Reset: 0x01 Hardware Reset: 0x01 PCMDIVIDER is used to set the frequency ratio between the OCLK (Oversampling Clock for DACs), and the SCKT (Serial Audio Transmitter Clock). The relation is the following: The Oversampling Factor (O_FAC) is related to OCLK and SCKT by the following expression: 1) OCLK_freq = O_FAC * LRCKT_ Freq (DAC relation) 2) OCLK_ Freq = 2 * (1+PCM_DIV) * 32* LRCKT_Freq (when 16 bit PCM mode is used) 3) OCLK_ Freq = 2 * (1+PCM_DIV) * 64* LRCKT_Freq (when 32 bit PCM mode is used) MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 PF15 PF14 PF13 PF12 PF11 PF10 PF19 PF8 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 X X X ADPCM_SF 0x02 8KHz 0x0A 16KHz 0x0E 32KHz MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 SCKT_freq OCLK_freq

Obsolete Product(s) - Obsolete Product(s) STA015 4) PCM_DIV = (O_FAC/64) - 1 in 16 bit mode 5) PCM_DIV = (O_FAC/128) - 1 in 32 bit mode Example for setting: PCMCONF Address: 0x55 (85) Type: R/W Software Reset: 0x21 Hardware Reset: 0x21 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 0 0000111 1 6 b i t m o d e5 1 2 x F s 0 0000101 1 6 b i t m o d e3 8 4 x F s 0 0000011 1 6 b i t m o d e2 5 6 x F s 0 0000011 3 2 b i t m o d e5 1 2 x F s 0 0000010 3 2 b i t m o d e3 8 4 x F s 0 0000001 3 2 b i t m o d e2 5 6 x F s for 16 bit PCM Mode for 32 bit PCM Mode O_FAC = 512 ; PCM_DIV = 7 O_FAC = 512 ; PCM_DIV = 3 O_FAC = 256 ; PCM_DIV = 3 O_FAC = 256 ; PCM_DIV = 1 O_FAC = 384 ; PCM_DIV = 5 O_FAC = 384 ; PCM_DIV = 2 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description X ORD DIF INV FOR SCL PREC (1) PREC (1) X 1 PCM order the LS bit is transmitted First X 0 PCM order the MS bit is transmitted First X 0 The word is right aligned X 1 The word is left aligned X0 LRCKT Polarity compliant to I 2S format X 1 LRCKT Polarity inverted X0 I2S format X 1 Different formats X 1 Data are sent on the rising edge of SCKT X 0 Data are sent on the falling edge of SCKT X 0 0 16 bit mode (16 slots transmitted) X 0 1 18 bit mode (32 slots transmitted) X 1 0 20 bit mode (32 slots transmitted) X 1 1 24 bit mode (32slots transmitted)

Obsolete Product(s) - Obsolete Product(s) STA015 PCMCROSS Address: 0x56 (86) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 The default configuration for this register is ’0x00’. MFSDF (X) Address: 0x61 (97) Type: R/W Software Reset: 0x07 Hardware Reset: 0x07 The register contains the values for PLL X divider (see Fig. 7). The value is changed by the internal STA015 Core, to set the clocks frequencies, according to the incom- ing bitstream. This value can be even set by the user to select the PCM interface configuration. The VCO output frequency is divided by (X+1). This register is a referenc e for 32KHz and 48KHz input bitstream. DAC_CLK_MODE (99) Address: 0x63 Type: RW Software Reset: 0x00 Hardware Reset: 0x00 This register is used to select the operating mode for OC LK clock signal. If it is set to “1”, the OCLK fre- quency is fixed, and it is mantained to the value fi xed by the user even if the sampling frequency of the incoming bitstream changes. It the MODE flag is set to f0f, the OCLK frequency changes, and can be set to (512, 384, 256) * Fs. The default configuration fo r this mode is 256 * Fs. When this mode is selected, MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description XXXXXX00 L e f t c h a nnel is mapped on the left output. Right channel is mapped on the Right output XXXXXX01 L e f t c h a nnel is duplicated on both Output channels. XXXXXX10 R i g h t c hannel is duplicated on both Output channels XXXXXX11 R i g h t a n d L e f t c h a nnels are toggled MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 X X X M 4M 3M 2M 1M 0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XXXXXXX M O D E

Obsolete Product(s) - Obsolete Product(s) STA015 the default OCLK frequency is 12.288 MHz. PLLFRAC_L ([7:0]) PLLFRAC_H ([15:8]) Address: 0x64 - 0x65 (100 - 101) Type: R/W Software Reset: 0x46 | 0x5B Hardware Reset: 0xNA | 0x5B The registers are considered logically concatenated and contain the fractional values for the PLL, used to select the internal configuration. After Reset, the values are NA, and the operational setting are done when the MPEG synchronisation is achieved. The following formula describes the relationships among all the STA015 fractional PLL parameters: where: FRAC=256 x FRAC_H + FRAC_L (decimal) These registers are a reference for 48 / 24 / 12 / 32 / 16 / 8KHz audio. FRAME_CNT_L FRAME_CNT_M FRAME_CNT_H MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 PF15 PF14 PF13 PF12 PF11 PF10 PF9 PF8 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 FC15 FC14 FC13 FC12 FC11 FC10 FC9 FC8 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 FC23 FC22 FC21 FC20 FC19 FC18 FC17 FC16 OCLK_Freq 1

Obsolete Product(s) - Obsolete Product(s) STA015 Address: 0x67, 0x68, 0x69 (103 - 104 - 105) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 The three registers are considered logically concatenated and compose the Global Frame Counter as de- scribed in the table. It is updated at every decoded MPEG Frame. The registers are reset on both hardware and software reset. AVERAGE_BITRATE Address: 0x6A (106) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 AVERAGE_BITRATE is a read-only register and it contains the average bitrate of the incoming bitstream divided by two. The value is rounded with an accuracy of 1 Kbit/sec. SOFTVERSION Address: 0x71 (113) Type: RO After the STA015 boot, this register contains the version code of the embedded software. RUN Address: 0x72 (114) Type: RW Software Reset: 0x00 Hardware Reset: 0x00 Setting this register to 1, STA015 leaves the idle state, starting the decoding process. The Microcontroller is allowed to set the RUN flag, once all the control registers have been initialized. MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 SV7 SV6 SV5 SV4 SV3 SV2 SV1 SV0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XXXXXXX R U N

Obsolete Product(s) - Obsolete Product(s) STA015 TREBLE_FREQUENCY_LOW Address: 0x77 (119) Type: RW Software Reset: 0x00 Hardware Reset: 0x00 TREBLE_FREQUENCY_HIGH Address: 0x78 Type: RW Software Reset: 0x00 Hardware Reset: 0x00 The registers TREBLE_FREQUENCY-HIGH and TR EBLE_FREQUENCY-LOW, logically concatenated as a 16 bit wide register, are used to select the frequency, in Hz, where the selected frequency is +12dB respect to the stop band. By setting these registers, the following rule must be kept: Treble_Freq < Fs/2 BASS_FREQUENCY_LOW Address: 0x79 (121) Software Reset: 0x00 Hardware Reset: 0x00 BASS_FREQUENCY_HIGH Address: 0x7A (122) Software Reset: 0x00 Hardware Reset: 0x00 The registers BASS_FREQUENCY_HIGH and BASS_FREQ UENCY_LOW, logically concatenated as a 16 bit wide register, are used to select the frequency, in Hz, where the selected frequency is -12dB respect to the pass-band. By setting the BASS_FREQUENCY registers, the following rules must be kept: MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 TF7 TF6 TF5 TF4 TF3 TF2 TF1 TF0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 TF15 TF14 TF13 TF12 TF11 TF10 TF9 TF8 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 BF7 BF6 BF5 BF4 BF3 BF2 BF1 BF0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 BF15 BF14 BF13 BF12 BF11 BF10 BF9 BF8

Obsolete Product(s) - Obsolete Product(s) STA015 Bass_Freq <= Treble_Freq Bass_Freq > 0 (suggested range: 20 Hz < Bass_Freq < 750 Hz) Example: Bass = 200Hz Treble = 3kHz TFS BFS TREBLE_ENHANCE Address: 0x7B (123) Software Reset: 0x00 Hardware Reset: 0x00 Signed number (2 complement) This register is used to select the enhancement or attenuation STA015 has to perform on Treble Frequen- cy range at the digital signal. A decrement (increment) of a decimal unit corresponds to a step of attenuation (enhancement) of 1.5dB. The allowed Attenuation/Enhancement range is [-18dB, +18dB]. 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 0000101110111000 1 5 1 4 1 3 1 2 1 1 1 0 9876543210 0000000011001000 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 TE7 TE6 TE5 TE4 TE3 TE2 TE1 TE0 MSB LSB ENHANCE/ATTENUATION b7 b6 b5 b4 b3 b2 b1 b0 1.5dB step 00001100 + 1 8 00001011 + 1 6 . 5 00001010 + 1 5 00001001 + 1 3 . 5 00000001 + 1 00000000 0 11111111 - 1 11110111 + 1 3 . 5 11110110 - 1 5 11110100 - 1 6 . 5 11110100 - 1 8

Obsolete Product(s) - Obsolete Product(s) STA015 BASS_ENHANCE Address: 0x7C (1240 Software Reset: 0x00 Hardware Reset: 0x00 Signed number (2 complement) This register is used to select the enhancement or attenuation STA015 has to perform on Bass Frequency range at the digital signal. A decrement (increment) of a decimal unit corresponds to a step of attenuation (enhancement) of 1.5dB. The allowed Attenuation/Enhancement range is [-18dB, +18dB]. TONE_ATTEN Address: 0x7D (125) Type: RW Software Reset: 0x00 Hardware Reset: 0x00 In the digital output audio, the full signal is achieved with 0 dB of attenuation. For this reason, before ap- plying Bass & Treble Control, the user has to set the TONE_ATTEN register to the maximum value of en- MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 BE7 BE6 BE5 BE4 BE3 BE2 BE1 BE0 MSB LSB ENHANCE/ATTENUATION b7 b6 b5 b4 b3 b2 b1 b0 1.5dB step 00001100 + 1 8 00001011 + 1 6 . 5 00001010 + 1 5 00001001 + 1 3 . 5 00000001 + 1 00000000 0 11111111 - 1 11110111 + 1 3 . 5 11110110 - 1 5 11110100 - 1 6 . 5 11110100 - 1 8 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0

Obsolete Product(s) - Obsolete Product(s) STA015 hancement is going to perform. For example, in case of a 0 dB signal (max. leve l) only attenuation would be possible. If enhancement is desired, the signal has to be attenuated accordingly before in order to reserve a margin in dB. An increment of a decimal unit corresponds to a Tone Attenuation step of 1.5dB. ANCILLARY DATA BUFFER Address: 0x7E - 0xB5 (126 - 181) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 The STA015 contains 56 consecutive 8-bit register s corresponding to the maximum number of ancillary data that may be contained in MPEG frame. The ANCCOUNT_L and ANCOUNT_H registers contain the number of ancillary data bits available within the current MPEG frame. To perform ancillary data reading a status register (0xB6 - INTERRUPT_STATUS_REGISTER) is avail- able: bit 0 of this register shoul d be polled by the micr ocontroller in order to understand when new data are available. ISR Address: 0xB6 (182) Type: R/W Software Reset: 0x00 MSB LSB ATTENUATION b7 b6 b5 b4 b3 b2 b1 b0 1.5dB step 00000000 0 d B 00000001 - 1 . 5 d B 00001010 3 d B 00000011 4 . 5 d B 00001010 - 1 5 00001011 - 1 6 . 5 00001100 - 1 8 0x7E ANC_DATA_1 0xB5 ANC_DATA_56 0xB6 ISR

Obsolete Product(s) - Obsolete Product(s) STA015 Hardware Reset: 0x00 X = don’t care; 0 = no ancillary data 1 = Ancillary Data Available The ISR is used by the microcontroller to understand when a new ancillary data block is available. After all ancillary data has been retrieved this bit must be cleared. ADPCM_CONFIG Address: 0xB8 (184) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 This register controls ADPCM engine and how data must be compressed. AFM_EN ADPCM Frame Mode Enable 0 = no frames (raw format) 1 = select the framed output format for ADPCM encoded data ASM_EN: ADPCM Stereo Mode Enable 0 = Disable stereo mode 1 = Enable stereo mode AA0,AA1: ADPCM Algorithm selection The ADPC M encoding/decoding algorithm can be selected according to the following table: The above bitrates refers to an 8 KHz 16 bits mono input stream. Please note that 32KHz stereo mode is only available (both in encoding and decoding) with DVI algorithm MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XXXXXXX0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 X X X X AA1 AA0 ASM_EN AFM_EN AA1 AA0 0 0 DVI algorithm 0 1 G723-24 algorithm (24kbp/s) 1 0 G721 algorithm (32kbp/s) 1 1 G723-40 algorithm (40kbp/s)

Obsolete Product(s) - Obsolete Product(s) STA015 GPSO_ENABLE Address: 0xB9 (185) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 This register enable/disable the GPSO interface. Setting the GEN bit will enable the se rial interface for ADPCM data retrieving. Reset GEN bit to disable GPSO interface. GPSO_CONF Address: 0xBA (186) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 GSP: GPSO clock polarity sing this bit the GPSO_SCKR polarity can be controlled. Clearing GSP bit data on GPSO_DATA line will be provided on the ri sing edge of GPSO_SCKR (sampling on falling edge). Setting GSP bit data are provided on falling edge of GPSO_SCKR (sampling on rising edge) GRP: GPSO Request Polarity This bit is used to determine the polarity of GPSO_REQ signal. If GRP bit is cleared data are valid on GPSO_REQ signal high. If this bit is set data are valid on GPSO_REQ signal low ADC_ENABLE Address: 0xBB (187) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 This register controls if the ADPCM data to be encoded comes from A/D interface or from MP3 bitstream input interface. If ADCEN bit is set data to be encoded comes from ADC interface, otherwise data comes from MP3 stream interface MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XXXXXXX G E N MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XXXXXX G R P G S P MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XXXXXXX A D C E N

Obsolete Product(s) - Obsolete Product(s) STA015 ADC_CONF Address: 0xBC (188) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 Using this register the ADC input interface can be configured as follow: AIIS: ADC I 2S mode 0 = sample word must be aligned with LRCK (no I2S mode) 1 = sample word not aligned with LRCK (I2S compliant mode) ADC: ADC Data Config. 0 = sample word is LSB first 1 = sample word is MSB first ASCP: ADC Serial Clock Polarity 0 = Data is sampled on rising edge 1 = Data is sampled an falling edge ALRCP: ADC Left/Right Clock Polarity ALRCS: ADC Left/Right Clock Start value. This two bits permit to determine Left/Right clock usage according to the following table: MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 X X X ALRCS ALRCP ASCP ADC AIIS ALRCP ALRCS LEFT/RIGHT COUPLE 0 0 (Data1, Data2) (Data3, Data4) 1 0 (0, 1) (2, 3) 0 1 (0, 1) (2, 3) 1 1 (1, 2) (3, 4) DATA 0 LRCK DATA DATA 1 DATA 2 DATA 3 DATA 4 D99AU1065

Obsolete Product(s) - Obsolete Product(s) STA015 ADPCM_FRAME_SIZE Address: 0xBD (189) Type: R/W Software Reset: 0x13 Hardware Reset: 0x00 The ADPCM frame size may be adjusted to match a trade-off between the bitrate overhead and the frame length. The frame size (in bytes) is calculated as follow: FRAME size = (ADPCM_FRAME_SIZE * 90) +108 The frame starts with a 12 bytes header: – 6 bytes for DVI algorithm – 96 bytes for G726 pack algorithms ADPCM_INT_CFG Address: 0xBE (190) Type: R/W Software Reset: 0x0B Hardware Reset: 0x00 Using this register the ADPCM in terrupt capability can be properly configured. INTL0 - INTL6 Interrupt Length he interrupt length can be programmed, using this bits, from 0 up to 128 system clock cycles GPIO_CONF Address: 0xBF (191) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 This register controls how data are strobed on the GPIO interface. GISP: GPIO Strobe Polarity in INPUT mode 0 = data strobed an falling edge 1 = data strobed on rising edge GOSP: GPIO Strobe Polarity in OUTPUT mode 0 = non inverted 1 = inverted MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 AFS7 AFS6 AFS5 AFS4 AFS3 AFS2 AFS1 AFS0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 INTL6 INTL5 INTL4 INTL3 INTL2 INTL1 INTL0 X MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XXXXXX G O S P G I S P

Obsolete Product(s) - Obsolete Product(s) STA015 ADC_WLEN Address: 0xC0 (192) Type: R/W Software Reset: 0x0F Hardware Reset: 0x0F To select ADC word length AWL4 through AWL0 bits can be used. This 5 bit value must contain the size of the significant data bits minus one. ADC_WPOS Address: 0xC1 (193) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 These bits specify the position of the sample word referred to the LRCK slot boundary. Bit AWP0 thru AWP4 must be programmed with the number of bits to ignore after the sample word. ADPCM_SKIP_FRAME Address: 0xC2 (194) Type: R/W Software Reset:0x00 Hardware Reset: 0x00 This register is useful when decoding ADPCM frame-based streams in order to skip the specified number of frames. The content of the register will automatically be decremented on each new frame and the skip process will continue until the content reaches zero. MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 X X X AWL4 AWL3 AWL2 AWL1 AWL0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 X X X AWP4 AWP3 AWP2 AWP1 AWP0 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 ASF7 ASF6 ASF5 ASF4 ASF3 ASF2 ASF1 ASF0

Obsolete Product(s) - Obsolete Product(s) STA015

6.2 I/O CELL DESCRIPTION (pinout relative to TQFP44 package)

1) CMOS Tristate Output Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 2, 4, 13, 27, 33, 42, 44 2) CMOS Bidir Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 3, 31 3) CMOS Inpud Pad Buffer / Pin numbers 24, 26, 32, 34, 36, 40 4) CMOS Inpud Pad Buffer with Active Pull-Up / Pin numbers 22, 25, 28, 38 5) CMOS Schmitt Trigger Bidir Pad Buffer with active Pull-up, 4mA, with slew rate control/ Pin numbers 14, 16, 18, 20, 35, 37, 39, 41, 43 EN A D98AU904 Z OUTPUT PIN MAX LOAD Z 100pF EN A D98AU905 ZI IO INPUT PIN CAPACITANCE OUTPUT PIN MAX LOAD IO 5pF IO 100pF A D98AU906 Z INPUT PIN CAPACITANCE A3 . 5 p F A D98AU907 Z INPUT PIN CAPACITANCE A3 . 5 p F EN A D00AU1150 ZI IO INPUT PIN CAPACITANCE OUTPUT PIN MAX LOAD IO 5pF IO 100pF

Obsolete Product(s) - Obsolete Product(s) STA015

6.3 TIMING DIAGRAMS

6.3.1 Audio DAC Interface

a) OCLK in output. The audio PLL is used to clock the DAC tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing (Cload_ OCLK) tsckt = 4 + pad_timing (Cload_SCKT) - pad_timing (Cload_ OCLK) tlrckt = 3.5 + pad_timing (Cload_LRCCKT) - pad_timing (Cload_ OCLK) Pad-timing versus load Cload_XXX is the load in pF on the XXX output. pad_timing (Cload_XXX) is the propagation delay added to the XXX pad due to the load. b) OCLK in input. Load (pF) Pad_timing 25 2.90ns 50 3.82ns 75 4.68ns 100 5.52ns OCLK (OUTPUT) SDO SCKT LRCLK tsdo tsckt tlrclk D98AU969 OCLK (INPUT) SDO SCKT LRCLK tsdo tsckt tlrclk D98AU970 thi tlo toclk

Obsolete Product(s) - Obsolete Product(s) STA015 Thi min = 3ns Tlo min = 3ns Toclk min = 25ns tsdo = 5.5 + pad_timing (Cload_SDO) ns tsckt = 6 + pad_timing (Cload_SCKT) ns tlrckt = 5.5 + pad_timing (Cload_LRCKT) ns

6.3.2 Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 0

6.3.3 Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 1

tsdi_setup_min = 2ns tsdi_hold_min = 3ns tsckr_min_hi = 10ns tsckr_min_low = 10ns tsckr_min_lperiod = 50ns t_biten (min) = 2ns

6.3.4 SRC_INT

This is an asynchronous input used in "broadcast’ mode. SRC_INT is active low t_src_low min duration is 50ns (1DSP clock period) t_src_high min duration is 50ns (1DSP clock period) SDI SCKR IGNORED VALID IGNORED t_biten t_biten tsdi_holdtsdi_setup D98AU971A tsckr_min_high BIT_EN SCLK_POL=0tsckr_min_low tsckr_min_period SDI SCKR IGNOREDIGNORED VALID IGNORED t_biten t_biten tsdi_holdtsdi_setup D99AU1038 tsckr_min_high BIT_EN SCLK_POL=4tsckr_min_low tsckr_min_period SRC_INT D98AU972 t_src_hi t_src_low

Obsolete Product(s) - Obsolete Product(s) STA015

6.3.5 XTI,XTO and CLK_OUT timings

txto = 1.40 + pad_timing (Cload_XTO) ns tclk_out = 4 + pad_timing (Cload_CLK_OUT) ns Note: In "multimedia" mode, the CLK_OUT pad is DATA_REQ. In that case, no timing is given between the XTI input and this pad.

6.3.6 RESET

The Reset min duration (t_reset_low_min) is 100ns

6.4 CONFIGURATION FLOW EXAMPLE

XTI (INPUT) XTO CLK_OUT txto tclk_out D98AU973 thi tlo RESET D98AU974 treset_low_min HW RESET set PCM OUTPUT INTERFACE CONFIGURATION set set PCM-DIVIDER PCM-CONF. PLL FRAC_441_H, PLL FRAC_441_L, PLL FRAC_H, PLL FRAC_L } set MFS DF_441, MFSDF } PLL CONFIGURATION FOR: set PLL CTRL 48, 44.1, 32 29, 22.05, 16 12, 11.025, 8 } KHz

• { set SCKR_POL INPUT SERIAL CLOCK POLARITY CONFIGURATION set CHIP_MODE SELECT OPERATIONAL MODEset REQ_POL DATA REQUEST POLARITY CONFIGURATION RUNset
• MULTIMEDIA MODE see {TAB 5 to TAB12} D00AU1146A

Obsolete Product(s) - Obsolete Product(s) STA015 Table 2. PLL Configuration Sequence For 10MHz Input Clock

256 Oversapling Clock

Table 3. PLL Configuration Sequence For 10MHz Input Clock

384 Oversapling Rathio

Table 4. PLL Configuration Sequence For 14.31818MHz Input Clock

256 Oversapling Rathio

Table 5. PLL Configuration Sequence For 14.31818MHz Input Clock

97 MFSDF (x) 15

80 MFSDF-441 16

101 PLLFRAC-H 169

82 PLLFRAC-441-H 49

100 PLLFRAC-L 42

81 PLLFRAC-441-L 60

97 MFSDF (x) 9

80 MFSDF-441 10

101 PLLFRAC-H 110

82 PLLFRAC-441-H 160

100 PLLFRAC-L 152

81 PLLFRAC-441-L 186

101 PLLFRAC-H 187

82 PLLFRAC-441-H 103

100 PLLFRAC-L 58

81 PLLFRAC-441-L 119

5 PLLCTRL 161

97 MFSDF (x) 6

80 MFSDF-441 7

101 PLLFRAC-H 3

82 PLLFRAC-441-H 157

100 PLLFRAC-L 211

81 PLLFRAC-441-L 157

Obsolete Product(s) - Obsolete Product(s) STA015 Table 6. PLL Configuration Sequence For 14.31818MHz Input Clock

512 Oversapling Rathio

Table 7. PLL Configuration Sequence For 14.7456MHz Input Clock Table 8. PLL Configuration Sequence For 14.7456MHz Input Clock Table 9. PLL Configuration Sequence For 14.7456MHz Input Clock

101 PLLFRAC-H 85

82 PLLFRAC-441-H 4

100 PLLFRAC-L 85

81 PLLFRAC-441-L 0

97 MFSDF (x) 8

80 MFSDF-441 9

101 PLLFRAC-H 64

82 PLLFRAC-441-H 124

100 PLLFRAC-L 0

97 MFSDF (x) 5

80 MFSDF-441 6

101 PLLFRAC-H 0

82 PLLFRAC-441-H 184

Obsolete Product(s) - Obsolete Product(s) STA015

6.5 STA015 CONFIGURATION FILE FORMAT

The STA015 Configuration File is an ASCII format. An example of the file format is the following: 58 1 42 4 128 15 It is a sequence of rows and each one can be interpreted as an I 2C command. The first part of the row is the I2C address (register) and the second one is the I 2C data (value). To download the STA015 configu- ration file into the device, a sequence of write operation to STA015 I2C interface must be performed. The following program describes the I2C routine to be implemented for the configuration driver: STA015 Configuration Code (pseudo code) download cfg - file fopen (cfg_file); fp:=1; /*set file pointer to first row */ do { I 2C_start_cond; /* generate I 2C start condition for STA015 device address */ I2C_write_dev_addr; /* write STA015 device address */ I2C_write_subaddress (fp); /* write subaddress */ I2C_write_data (fp); /* write data */ I2C_stop_cond; /* generate I 2C stop condition */ fp++; /* update pointer to new file row */ while (!EDF) /* repeat until End of File */ } /* End routine */ Note: 1. STA015 is a device based on an integrated DSP core. Some of the I 2C registers default values are loaded after an internal DSP boot operation. The bootstrap time is 60 micro second. Only after this time lenght, the data in the register can be considered stable 2. Refer also to the application note AN1250 42 4 I2C REGISTER VALUE I2C SUB-ADDRESS D98AU976

Obsolete Product(s) - Obsolete Product(s) STA015 SO-28 DIM. mm inch A 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 0.020 c1 45 ° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 S8 ° (max.) OUTLINE AND MECHANICAL DATA

Obsolete Product(s) - Obsolete Product(s) STA015 OUTLINE AND MECHANICAL DATA DIM. mm inch A 1.60 0.063 A1 0.05 0.15 0.002 0.006 C 0.09 0.20 0.004 0.008 D3 8.00 0.315 E3 8.00 0.315 e 0.80 0.031 L1 1.00 0.039 k 0˚(min.), 3.5˚(typ.), 7˚(max.) TQFP44 (10 x 10 x 1.4mm) A A1B Seating Plane C 2333 E D e K B TQFP4410 L 0.10mm .004 0076922 D

Obsolete Product(s) - Obsolete Product(s) STA015 OUTLINE AND MECHANICAL DATA D1 D A 0.15 A2e f f A 12345678 B C D E F G H φ b (64 PLACES) E BALL 1 IDENTIFICATION LFBGA64M DIM. mm inch A 1.700 0.067 A2 1.100 0.043 b 0.500 0.20 D 8.000 0.315 D1 5.600 0.220 e 0.800 0.031 E 8.000 0.315 E1 5.600 0.220 f 1.200 0.047 LFBGA64 Body: 8 x 8 x 1.7mm

Obsolete Product(s) - Obsolete Product(s) STA015

7.0 REVISION HISTORY

16-Mar-2004 4 Changed block diagram pin 28, changed legalcy 26-Apr-2010 5 Major revision for revalidation process