STA001

STA001 STMICROELECTRONICS | Alldatasheet

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This is preliminary information on a new product now in development. Details are subject to change without notice. ■ SINGLE CHIP RECEIVER FOR SATELLITE DIGITAL TRANSMISSION ■ SUPERHETERODYNE RECEIVER WITH IF OUTPUT ■ HIGH INPUT INTERCEPT POINT, LOW MIXER NOISE ■ 54dB IF VGA GAIN RANGE ■ ADJUSTABLE RF GAIN ■ ADJUSTABLE IF GAIN ■ INTEGRATED RF VCO ■ INTEGRATED IF VCO ■ INTEGRATED SYNTHESIZER ■ I2CBUS COMPATIBLE PROGRAMMING INTERFACE ■ UNREGULATED 2.7 V TO 3.3V VOLTAGE SUPPLY ■ LOW COST EXTERNAL COMPONENTS

DESCRIPTION

The STA001 is an RF IC using STMicroelectronics HSB2 High Speed Bipolar Technology for one chip so- lution for the Starman digital satellite radio receiver. The STA001 is assembled in a TQFP44 package. The frontend architecture is a double conversion re- ceiver (see block diagram) . The chip includes all the RF functions up to low IF and manages the signals to and from the baseband. TQFP44 ORDERING NUMBER: STA001 PRODUCT PREVIEW RF FRONT-END FOR DIGITAL RADIO BLOCK DIAGRAM XTAL1, XTAL2CHANNEL SELECTION M_CLK DIFFERENTIAL SINGLE ENDED FLT2 TK2, NTK2 LNI, NLNI SIP, SIN AGC1, AGC2 OSC 3.68MHz 113.23KHz SCL SDA 14.72MHz PHASE DETECTOR CHARGE PUMP : 1034 2nd PLL:130 VCO 1338.14 - 1375.4 MHz 117.0806 MHz SOP, SON CHARGE PUMP PHASE DETECTOR :363.625- 373.75 1st PLL VCO VDD1 VSS1 RF MIXER IF1 BUFFER VGA IF1 to IF2 MIXERIF2 BUFFER FLT1 CE

1.8366 Mhz

DETECTOR :4 ENRFOSC BUFFER TK1, NTK1 SUPPLY2 :PLL1 + Crystal osc . SUPPLY3 :DIG. SUPPLY4 :IF1, IF2 &PLL2SUPPLY1 :RF GADJ1, GADJ2 I2CBUS INTERFACE REFXOSEL MUX PADJ1, PADJ2 LNA RXI, NRXI VDD2 VSS2 VDD4 VSS4 VDD3 VSS3

PIN CONNECTION (Top view) PIN FUNCTION N° Pin Function

1 VDD1 Positive supply 1

2 SIP SAW filter input connection

3 SIN SAW filter input connection

4 VSS1 Negative supply 1

5 LNI RF input

6 NLNI RF input

7 VSS1 Negative supply 1

8 NC Not connected

9 PADJ1 RF gain adjust connection 1

10 PADJ2 RF gain adjust connection 2

11 ENRFOSC RF Oscillator enable

12 VDD2 Positive supply 2

13 TK1 1st PLL tank connection 1

14 NTK1 1st PLL tank connection 2

15 VDD2 Positive supply 2

16 FLT1 1st PLL loop filter connection

17 VSS2 Negative supply 2

18 XTAL1 Quartz oscillator connection 1

19 XTAL2 Quartz oscillator connection 2

20 REF External optional TCXO input

21 XOSEL Internal/external XO selection

22 TLCK Lock detector output

44 43 42 41 39 40 38 37 36 35 34 VDD1 SIP SIN VSS1 LNI NLNI VSS1 N.C. PADJ1 PADJ2 ENRFOSC VDD2 TK1 NTK1 VDD2 FLT1 VSS2 XTAL1 XTAL2 REF XOSEL TLCK FLT2 VDD4 TK2 NTK2 VDD4 AGC2 AGC1 VSS4 SON SOP VSS4 M_CLK2 M_CLK1 VSS3 SDA SCL VDD3 CE GADJ2 GADJ1 NRXI RXI D97AU602 12 13 14 15 16

23 M_CLK2 Master clock differential output 1

24 M_CLK1 Master clock differential output 2

25 VSS3 Negative supply 3

26 SDA Data serial input

27 SCL Clock input

28 VDD3 Positive supply 3

29 CE Chip Enable

30 GADJ2 IF gain adjust connection 2

31 GADJ1 IF gain adjust connection 1

32 NRXI Low IF Signal output 2

33 RXI Low IF Signal output 1

34 FLT2 2nd PLL loop filter connection

35 VDD4 Positive supply 4

36 TK2 2nd PLL tank connection

37 NTK2 2nd PLL tank connection

38 VDD4 Positive supply 4

39 AGC2 VGA control pin 2

40 AGC1 VGA control pin 1

41 VSS4 Negative supply 4

42 SON SAW filter output connection

43 SOP SAW filter output connection

44 VSS4 Negative supply 4

Symbol Parameter Value Unit T stg Storage temperature -40 , +125 °C Toper Operative ambient temperature -20 , +85 °C Vmax Maximum voltage on any pin (with the exception of CE, SDA, SDL)VDD+0.3 V Vmin Minimum voltage on any pin GND-0.3 V Vmaxi Maximum voltage on pins CE, SDA, SDL VDD+0.6 V VDD max Minimum/Maximum power supply between VDD1,2,3,4 and VSS 1,2,3,4 -0.3/5.5 V Vesd Electrostatic Discharge Voltage (ESD) 2 KV Symbol Parameter Value Unit VDD Operating voltage 2.7, 3.3 V Tjun Junction temperature -30, +95 °C PIN FUNCTION (continued) N° Pin Function

(1) According to JEDEC specification on a 4 layers board Symbol Parameter Value Unit R Th j-amb Thermal Resistance Junction to Ambient (1) 45 °C/W ELECTRICAL CHARACTERISTCS Symbol Parameter Test Condition Min. Typ. Max. Unit SUPPLY CURRENTS (Tamb = 25°, VDD = 3V) ICC1 Current supplied by VDD1 Powered circuits: LNA, RF mixer, IF buffer 9.5 14 17 mA ICC2 Current supplied by VDD2 Powered circuits: RF pll, Crystal Oscillator. ENRFOSC=high (IC RF Osc. Enabled), XOSEL=high (IC XO Enabled) ENRFOSC=low (IC RF Osc. Disabled), XOSEL=high (IC XO Enabled) ENRFOSC=high (IC RF Osc. Enabled), XOSEL=low (IC XO Disabled) ENRFOSC=low (IC RF Osc. Disabled), XOSEL=low (IC XO Disabled) 8.5 7.5 mA mA mA mA I CC3 Current supplied by VDD3 Powered circuits: Digital cells 12 15 18 mA ICC4 Current supplied by VDD4 Powered circuits: VGA, IF mixer, output buffer, IF pll. V(AGC1)=V(AGC2)=1.2 (IFgain=75dB) 71 1 1 4 m A ITOT ICC1 + ICC2 + ICC3 + ICC4 ENRFOSC=high (IC RF Osc. Enabled), XOSEL=high (IC XO Enabled) ENRFOSC=low (IC RF Osc. Disabled), XOSEL=high (IC XO Enabled) ENRFOSC=high (IC RF Osc. Enabled), XOSEL=low (IC XO Disabled) ENRFOSC=low (IC RF Osc. Disabled), XOSEL=low (IC XO Disabled) mA mA mA mA I TOTSB Standby ICC1 + ICC2 + ICC3 + ICC4 CE=GND 100 µA LNA, RF MIXER AND IF1 BUFFER (T = 25°, VDD-VSS = 3V) BW i Input signal BW 1452 1492 MHz BW o Output signal BW 114 116.5 MHz G V Voltage Gain Input LNI, NLNI pins; output SIP , NIP pins. R L = 200Ω, PADJ1, PADJ2 floating 28 30 33 dB

G Vtrim Minimum Voltage Gain Input LNI, NLNI pins; output SIP , NIP pins. R L = 200Ω, R ext=0 22 25 28 dB Zi Input impedance R || C Balanced, LNI, NLNI pins 75 0.2 Ω pF Zo Output impedance Balanced, SIP, SIN pins 50 Ω R l Input Return Loss LNI, NLNI pins 14 dB IIP3 Input IP3 Input LNI, NLNI pins; output SIP , NIP pins, R l=200Ω, PADJ1, PADJ2 floating -20 -15 dBm IIP3trim Input IP3 minimum gain Input LNI, NLNI pins; output SIP , NIP pins, R l=200Ω, R ext=0 on PADJ1, PADJ2 -19.5 -11.5 dBm 1dBcp Input 1 dB compression point Input LNI, NLNI pins; output SIP , NIP pins, R l=200Ω, PADJ1, PADJ2 floating -26 dBm 1dBcptri m Input 1 dB compression point Input LNI, NLNI pins; output SIP , NIP pins, R l=200Ω, PADJ1, PADJ2 Rext=0 on PADJ1, PADJ2 -24 dBm NF Noise figure contribution Measurement conditions: Input LNI, NLNI pins; output SIP , NIP pins. Rs=50Ω, R l=200Ω, DSB, PADJ1, PADJ2 floating 5d B NF trim Noise figure contribution minimum gain Measurement conditions: Input LNI, NLNI pins; output SIP , NIP pins. Rs=50Ω, R l=200Ω, DSB, Rext=0 on PADJ1, PADJ2 6.5 dB IF1leak LO1 to IF1 leakage -100 -25 dBm RF leak LO1 to RF leakage -100 -30 dBm VDC LNI, NLNI common mode DC voltage AC coupled to the Balun V DD - 1.2 VDD -1 V DD - 0.8 V VDC SIP , SIN common mode DC voltage AC coupled to the SAW filter V DD - 1.3 VDD - 1.1 VDD - 0.9 V IF VGA AMPLIFIER, IF MIXER AND OUTPUT BUFFER (T = 25°, VDD-VSS = 3V) BW i Input signal BW 114 116.5 MHz BW o Output signal BW 0.6 3.1 MHz G min Minimum gain Input LNI, NLNI pins; output SIP , NIP pins. Rl=high impedance V(AGC1,2)=0V 32 37 dB G max Maximum gain Input LNI, NLNI pins; output SIP , NIP pins. Rl=high impedance V(AGC1,2)=3V 71 86 dB IAGC Input current in AGC control pin 10 µA ZAGC AGC pin input impedance

600 K Ω

ELECTRICAL CHARACTERISTCS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit

Figure 1. Typical IF Overall Gain vs Control Voltage

ELECTRICAL CHARACTERISTCS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit CRYSTAL OSCILLATOR (T = 25°, VDD-VSS = 3V) VDC XTAL1, XTAL2 common mode DC voltage XOSEL high V DD - 1.1 VDD - 0.68 V PLLs, SYNTHESIZERS (T = 25°, VDD-VSS = 3V) ts RF pll loop settling time within 1 KHz final freq. Offset, by using the loop filter of Application board 1m s Pn Total phase noise contribution 100Hz < Δf < 1.84Mhz, Q rf_tank≥20, Qif_tank≥20 1.6 deg rms fREF1 RF pll comparation frequency

3.68 MHz

113.23 KHz

PSP Spurious power level*** RF pll, Δfc=n*460KHz n=1,2.. IF pll, Δfc=113.23KHz -100 -50 -45 dBc dBc N prog1 RF PLL selectable division ratios from REF1 to LO1, range covered by a 0.5 step, using a 14.72MHz quartz 1443 (first used 1454.5) 1506.5 (last used 1495) N prog2 RF PLL selectable division ratios from REF1 to LO1, range covered by a 0.5 step, using a 14.725MHz quartz 1443 (first used 1454) 1506.5 (last used 1494.5) N fix IF PLL fixed division ratios from REF2 to LO2, 1 fixed +2 testing values987 1034 1081 N REF1 REF1 division ratio from Crystal oscillator to REF1 4 N REF2 REF2 division ratio from Crystal oscillator to REF2 130 *** Using loop filter as suggested in application board schematics RF VCO (T = 25°, VDD-VSS = 3V) fLO1_1 LO Freq. range Using 14.72Mhz quartz 1338.14 1375.4 MHz fLO1_2 LO Freq. range Using 14.725Mhz quartz 1338.134375 to 1375.407031MHz VFLT1 Freq. control voltage range Pin FLT1 VSS + 0.2 VDD - 0.2 V VDC TK1, NTK1 DC voltage ENRFOSC high V DD - 1.3 VDD - 1.1 VDD - 0.65 V Zi Input impedance R || C Balanced, TK1, NTK1 pins 300 0.2 Ω pF

IF VCO (T = 25°, VDD-VSS = 3V) fLO2_1 LO Freq. Using a 14.72MHz quartz, Min. and Max. Values are optional fixed frequency usable for testing purposes. 111.76 117.08 122.4 MHz f LO2_2 LO Freq. Using a 14.725MHz quartz, Min. and Max. Values are optional fixed frequency usable for testing purposes. 111.8 117.12 122.44 MHz VFLT2 Freq. control voltage range FLT2 pin V SS + 0.2 VDD - 0.2 V DIGITAL INTERFACE TO MP (SCL, SDA, TLCK) AND XOSEL INTERFACE (T = 25°, VDD-VSS = 3V) INPUT PARAMETERS (SCL, SDA) VIH digital input signals high V DD -1 V DD V VIL low V SS VSS +0. V IIH Input current High 10 µA IIL Input current Low -40 µA Tt Input edge transition 0.1 µs/V R in Input resistance 190K Ω OUTPUT PARAMETERS (TLCK) VOH digital output signals high V DD - 0.5 VDD V VOL low V SS VSS +0. V tr Rise time Cl=5pF 0.4 µs/V tf Fall time Cl=5pF 0.4 µs/V DIFFERENTIAL DIGITAL INTERFACE (M_CLK1, M_CLK2) (T = 25°, VDD-VSS = 3V) VOH digital output signals, V(M_CLK1) - V(M_CLK2) high 0.2 V VOL low -0.2 V VDC M_CLK1, M_CLK2 common mode DC voltage VDD - 1.12 VDD - 0.7 V tr Rise time Cl=5pF each pin 10 ns tf Fall time Cl=5pF each pin 10 ns Zout Output impedance balanced 500 Ω ELECTRICAL CHARACTERISTCS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit

XOSEL, CE, TLCK, ENRFOSC TRUTH TABLE (LOW = GND, HIGH = VDD) fM_CLK1 M_CLK frequency Using a 14.72MHz quartz 14.72 MHz fM_CLK2 M_CLK frequency Using a 14.725MHz quartz 14.725 MHz ADDITIONAL DIGITAL INTERFACE (CE) (T = 25°, VDD-VSS = 3V) (LOW=GND, HIGH=VDD) VIH digital input signals high VSS+1. V VIL low VSS +1. V tr CE power up time 2 µs tf CE power down time 6 µs Pin Type Level Result CE input high Chip enabled low Chip disabled XOSEL input high Internal Crystal oscillator selected low External TCXO connected on REF selected ENRFOSC input high Internal RF oscillator selected low External RF oscillator connected on TK1, NTK1 pins TLCK output high Synth. locked low Synth. unlocked ADDITIONAL OPTIONAL INTERFACE INFORMATION (REF) Symbol Parameter Test Condition Min. Typ. Max. Unit VDC REF DC voltage XOSEL low V DD - 1.1 VDD - 0.9 VDD - 0.7 V R in Input resistance XOSEL low 70K Ω ELECTRICAL CHARACTERISTCS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit

The receiver chain transforms the RF frequency signals to an IF signal at 1.84 MHz Carrier directly usable by the Channel decoder. In front of the STA001 IC it can be placed an external LNA and a bandpass filter; the bandpass filter limitates the input bandwidth and guarantees a suitable rejection to the image frequency. The STA001 input stage is a LNA working in the 1452-1492 MHz band. The RF signal is downconverted, using an active mixer, to a first IF of 115.244 MHz. The first LO is tunable with a frequency step of 460 KHz. The RF can be reduced 5dB by an external trimmer/resistor connected between PADJ1 and PADJ2 pins. An IF variable gain amplifier guarantees 54 dB typical of gain range. Using pins GADJ1, GADJ2, the output RX signal level can be decreased to the desired value by an external trimmer/resistor. Moreover, the IF chain can be configured to have a fixed gain by fixing statically control voltages on AGC1 and AGC2 pins (i.e. V(AGC1)=VCC and V(AGC2)=GND), and by trimming the gain through connecting an external resistor between GADJ1 and GADJ2. By using an 800 Ohm resistor connected between GADJ1 and GADJ2, for example, a typical 56 dBs IF static gain is obtained. The first IF signal, having a bandwidth of 2.5 MHz, shaped by an external SAW filter, is downconverted to a second IF of 1.84 MHz. A differential clock output at 14.72 MHz is available to be used from the baseband. Synthesizers, PLL, charge pump and VCOs The first Voltage controlled Oscillator is controlled by an integrated PLL and it's able to cover a frequency range of 37MHz with a step size of 460 KHz. The second Voltage controlled oscillator produces a fixed 117.08MHz frequency controlled by a second inte- suitable for application test. The other components of the first PLL synthesizer are a low frequency programmable divider and a dual mod- ulus prescaler; a fixed dividers is instead used to synthesize the second VCO frequency. Other fixed internal dividers are used to get the comparation frequencies of both loops. Channel selection is made through the I 2CBUS interface , directly from the µP. POWER SUPPLIES The chip operates from an unregulated power supply of 2.7 to 3.3 Volts. All interface circuits to the baseband chips are operating between these supplies unless otherwise specified. INTERFACE SPECIFICATION All the interface voltage levels to the micro controller are referenced to the supply voltage of the interface power supply (GND) . The interface voltage levels are therefore fully compatible with the base band circuits. The digital levels are all CMOS threshold compatible with the exception of M_CLK1, M_CLK2 pins (ECL type). For completeness all other interface signals are also included. I2C BUS INTERFACE Data transmission from microprocessor to the STA001 takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected to SDA and SCL).

Figure 7. SOFTWARE SPECIFICATION Interface protocol The interface protocol comprises: - A start condition (S) - A chip address byte - A two data bytes - A stop condition (P) ack = Acknowledge S = Start P = Stop "Byte by byte" option A "byte by byte" programming mode is also possible when there is no need to use both data bytes to program the chip (for example during the setup of 2nd PLL). To use this feature remember that first bit of both data bytes is reserved to chose the destination of the remaining 7 bits. ack = Acknowledge S = Start Symbol Parameter Maximum time (ns) td1 Ack begin delay 200 td2 Ack end delay 200 MSB chip address LSB MSB 1st data byte LSB MSB 2nd data byte LSB S11000000 ack 1 D 6D 5D 4D 3D 2D 1D 0 ack 0 D 6D 5D 4D 3D 2D 1 D 0a c k P MSB chip address LSB MSB 1st data byte LSB S11000000 ack K D 6D 5D 4D 3D 2D 1D 0a c k P SDA SCL td2 td1

K=1 the data byte has the same function of the 1st data byte in the normal programming mode. K=0 the data byte has the same function of the 2nd data byte in the normal programming mode. Table 1. First data byte selection table (selection of synthesizer channel) using a 14.72Mhz quartz MHz 360 + N*0.125 general freq.

Table 2. First data byte selection table (selection of synthesizer channel) using a 14.725Mhz quartz Table 3. Second data byte selection table (LOCK test on both pll, dividers test and IF pll test) MHz 360 + N*0.125 general freq.

0000000 L o c k t e s t o n R F p l l lock flag to be tested: TLCK;

0000100 L o c k t e s t o n I F p l l lock flag to be tested: TLCK

0000001 L ock test on RF and IF pll lock flag to be tested: TLCK

0010010 First pll programmable

0011010 First pll reference divider

0010110 Second pll fixed divider

1000000 T est frequency on IF pll

1100000 T est frequency on IF pll

Figure 8. Test Board Schematic Diagram

Figure 9. Application Board Schematic Diagram

Application note: the crystal oscillator must have the following features: Symbol Parameter Test Condition Min. Typ. Max. Unit CRYSTAL OSCILLATOR (T = 25°, VP-VN = 3V) fxtal1 Quartz frequency - Resonance mode: series - Using a 14.72

14.72 MHz

fxtal2 Quartz frequency - Resonance mode: series - using a 14.725 quartz

14.725 MHz

Pn Phase noise Δf = 1 KHz -120 -118 dBc/Hz VDC XTAL1, XTAL2 common mode DC voltage XOSEL high VP-1.1 VP-0.9 VP-0.7 V

TQFP44 (10 x 10) DIM. mm inch A 1.60 0.063 A1 0.05 0.15 0.002 0.006 C 0.09 0.20 0.004 0.008 D 12.00 0.472 D1 10.00 0.394 D3 8.00 0.315 e 0.80 0.031 E 12.00 0.472 E1 10.00 0.394 E3 8.00 0.315 L1 1.00 0.039 K 0°(min.), 3.5˚(typ.), 7°(max.) A A1B Seating Plane C 2333 E D e K B TQFP4410 L 0.10mm .004 OUTLINE AND MECHANICAL DATA

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics  2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com STA001