ST90T158LV

ST90158-ST90135 STMICROELECTRONICS | Alldatasheet

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Rev. 3.0 ST90158 - ST90135 8/16-BIT MCU FAMILY WITH UP TO 64K ROM/OTP/EPROM AND UP TO 2K RAM n Register File based 8/16 bit Core Architecture with RUN, WFI, SLOW and HALT modes n 0 - 16 MHz Operation @ 5V±10%, -40°Ct o +85°C and 0 °C to +70 °C Operating Temperature Ranges n 0 - 14 MHz Operation @ 3V±10% and 0°Ct o +70°C Operating Temperature Range n Fully Programmable PLL Clock Generator, with Frequency Multiplication and low frequency, low cost external crystal n Minimum 8-bit Instruction Cycle time: 83ns - (@

24 MHz internal clock frequency)

n Minimum 16-bit Instruction Cycle time: 250ns - (@ 24 MHz internal clock frequency) n Internal Memory: – EPROM/OTP/ROM 16/24/32/48/64K bytes – ROMless version available – RAM 512/768/1K/1.5K/2K bytes n Maximum External Memory: 64K bytes n 224 general purpose registers available as RAM, accumulators or index pointers (register file) n 80-pin Plastic Quad Flat Package and 80-pin Thin Quad Flat Package n 67 fully programmable I/O bits n 8 external and 1 Non-Maskable Interrupts n DMA Controller and Programmable Interrupt Handler n Single Master Serial Peripheral Interface n Two 16-bit Timers with 8-bit Prescaler, one usable as a Watchdog Timer (software and hardware) n Three (ST90158) or two (ST90135) 16-bit Multifunction Timers, each with an 8 bit prescaler, 12 operating modes and DMA capabilities n 8 channel 8-bit Analog to Digital Converter, with Automatic voltage monitoring capabilities and external reference inputs n Two (ST90158) or one (ST90135) Serial Communication Interfaces with asynchronous, synchronous and DMA capabilities n Rich Instruction Set with 14 Addressing modes n Division-by-Zero trap generation n Versatile Development Tools, including Assembler, Linker, C-compiler, Archiver, Source Level Debugger and Hardware Emulators with Real-Time Operating System available from Third Parties DEVICE SUMMARY DEVICE Program Memory (Bytes) RAM (Bytes)MFT SCI PACKAGE ST90135 16K ROM 512 2 1 PQFP80 24K ROM 768 2 1 32K ROM 1K 2 1 ST90158 48K ROM 1.5K 3 2 64k ROM 2K 3 2 PQFP80/ TQFP80 ST90E158 64K EPROM 2K 3 2 CQFP80 ST90E158LV 64K EPROM 2K 3 2 CQFP80 ST90T158 64K OTP 2K 3 2 PQFP80 ST90T158LV 64K OTP 2K 3 2 PQFP80/ TQFP80/ ST90R158 ROMless 2K 3 2 PQFP80/ TQFP80 PQFP80 TQFP80

ST90158 - GENERAL DESCRIPTION

1 GENERAL DESCRIPTION

1.1 INTRODUCTION

The ST90158 and ST90135 microcontrollers are developed and manufactured by STMicroelectron- ics using a proprietary n-well CMOS process. Their performance derives from the use of a flexi- ble 256-register programming model for ultra-fast context switching and real-time event response. The intelligent on-chip peripherals offload the ST9 core from I/O and data management processing tasks allowing critical application tasks to get the maximum use of core resources. The new-gener- ation ST9 MCU devices now also support low power consumption and low voltage operation for power-efficient and low-cost embedded systems.

1.1.1 ST9+ Core

The advanced Core consists of the Central Processing Unit (CPU), the Register File, the Inter- rupt and DMA controller, and the Memory Man- agement Unit. The MMU allows addressing of up to 4 Megabytes of program and data mapped into a single linear space. Four independent buses are controlled by the Core: a 16-bit memory bus, an 8-bit register data bus, an 8-bit register address bus and a 6-bit inter- rupt/DMA bus which connects the interrupt and DMA controllers in the on-chip peripherals with the core. This multiple bus architecture makes the ST9 fam- ily devices highly efficient for accessing on and off- chip memory and fast exchange of data with the on-chip peripherals. The general-purpose registers can be used as ac- cumulators, index registers, or address pointers. Adjacent register pairs make up 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit opera- tions, including arithmetic, loads/stores, and mem- ory/register and memory/memory exchanges.

1.1.2 Power Saving Modes

To optimize performance versus power consump- tion, a range of operating modes can be dynami- cally selected. Run Mode. This is the full speed execution mode with CPU and peripherals running at the maximum clock speed delivered by the Phase Locked Loop (PLL) of the Clock Control Unit (CCU). Slow Mode . Power consumption can be signifi- cantly reduced by running the CPU and the periph- erals at reduced clock speed using the CPU Pres- caler and CCU Clock Divider (PLL not used) or by using the CK_AF external clock. Wait For Interrupt Mode.The Wait For Interrupt (WFI) instruction suspends program execution un- til an interrupt request is acknowledged. During WFI, the CPU clock is halted while the peripheral and interrupt controller keep running at a frequen- cy programmable via the CCU. In this mode, the power consumption of the device can be reduced by more than 95% (Low Power WFI). Halt Mode.When executing the HALT instruction, and if the Watchdog is not enabled, the CPU and its peripherals stop operating and the status of the machine remains frozen (the clock is also stopped). A reset is necessary to exit from Halt mode. 1.1.3 system Clock A programmable PLL Clock Generator allows standard 3 to 5 MHz crystals to be used to obtain a large range of internal frequencies up to 24 MHz.

1.1.4 I/O Ports

The I/O lines are grouped into up to nine 8-bit I/O Ports and can be configured on a bit basis to pro- vide timing, status signals, an address/data bus for interfacing to external memory, timer inputs and outputs, analog inputs, external interrupts and se- rial or parallel I/O.

ST90158 - GENERAL DESCRIPTION

1.1.5 Multifunction Timers (MFT)

Each multifunction timer has a 16-bit Up/Down counter supported by two 16-bit Compare regis- ters and two 16-bit input capture registers. Timing resolution can be programmed using an 8-bit pres- caler. Multibyte transfers between the peripheral and memory are supported by two DMA channels.

1.1.6 Standard Timer (STIM)

The Standard Timer includes a programmable 16- bit down counter and an associated 8-bit prescaler with Single and Continuous counting modes.

1.1.7 Watchdog Timer (WDT)

The Watchdog timer can be used to monitor sys- tem integrity. When enabled, it generates a reset after a timeout period unless the counter is re- freshed by the application software. For additional security, watchdog function can be enabled by hardware using a specific pin.

1.1.8 Serial Peripheral Interface (SPI)

The SPI bus is used to communicate with external devices via the SPI, or I C bus communication standards. The SPI uses one or two lines for serial data and a synchronous clock signal.

1.1.9 Serial Communications Controllers (SCI)

Each SCI provides a synchronous or asynchro- nous serial I/O port using two DMA channels. Baud rates and data formats are programmable.

1.1.10 Analog/Digital Converter (ADC)

The ADCs provide up to 8 analog inputs with on- chip sample and hold. The analog watchdog gen- erates an interrupt when the input voltage moves out of a preset threshold.

Figure 1. ST90158 Block Diagram

Figure 2. ST90135 Block Diagram

ST90158 - GENERAL DESCRIPTION

1.2 PIN DESCRIPTION

AS : Address Strobe (output, active low, 3-state). Address Strobe is pulsed low once at the begin- ning of each memory cycle. The rising edge of AS indicates that address, Read/Write (R/W), and Data Memory signals are valid for memory trans- fers. Under program control, AS can be placed in a high-impedance state along with Port 0, Port 1 and Data Strobe (DS). DS : Data Strobe (output, active low, 3-state). Data Strobe provides the timing for data movement to or from Port 0 for each memory transfer. During a write cycle, data out is valid at the leading edge of DS. During a read cycle, Data In must be valid pri- or to the trailing edge of DS. When the ST90158 accesses on-chip memory, DS is held high during the whole memory cycle. It can be placed in a high impedance state along with Port 0, Port 1 and AS. RESET : Reset (input, active low). The ST9+ is ini- tialised by the Reset signal. With the deactivation of RESET, program execution begins from the memory location pointed to by the vector con- tained in memory locations 00h and 01h. R/W : Read/Write (output, 3-state). Read/Write de- termines the direction of data transfer for external memory transactions. R/W is low when writing to external memory, and high for all other transac- tions. It can be placed in high impedance state along with Port 0, Port 1, AS and DS. OSCIN, OSCOUT : Oscillator (input and output). These pins connect a parallel-resonant crystal (3 to 5 MHz), or an external source to the on-chip clock oscillator and buffer. OSCIN is the input of the oscillator inverter and internal clock generator; OSCOUT is the output of the oscillator inverter. HW0_SW1: When connected to V DD through a 1K pull-up resistor, the software watchdog option is selected. When connected to VSS through a 1K pull-down resistor, the hardware watchdog option is selected. VPP : Programming voltage for EPROM/OTP de- vices. Must be connected to VSS in user mode through a 10 Kohm resistor. AV DD : Analog VDD of the Analog to Digital Con- verter. AV SS : Analog VSS of the Analog to Digital Con- verter. VDD : Main Power Supply Voltage (5V± 10%). VSS : Digital Circuit Ground. P0[7:0], P1[7:0]:(Input/Output, TTL or CMOS compatible). 16 lines grouped into I/O ports provid- ing the external memory interface for addressing 64Kbytes of external memory. Port Lines (Input/Output, TTL or CMOS compati- ble).I/O lines grouped into I/O ports of 8 bits, bit programmable under program control as general purpose I/O or as alternate functions.

Figure 3. 80-Pin TQFP Pin-out

Figure 4. 80-Pin PQFP Pin-Out

1.3 I/O PORT PINS

vidually (Refer to the I/O ports chapter). by programming the relevant PxC2.n control bit. uration” in the I/O Ports Chapter . DD +0.3 Volt, to avoid direct junction biasing. Table 1. I/O Port Characteristics

ble in the I/O ports Chapter (See page 92). input level can be selected by software. will always be Schmitt Trigger. An alternate function can be selected as follows. Table 2. I/O Port Description and Alternate Functions

ST90158 - GENERAL DESCRIPTION P1.3 All ports useable for general pur- pose I/O (input, output or bidirec- tional) 63 65 A11 I/O Address bit 11 P1.4 64 66 A12 I/O Address bit 12 P1.5 65 67 A13 I/O Address bit 13 P1.6 66 68 A14 I/O Address bit 14 P1.7 67 69 A15 I/O Address bit 15 P2.0 16 18 I/O P2.1 17 19 I/O P2.2 18 20 I/O P2.3 19 21 I/O P2.4 20 22 I/O P2.5 21 23 I/O P2.6 22 24 I/O P4.0 8 10 I/O P4.1 9 11 I/O P4.2 10 12 INTCLK O Internal main Clock P4.3 11 13 STOUT O Standard Timer Output P4.4 12 14 INT0 I External Interrupt 0 WDOUT O Watchdog Timer output P4.5 13 15 INT4 I External interrupt 4 P4.6 14 16 INT5 I External Interrupt 5 T0OUTB O MF Timer 0 Output B P4.7 15 17 T0OUTA O MF Timer 0 Output A 1) P5.1 55 57 SDI I SPI Serial Data In P5.3 53 55 I/O P5.4 52 54 T1OUTA O MF Timer 1 output A DCD0 I SCI0 Data Carrier Detect P5.5 51 53 RTS0 O SCI0 Request to Send T1OUTB O MF Timer 1 output B P5.6 50 52 T3OUTA O MF Timer 3 output A DCD1 I SCI1 Data Carrier Detect 1) P5.7 49 51 RTS1 O SCI1 Request to Send 1) T3OUTB O MF Timer 3 output B CK_AF I External Clock Input P6.0 68 70 I/O Port Name General Purpose I/O Pin No. Alternate Functions TQFP PQFP

ST90158 - GENERAL DESCRIPTION P6.1 All ports useable for general pur- pose I/O (input, output or bidirec- tional) 69 71 I/O P6.2 70 72 I/O P6.3 71 73 I/O P6.4 72 74 I/O P6.5 73 75 R/W O Read/Write P6.6 74 76 I/O P7.0 30 32 AIN0 I A/D Analog input 0 RX0CKIN I SCI0 Receive Clock input WDIN I T/WD input EXTRG I A/D External Trigger P7.1 31 33 AIN1 I A/D Analog input 1 T0INB I MF Timer 0 input B SDI I SPI Serial Data In P7.2 32 34 AIN2 I A/D Analog input 2 CLK0OUT O SCI0 Byte Sync Clock output TX0CKIN I SCI0 Transmit Clock input P7.3 33 35 AIN3 I A/D Analog input 3 T0INA I MF Timer 0 input A 1) P7.4 34 36 AIN4 I A/D Analog input 4 P7.5 35 37 AIN5 I A/D Analog input 5 P7.6 36 38 AIN6 I A/D Analog input 6 P7.7 37 39 AIN7 I A/D Analog input 7 P8.0 47 49 T3INA I MF Timer 3 input A P8.1 46 48 T1INB I MF Timer 1 input B P8.2 45 47 INT1 I External interrupt 1 T1OUTA O MF Timer 1 output A P8.3 44 46 INT3 I External interrupt 3 T1OUTB O MF Timer 1 output B P8.4 43 45 T1INA I MF Timer 1 input A WAIT I External Wait input WDOUT O Watchdog Timer output P8.5 42 44 T3INB I MF Timer 3 input B P8.6 41 43 INT7 I External interrupt 7 T3OUTA O MF Timer 3 output A P8.7 40 42 NMI I Non-Maskable Interrupt T3OUTB O MF Timer 3 output B Port Name General Purpose I/O Pin No. Alternate Functions TQFP PQFP

ST90158 - GENERAL DESCRIPTION Note 1) Not present on ST90135 P9.0 All ports useable for general pur- pose I/O (input, output or bidirec- tional) 23 25 S1OUT O SCI1 Serial Output 1) P9.1 24 26 T0OUTB O MF Timer 0 output B 1) S1IN I SCI1 Serial Input 1) P9.2 25 27 CLK1OUT O SCI1 Byte Sync Clock output1) TX1CKIN I SCI1 Transmit Clock input1) P9.4 26 28 S0OUT O SCI0 Serial Output RX1CKIN O SCI1 Receive Clock input1) P9.5 27 29 S0IN I SCI0 Serial Input P9.6 28 30 INT2 I External interrupt 2 SCK O SPI Serial Clock P9.7 29 31 INT6 I External interrupt 6 SDO O SPI Serial Data Out Port Name General Purpose I/O Pin No. Alternate Functions TQFP PQFP

2 DEVICE ARCHITECTURE

2.1 CORE ARCHITECTURE

2.2 MEMORY SPACES

2.2.1 Register File

to Group F (R240 to R255), see Figure 7. Figure 5. Single Program and Data Memory Address Space

Figure 6. Register Groups Figure 7. Page Pointer for Group F mapping Figure 8. Addressing the Register File

64 PAGES

2.2.2 Register Addressing

dressed in Working Register mode. third register of page 5 (R242). Table 3. Register File Organization

2.3 SYSTEM REGISTERS

description of the PORT[5:0] Data registers. Table 4. System Registers (Group E)

2.3.1 Central Interrupt Control Register

tailed description of the ST9 interrupt philosophy. then this bit has no effect. Top Level Interrupt Pending. on the TLNM bit in the NICR Register. (described in the Interrupt chapter). Bit 4 =IEN:Interrupt Enable . operation to the CICR register. 0: Disable all interrupts except Top Level Interrupt. stored until required in the NICR register.

ST90158 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d)

2.3.2 Flag Register

The Flag Register contains 8 flags which indicate the CPU status. During an interrupt, the flag regis- ter is automatically stored in the system stack area and recalled at the end of the interrupt service rou- tine, thus returning the CPU to its original status. This occurs for all interrupts and, when operating in nested mode, up to seven versions of the flag register may be stored. FLAG REGISTER (FLAGR) R231- Read/Write Register Group: E (System) Reset value: 0000 0000 (00h) Bit 7 =C : Carry Flag. The carry flag is affected by: Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply and Divide (mul, div, divws). When set, it generally indicates a carry out of the most significant bit position of the register being used as an accumulator (bit 7 for byte operations and bit 15 for word operations). The carry flag can be set by the Set Carry Flag (scf) instruction, cleared by the Reset Carry Flag (rcf) instruction, and complemented by the Com- plement Carry Flag (ccf) instruction. Bit 6 =Z: Zero Flag. The Zero flag is affected by: Addition (add, addw, adc, adcw), Subtraction (sub, subw, sbc, sbcw), Compare (cp, cpw), Shift Right Arithmetic (sra, sraw), Shift Left Arithmetic (sla, slaw), Swap Nibbles (swap), Rotate (rrc, rrcw, rlc, rlcw, ror, rol), Decimal Adjust (da), Multiply and Divide (mul, div, divws), Logical (and, andw, or, orw, xor, xorw, cpl), Increment and Decrement (inc, incw, dec, decw), Test (tm, tmw, tcm, tcmw, btset). In most cases, theZero flag is setwhen the contents of the register being used as an accumulator be- come zero, following one of the above operations. Bit 5 =S:Sign Flag. The Sign flag is affected by the same instructions as the Zero flag. The Sign flag is set when bit 7 (for a byte opera- tion) or bit 15 (for a word operation) of the register used as an accumulator is one. Bit 4 =V: Overflow Flag. The Overflow flag is affected by the same instruc- tions as the Zero and Sign flags. When set, the Overflow flag indicates that a two’s- complement number, in a result register, is in er- ror, since it has exceeded the largest (or is less than the smallest), number that can be represent- ed in two’s-complement notation. Bit 3 =DA : Decimal Adjust Flag. The DA flag is used for BCD arithmetic. Since the algorithm for correcting BCD operations is differ- ent for addition and subtraction, this flag is used to specify which type of instruction was executed last, so that the subsequent Decimal Adjust (da) operation can perform its function correctly. The DA flag cannot normally be used as a test condi- tion by the programmer. Bit 2 =H : Half Carry Flag. The H flag indicates a carry out of (or a borrow in- to) bit 3, as the result of adding or subtracting two 8-bit bytes, each representing two BCD digits. The H flag is used by the Decimal Adjust (da) instruc- tion to convert the binary result of a previous addi- tion or subtraction into the correct BCD result. Like the DA flag, this flag is not normally accessed by the user. Bit 1 = Reserved bit (must be 0). Bit 0 =DP : Data/Program Memory Flag. This bit indicates the memory area addressed. Its value is affected by the Set Data Memory (sdm) and Set Program Memory (spm) instructions. Re- fer to the Memory Management Unit for further de- tails. C Z S V DA H - DP

ST90158 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) If the bit is set, data is accessed using the Data Pointers (DPRs registers), otherwise it is pointed to by the Code Pointer (CSR register); therefore, the user initialization routine must include aSdm instruction. Note that code is always pointed to by the Code Pointer (CSR). Note:In the ST9+, the DP flag is only for compat- ibility with software developed for the first genera- tion of ST9 devices. With the single memory ad- dressing space, its use is now redundant. It must be kept to 1 with aSdminstruction at the beginning of the program to ensure a normal use of the differ- ent memory pointers.

2.3.3 Register Pointing Techniques

Two registers within the System register group, are used as pointers to the working registers. Reg- ister Pointer 0 (R232) may be used on its own as a single pointer to a 16-register working space, or in conjunction with Register Pointer 1 (R233), to point to two separate 8-register spaces. For the purpose of register pointing, the 16 register groups of the register file are subdivided into 32 8- register blocks. The values specified with the Set Register Pointer instructions refer to the blocks to be pointed to in twin 8-register mode, or to the low- er 8-register block location in single 16-register mode. The Set Register Pointer instructionssrp,srp0 and srp1automatically inform the CPU whether the Register File is to operate in single 16-register mode or in twin 8-register mode. Thesrpinstruc- tion selects the single 16-register group mode and specifies the location of the lower 8-register block, while thesrp0and srp1instructions automatical- ly select the twin 8-register group mode and spec- ify the locations of each 8-register block. There is no limitation on the order or position of these register groups, other than that they must start on an 8-register boundary in twin 8-register mode, or on a 16-register boundary in single 16- register mode. The block number should always be an even number in single 16-register mode. The 16-regis- ter group will always start at the block whose number is the nearest even number equal to or lower than the block number specified in thesrp instruction. Avoid using odd block numbers, since this can be confusing if twin mode is subsequently selected. Thus: srp #3will be interpreted assrp #2and will al- In single 16-register mode, the working registers are referred to asr0to r15. In twin 8-register mode, registersr0tor7are in the block pointed to by RP0 (by means of thesrp0instruction), while registersr8tor15are in the block pointed to by RP1 (by means of thesrp1instruction). Caution: Group D registers can only be accessed as working registers using the Register Pointers, or by means of the Stack Pointers. They cannot be addressed explicitly in the form “Rxxx”.

ST90158 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) POINTER 0 REGISTER (RP0) R232 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh) Bit 7:3 =RG[4:0]:Register Group number. These bits contain the number (in the range 0 to 31) of the register block specified in thesrp0or srpinstructions. In single 16-register mode the number indicates the lower of the two 8-register blocks to which the 16 working registers are to be mapped, while in twin 8-register mode it indicates the 8-register block to whichr0to r7are to be mapped. Bit 2 =RPS : Register Pointer Selector. This bit is set by the instructionssrp0and srp1to indicate that the twin register pointing mode is se- lected. The bit is reset by thesrpinstruction to in- dicate that the single register pointing mode is se- lected. 0: Single register pointing mode 1: Twin register pointing mode Bit 1:0: Reserved. Forced by hardware to zero. POINTER 1 REGISTER (RP1) R233 - Read/Write Register Group: E (System) Reset Value: xxxx xx00 (xxh) This register is only used in the twin register point- ing mode. When using the single register pointing mode, or when using only one of the twin register groups, the RP1 register must be considered as RESERVED and may NOT be used as a general purpose register. Bit 7:3 =RG[4:0]: Register Group number.These bits contain the number (in the range 0 to 31) of the 8-register block specified in thesrp1instruc- tion, to whichr8tor15are to be mapped. Bit 2 =RPS :Register Pointer Selector. This bit is set by thesrp0and srp1instructions to indicate that the twin register pointing mode is se- lected. The bit is reset by thesrpinstruction to in- dicate that the single register pointing mode is se- lected. 0: Single register pointing mode 1: Twin register pointing mode Bit 1:0: Reserved. Forced by hardware to zero. RG4 RG3 RG2 RG1 RG0 RPS 0 0 RG4 RG3 RG2 RG1 RG0 RPS 0 0

ST90158 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d)

2.3.4 Paged Registers

Up to 64 pages, each containing 16 registers, may be mapped to Group F. These paged registers hold data and control information relating to the on-chip peripherals, each peripheral always being associated with the same pages and registers to ensure code compatibility between ST9+ devices. The number of these registers depends on the pe- ripherals present in the specific ST9 device. In oth- er words, pages only exist if the relevant peripher- al is present. The paged registers are addressed using the nor- mal register addressing modes, in conjunction with the Page Pointer register, R234, which is one of the System registers. This register selects the page to be mapped to Group F and, once set, does not need to be changed if two or more regis- ters on the same page are to be addressed in suc- cession. Thus the instructions: spp #5 ld R242, r4 will load the contents of working register r4 into the third register of page 5 (R242). Warning: During an interrupt, the PPR register is not saved automatically in the stack. If needed, it should be saved/restored by the user within the in- terrupt routine. PAGE POINTER REGISTER (PPR) R234 - Read/Write Register Group: E (System) Reset value: xxxx xx00 (xxh) Bit 7:2 =PP[5:0]: Page Pointer. These bits contain the number (in the range 0 to 63) of the page specified in thesppinstruction. Once the page pointer has been set, there is no need to refresh it unless a different page is re- quired. Bit 1:0: Reserved. Forced by hardware to 0.

2.3.5 Mode Register

The Mode Register allows control of the following operating parameters: – Selection of internal or external System and User Stack areas, – Management of the clock frequency, – Enabling of Bus request and Wait signals when interfacing to external memory. MODE REGISTER (MODER) R235 - Read/Write Register Group: E (System) Reset value: 1110 0000 (E0h) Bit 7 =SSP : System Stack Pointer. This bit selects an internal or external System Stack area. 0: External system stack area, in memory space. 1: Internal system stack area, in the Register File (reset state). Bit 6 =USP : User Stack Pointer. This bit selects an internal or external User Stack area. 0: External user stack area, in memory space. 1: Internal user stack area, in the Register File (re- set state). Bit 5 =DIV2: OSCIN Clock Divided by 2. This bit controls the divide-by-2 circuit operating on OSCIN. 0: Clock divided by 1 1: Clock divided by 2 Bit 4:2 =PRS[2:0]: CPUCLK Prescaler. These bits load the prescaler division factor for the internal clock (INTCLK). The prescaler factor se- lects the internal clock frequency, which can be di- vided by a factor from 1 to 8. Refer to the Reset and Clock Control chapter for further information. Bit 1 =BRQEN : Bus Request Enable. 0: External Memory Bus Request disabled 1: External Memory Bus Request enabled on the BREQ pin (where available). Bit 0 =HIMP :High Impedance Enable. When any of Ports 0, 1, 2 or 6 depending on de- vice configuration, are programmed as Address and Data lines to interface external Memory, these lines and the Memory interface control lines (AS, PP5 PP4 PP3 PP2 PP1 PP0 0 0 SSP USP DIV2 PRS2 PRS1 PRS0 BRQEN HIMP

ST90158 - DEVICE ARCHITECTURE SYSTEM REGISTERS (Cont’d) DS, R/W) can be forced into the High Impedance state by setting the HIMP bit. When this bit is reset, it has no effect. Setting the HIMP bit is recommended for noise re- duction when only internal Memory is used. If Port 1 and/or 2 are declared as an address AND as an I/O port (for example: P10... P14 = Address, and P15... P17 = I/O), the HIMP bit has no effect on the I/O lines.

2.3.6 Stack Pointers

Two separate, double-register stack pointers are available: the System Stack Pointer and the User Stack Pointer, both of which can address registers or memory. The stack pointers point to the “bottom” of the stacks which are filled using the push commands and emptied using the pop commands. The stack pointer is automatically pre-decremented when data is “pushed” in and post-incremented when data is “popped” out. The push and pop commands used to manage the System Stack may be addressed to the User Stack by adding the suffix “u”. To use a stack in- struction for a word, the suffix “w”is added. These suffixes may be combined. When bytes (or words) are “popped” out from a stack, the contents of the stack locations are un- changed until fresh data is loaded. Thus, when data is “popped” from a stack area, the stack con- tents remain unchanged. Note: Instructions such as:pushuw RR236or pushw RR238,as well as the corresponding popinstructions (where R236 & R237, and R238 & R239 are themselves the user and system stack pointers respectively), must not be used, since the pointer values are themselves automatically changed by thepushorpopinstruction, thus cor- rupting their value. System Stack The System Stack is used for the temporary stor- age of system and/or control data, such as the Flag register and the Program counter. The following automatically push data onto the System Stack: – Interrupts When entering an interrupt, the PC and the Flag Register are pushed onto the System Stack. If the ENCSR bit in the EMR2 register is set, then the Code Segment Register is also pushed onto the System Stack. – Subroutine Calls When a callinstruction is executed, only the PC is pushed onto stack, whereas when acallsin- struction (call segment) is executed, both the PC and the Code Segment Register are pushed onto the System Stack. – Link Instruction The linkor linkuinstructions create a C lan- guage stack frame of user-defined length in the System or User Stack. All of the above conditions are associated with their counterparts, such as return instructions, which pop the stored data items off the stack. User Stack The User Stack provides a totally user-controlled stacking area. The User Stack Pointer consists of two registers, R236 and R237, which are both used for address- ing a stack in memory. When stacking in the Reg- ister File, the User Stack Pointer High Register, R236, becomes redundant but must be consid- ered as reserved. Stack Pointers Both System and User stacks are pointed to by double-byte stack pointers. Stacks may be set up in RAM or in the Register File. Only the lower byte will be required if the stack is in the Register File. The upper byte must then be considered as re- served and must not be used as a general purpose register. The stack pointer registers are located in the Sys- tem Group of the Register File, this is illustrated in Table 4. Stack location Care is necessary when managing stacks as there is no limit to stack sizes apart from the bottom of any address space in which the stack is placed. Consequently programmers are advised to use a stack pointer value as high as possible, particular- ly when using the Register File as a stacking area. Group D is a good location for a stack in the Reg- ister File, since it is the highest available area. The stacks may be located anywhere in the first 14 groups of the Register File (internal stacks) or in RAM (external stacks). Note. Stacks must not be located in the Paged Register Group or in the System Register Group.

Figure 11. Internal Stack Mode Figure 12. External Stack Mode

0 USP9 USP8

0 SSP9 SSP8

ST90158 - DEVICE ARCHITECTURE

2.4 MEMORY ORGANIZATION

Code and data are accessed within the same line- ar address space. All of the physically separate memory areas, including the internal ROM, inter- nal RAM and external memory are mapped in a common address space. The ST9+ provides a total addressable memory space of 4 Mbytes. This address space is ar- ranged as 64 segments of 64 Kbytes; each seg- ment is again subdivided into four 16 Kbyte pages. The mapping of the various memory areas (inter- nal RAM or ROM, external memory) differs from device to device. Each 64-Kbyte physical memory segment is mapped either internally or externally; if the memory is internal and smaller than 64 Kbytes, the remaining locations in the 64-Kbyte segment are not used (reserved). Refer to the Register and Memory Map Chapter for more details on the memory map.

2.5 MEMORY MANAGEMENT UNIT

may be written and read by the user program. Figure 13. Page 21 Registers

2.6 ADDRESS SPACE EXTENSION

2.6.1 Addressing 16-Kbyte Pages

Data memory space if no DMA is being performed. 22-bit address (see Figure 14). Figure 14. Addressing via DPR[3:0]

2 M SB

14 LSB

2.6.2 Addressing 64-Kbyte Segments

Three registers are used: CSR, ISR, and DMASR. given by the virtual 16-bit address (see Figure 15).

2.7 MMU REGISTERS

2.7.1 DPR[3:0]: Data Page Registers

2.7.1.1 Data Page Register Relocation

Figure 15. Addressing via CSR, ISR, and DMASR

ST90158 - DEVICE ARCHITECTURE MMU REGISTERS (Cont’d) DATA PAGE REGISTER 0 (DPR0) R240 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R224 if EMR2.5 is set. Bit 7:0 =DPR0_[7:0]: These bits define the 16- Kbyte Data Memory page number. They are used as the most significant address bits (A21-14) to ex- tend the address during a Data Memory access. The DPR0 register is used when addressing the virtual address range 0000h-3FFFh. DATA PAGE REGISTER 1 (DPR1) R241 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R225 if EMR2.5 is set. Bit 7:0 =DPR1_[7:0]: These bits define the 16- Kbyte Data Memory page number. They are used as the most significant address bits (A21-14) to ex- tend the address during a Data Memory access. The DPR1 register is used when addressing the virtual address range 4000h-7FFFh. DATA PAGE REGISTER 2 (DPR2) R242 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R226 if EMR2.5 is set. Bit 7:0 =DPR2_[7:0]: These bits define the 16- Kbyte Data memory page. They are used as the most significant address bits (A21-14) to extend the address during a Data memory access. The DPR2 register is involved when the virtual address is in the range 8000h-BFFFh. DATA PAGE REGISTER 3 (DPR3) R243 - Read/Write Register Page: 21 Reset value: undefined This register is relocated to R227 if EMR2.5 is set. Bit 7:0 =DPR3_[7:0]: These bits define the 16- Kbyte Data memory page. They are used as the most significant address bits (A21-14) to extend the address during a Data memory access. The DPR3 register is involved when the virtual address is in the range C000h-FFFFh. DPR0 DPR0 DPR0 DPR0 DPR0 DPR0 DPR0 DPR0 DPR1 DPR1 DPR1 DPR1 DPR1 DPR1 DPR1 DPR1 DPR2 DPR2 DPR2 DPR2 DPR2 DPR2 DPR2 DPR2 DPR3 DPR3 DPR3 DPR3 DPR3 DPR3 DPR3 DPR3

ST90158 - DEVICE ARCHITECTURE MMU REGISTERS (Cont’d)

2.7.2 CSR: Code Segment Register

This register selects the 64-Kbyte code segment being used at run-time to access instructions. It can also be used to access data if thespminstruc- tion has been executed (orldpp, ldpd, lddp). Only the 6 LSBs of the CSR register are imple- mented, and bits 6 and 7 are reserved. The CSR register allows access to the entire memory space, divided into 64 segments of 64 Kbytes. To generate the 22-bit Program memory address, the contents of the CSR register is directly used as the 6 MSBs, and the 16-bit virtual address as the 16 LSBs. Note: The CSR register should only be read and not written for data operations (there are some ex- ceptions which are documented in the following paragraph). It is, however, modified either directly by means of thejpsand callsinstructions, or indirectly via the stack, by means of theretsin- struction. CODE SEGMENT REGISTER (CSR) R244 -Read/Write Register Page: 21 Reset value: 0000 0000 (00h) Bit 7:6 = Reserved, keep in reset state. Bit 5:0 =CSR_[5:0]: These bits define the 64- Kbyte memory segment (among 64) which con- tains the code being executed. These bits are used as the most significant address bits (A21-16).

2.7.3 ISR: Interrupt Segment Register

INTERRUPT SEGMENT REGISTER (ISR) R248 - Read/Write Register Page: 21 Reset value: undefined ISR and ENCSR bit (EMR2 register) are also de- scribed in the chapter relating to Interrupts, please refer to this description for further details. Bit 7:6 = Reserved, keep in reset state. Bit 5:0 =ISR_[5:0]: These bits define the 64-Kbyte memory segment (among 64) which contains the interrupt vector table and the code for interrupt service routines and DMA transfers (when the PS bit of the DAPR register is reset). These bits are used as the most significant address bits (A21-16). The ISR is used to extend the address space in two cases: – Whenever an interrupt occurs: ISR points to the 64-Kbyte memory segment containing the inter- rupt vector table and the interrupt service routine code. See also the Interrupts chapter. – During DMA transactions between the peripheral and memory when the PS bit of the DAPR regis- ter is reset : ISR points to the 64 K-byte Memory segment that will be involved in the DMA trans- action.

2.7.4 DMASR: DMA Segment Register

DMA SEGMENT REGISTER (DMASR) R249 - Read/Write Register Page: 21 Reset value: undefined Bit 7:6 = Reserved, keep in reset state. Bit 5:0 =DMASR_[5:0] : These bits define the 64- Kbyte Memory segment (among 64) used when a DMA transaction is performed between the periph- eral’s data register and Memory, with the PS bit of the DAPR register set. These bits are used as the most significant address bits (A21-16). If the PS bit is reset, the ISR register is used to extend the ad- dress.

00 CSR_

CSR_ CSR_ CSR_ CSR_ CSR_ 0 0 ISR_5 ISR_4 ISR_3 ISR_2 ISR_1 ISR_0

00 DMA

SR_5 DMA SR_4 DMA SR_3 DMA SR_2 DMA SR_1 DMA SR_0

Figure 16. Memory Addressing Scheme (example)

ST90158 - DEVICE ARCHITECTURE

2.8 MMU USAGE

2.8.1 Normal Program Execution

Program memory is organized as a set of 64- Kbyte segments. The program can span as many segments as needed, but a procedure cannot stretch across segment boundaries.jps,calls and retsinstructions, which automatically modify the CSR, must be used to jump across segment boundaries. Writing to the CSR is forbidden during normal program execution because it is not syn- chronized with the opcode fetch. This could result in fetching the first byte of an instruction from one memory segment and the second byte from anoth- er. Writing to the CSR is allowed when it is not be- ing used, i.e during an interrupt service routine if ENCSR is reset. Note that a routine must always be called in the same way, i.e. either always withcallor always withcalls, depending on whether the routine ends withretorrets. This means that if the rou- tine is written without prior knowledge of the loca- tion of other routines which call it, and all the pro- gram code does not fit into a single 64-Kbyte seg- ment, thencalls/retsshould be used. In typical microcontroller applications, less than 64 Kbytes of RAM are used, so the four Data space pages are normally sufficient, and no change of DPR[3:0] is needed during Program execution. It may be useful however to map part of the ROM into the data space if it contains strings, tables, bit maps, etc. If there is to be frequent use of paging, the user can set bit 5 (DPRREM) in register R246 (EMR2) of Page 21. This swaps the location of registers DPR[3:0] with that of the data registers of Ports 0- 3. In this way, DPR registers can be accessed without the need to save/set/restore the Page Pointer Register. Port registers are therefore moved to page 21. Applications that require a lot of paging typically use more than 64 Kbytes of exter- nal memory, and as ports 0, 1 and 2 are required to address it, their data registers are unused.

2.8.2 Interrupts

The ISR register has been created so that the in- terrupt routines may be found by means of the same vector table even after a segment jump/call. When an interrupt occurs, the CPU behaves in one of 2 ways, depending on the value of the ENC- SR bit in the EMR2 register (R246 on Page 21). If this bit is reset (default condition), the CPU works in original ST9 compatibility mode. For the duration of the interrupt service routine, the ISR is used instead of the CSR, and the interrupt stack frame is kept exactly as in the original ST9 (only the PC and flags are pushed). This avoids the need to save the CSR on the stack in the case of an interrupt, ensuring a fast interrupt response time. The drawback is that it is not possible for an interrupt service routine to perform segment calls/jps: these instructions would update the CSR, which, in this case, is not used (ISR is used instead). The code size of all interrupt service rou- tines is thus limited to 64 Kbytes. If, instead, bit 6 of the EMR2 register is set, the ISR is used only to point to the interrupt vector ta- ble and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and the flags, and then the CSR is loaded with the ISR. In this case, aniretwill also restore the CSR from the stack. This approach lets interrupt service routines access the whole 4-Mbyte address space. The drawback is that the interrupt response time is slightly increased, because of the need to also save the CSR on the stack. Compatibility with the original ST9 is also lost in this case, because the interrupt stack frame is different; this difference, however, would not be noticeable for a vast major- ity of programs. Data memory mapping is independent of the value of bit 6 of the EMR2 register, and remains the same as for normal code execution: the stack is the same as that used by the main program, as in the ST9. If the interrupt service routine needs to access additional Data memory, it must save one (or more) of the DPRs, load it with the needed memory page and restore it before completion.

2.8.3 DMA

Depending on the PS bit in the DAPR register (see DMA chapter) DMA uses either the ISR or the DMASR for memory accesses: this guarantees that a DMA will always find its memory seg- ment(s), no matter what segment changes the ap- plication has performed. Unlike interrupts, DMA transactions cannot save/restore paging registers, so a dedicated segment register (DMASR) has been created. Having only one register of this kind means that all DMA accesses should be pro- grammed in one of the two following segments: the one pointed to by the ISR (when the PS bit of the DAPR register is reset), and the one refer- enced by the DMASR (when the PS bit is set).

3 REGISTER AND MEMORY MAP

3.1 MEMORY CONFIGURATION

on-chip memory, is fully available to the user. served for use by STMicroelectronics.

3.2 EPROM PROGRAMMING

grammers available from STMicroelectronics. cation in such an environment. erasure should be a minimum of 15W-sec/cm2. Table 5. First 6 Bytes of Program Space

0 Address high of Power on Reset routine

1 Address low of Power on Reset routine

2 Address high of Divide by zero trap Subroutine

3 Address low of Divide by zero trap Subroutine

4 Address high of Top Level Interrupt routine

5 Address low of Top Level Interrupt routine

Figure 17. Interrupt Vector Table

3.3 MEMORY MAP

Figure 18. Memory Map

128 Kbytes

Note:The total amount of directly addressable external memory is 64 Kbytes.

16 Kbytes

24 Kbytes

32 Kbytes

48 Kbytes

64 Kbytes

1 Kbytes

1.5 Kbytes

2 Kbytes 20F800h

3.4 ST90158/135 REGISTER MAP

registers, grouped by peripheral or function. – Registers common to other functions. rupt Vector table do not overlap. Table 6. Common Registers

Table 7. Group F Pages (*)ST90158/ST90E158 only. Not present on ST90135.

Table 8. Detailed Register Map

ST90158 - REGISTER AND MEMORY MAP I/O Port R240 P4C0 Port 4 Configuration Register 0 FF R241 P4C1 Port 4 Configuration Register 1 00 R242 P4C2 Port 4 Configuration Register 2 00 I/O Port R244 P5C0 Port 5 Configuration Register 0 FF R245 P5C1 Port 5 Configuration Register 1 00 R246 P5C2 Port 5 Configuration Register 2 00 I/O Port R248 P6C0 Port 6 Configuration Register 0 FF R249 P6C1 Port 6 Configuration Register 1 00 R250 P6C2 Port 6 Configuration Register 2 00 R251 P6DR Port 6 Data Register FF I/O Port R252 P7C0 Port 7 Configuration Register 0 00/FF R253 P7C1 Port 7 Configuration Register 1 00/00 R254 P7C2 Port 7 Configuration Register 2 00/00 R255 P7DR Port 7 Data Register FF Page (Decimal) Block Reg. No. Register Name Description Reset Value Hex.

ST90158 - REGISTER AND MEMORY MAP MFT1 R240 REG0HR1 Capture Load Register 0 High xx R241 REG0LR1 Capture Load Register 0 Low xx R242 REG1HR1 Capture Load Register 1 High xx R243 REG1LR1 Capture Load Register 1 Low xx R244 CMP0HR1 Compare 0 Register High 00 R245 CMP0LR1 Compare 0 Register Low 00 R246 CMP1HR1 Compare 1 Register High 00 R247 CMP1LR1 Compare 1 Register Low 00 R248 TCR1 Timer Control Register 0x R249 TMR1 Timer Mode Register 00 R250 ICR1 External Input Control Register 0x R251 PRSR1 Prescaler Register 00 R252 OACR1 Output A Control Register xx R253 OBCR1 Output B Control Register xx R254 FLAGR1 Flags Register 00 R255 IDMR1 Interrupt/DMA Mask Register 00 R244 DCPR0 DMA Counter Pointer Register xx R245 DAPR0 DMA Address Pointer Register xx R246 IVR0 Interrupt Vector Register xx R247 IDCR0 Interrupt/DMA Control Register C7 MFT0,1 R248 IOCR I/O Connection Register FC MFT0 (*) R240 DCPR1 DMA Counter Pointer Register xx R241 DAPR1 DMA Address Pointer Register xx R242 IVR1 Interrupt Vector Register xx R243 IDCR1 Interrupt/DMA Control Register C7 R240 REG0HR0 Capture Load Register 0 High xx R241 REG0LR0 Capture Load Register 0 Low xx R242 REG1HR0 Capture Load Register 1 High xx R243 REG1LR0 Capture Load Register 1 Low xx R244 CMP0HR0 Compare 0 Register High 00 R245 CMP0LR0 Compare 0 Register Low 00 R246 CMP1HR0 Compare 1 Register High 00 R247 CMP1LR0 Compare 1 Register Low 00 R248 TCR0 Timer Control Register 0x R249 TMR0 Timer Mode Register 00 R250 ICR0 External Input Control Register 0x R251 PRSR0 Prescaler Register 00 R252 OACR0 Output A Control Register xx R253 OBCR0 Output B Control Register xx R254 FLAGR0 Flags Register 00 R255 IDMR0 Interrupt/DMA Mask Register 00 Page (Decimal) Block Reg. No. Register Name Description Reset Value Hex.

ST90158 - REGISTER AND MEMORY MAP

11 STIM

R240 STH Counter High Byte Register FF R241 STL Counter Low Byte Register FF R242 STP Standard Timer Prescaler Register FF R243 STC Standard Timer Control Register 14 MFT3 R240 REG0HR1 Capture Load Register 0 High xx R241 REG0LR1 Capture Load Register 0 Low xx R242 REG1HR1 Capture Load Register 1 High xx R243 REG1LR1 Capture Load Register 1 Low xx R244 CMP0HR1 Compare 0 Register High 00 R245 CMP0LR1 Compare 0 Register Low 00 R246 CMP1HR1 Compare 1 Register High 00 R247 CMP1LR1 Compare 1 Register Low 00 R248 TCR1 Timer Control Register 0x R249 TMR1 Timer Mode Register 00 R250 ICR1 External Input Control Register 0x R251 PRSR1 Prescaler Register 00 R252 OACR1 Output A Control Register xx R253 OBCR1 Output B Control Register xx R254 FLAGR1 Flags Register 00 R255 IDMR1 Interrupt/DMA Mask Register 00 R244 DCPR0 DMA Counter Pointer Register xx R245 DAPR0 DMA Address Pointer Register xx R246 IVR0 Interrupt Vector Register xx R247 IDCR0 Interrupt/DMA Control Register C7 MMU R240 DPR0 Data Page Register 0 xx R241 DPR1 Data Page Register 1 xx R242 DPR2 Data Page Register 2 xx R243 DPR3 Data Page Register 3 xx R244 CSR Code Segment Register 00 R248 ISR Interrupt Segment Register xx R249 DMASR DMA Segment Register xx EXTMI R245 EMR1 External Memory Register 1 80 R246 EMR2 External Memory Register 2 0F Page (Decimal) Block Reg. No. Register Name Description Reset Value Hex.

ST90158 - REGISTER AND MEMORY MAP

24 SCI0

R240 RDCPR0 Receiver DMA Transaction Counter Pointer xx R241 RDAPR0 Receiver DMA Source Address Pointer xx R242 TDCPR0 Transmitter DMA Transaction Counter Pointer xx R243 TDAPR0 Transmitter DMA Destination Address Pointer xx R244 IVR0 Interrupt Vector Register xx R245 ACR0 Address/Data Compare Register xx R246 IMR0 Interrupt Mask Register x0 R247 ISR0 Interrupt Status Register xx R248 RXBR0 Receive Buffer Register xx R248 TXBR0 Transmitter Buffer Register xx R249 IDPR0 Interrupt/DMA Priority Register xx R250 CHCR0 Character Configuration Register xx R251 CCR0 Clock Configuration Register 00 R252 BRGHR0 Baud Rate Generator High Reg. xx R253 BRGLR0 Baud Rate Generator Low Register xx R254 SICR0 Synchronous Input Control 03 R255 SOCR0 Synchronous Output Control 01

25 SCI1

(*) R240 RDCPR1 Receiver DMA Transaction Counter Pointer xx R241 RDAPR1 Receiver DMA Source Address Pointer xx R242 TDCPR1 Transmitter DMA Transaction Counter Pointer xx R243 TDAPR1 Transmitter DMA Destination Address Pointer xx R244 IVR1 Interrupt Vector Register xx R245 ACR1 Address/Data Compare Register xx R246 IMR1 Interrupt Mask Register x0 R247 ISR1 Interrupt Status Register xx R248 RXBR1 Receive Buffer Register xx R248 TXBR1 Transmitter Buffer Register xx R249 IDPR1 Interrupt/DMA Priority Register xx R250 CHCR1 Character Configuration Register xx R251 CCR1 Clock Configuration Register 00 R252 BRGHR1 Baud Rate Generator High Reg. xx R253 BRGLR1 Baud Rate Generator Low Register xx R254 SICR1 Synchronous Input Control 03 R255 SOCR1 Synchronous Output Control 01 I/O Port R248 P8C0 Port 8 Configuration Register 0 00/03 R249 P8C1 Port 8 Configuration Register 1 00/00 R250 P8C2 Port 8 Configuration Register 2 00/00 R251 P8DR Port 8 Data Register FF I/O Port R252 P9C0 Port 9 Configuration Register 0 00/00 R253 P9C1 Port 9 Configuration Register 1 00/00 R254 P9C2 Port 9 Configuration Register 2 00/00 R255 P9DR Port 9 Data Register FF Page (Decimal) Block Reg. No. Register Name Description Reset Value Hex.

ST90158 - REGISTER AND MEMORY MAP (*) Not present on ST90135. Note: xx denotes a byte with an undefined value, however some of the bits may have defined values. Refer to register description for details.

55 RCCU

R240 CLKCTL Clock Control Register 00 R242 CLK_FLAG Clock Flag Register 48, 28 or 08 R246 PLLCONF PLL Configuration Register xx

63 AD0

R240 D0R0 Channel 0 Data Register xx R241 D1R0 Channel 1 Data Register xx R242 D2R0 Channel 2 Data Register xx R243 D3R0 Channel 3 Data Register xx R244 D4R0 Channel 4 Data Register xx R245 D5R0 Channel 5 Data Register xx R246 D6R0 Channel 6 Data Register xx R247 D7R0 Channel 7 Data Register xx R248 LT6R0 Channel 6 Lower Threshold Reg. xx R249 LT7R0 Channel 7 Lower Threshold Reg. xx R250 UT6R0 Channel 6 Upper Threshold Reg. xx R251 UT7R0 Channel 7 Upper Threshold Reg. xx R252 CRR0 Compare Result Register 0F R253 CLR0 Control Logic Register 00 R254 ICR0 Interrupt Control Register 0F R255 IVR0 Interrupt Vector Register x2 Page (Decimal) Block Reg. No. Register Name Description Reset Value Hex.

4 INTERRUPTS

4.1 INTRODUCTION

quest which depends on the selected mode. vector table mapped in Memory. Figure 19. Interrupt Response

4.2 INTERRUPT VECTORING

Service Routine automatically. (defined by the programmer). ISR register, thus allowing 8-bit vector addressing. to by the Interrupt Segment Register (ISR). select the appropriate vector. ment pointed to by ISR can contain program code.

4.2.1 Divide by Zero trap

Divide by Zero service routine is required.

4.2.2 Segment Paging During Interrupt

The ENCSR bit in the EMR2 register can be used to select between original ST9 backward compati- bility mode and ST9+ interrupt management mode. ST9 backward compatibility mode (ENCSR = 0) If ENCSR is reset, the CPU works in original ST9 compatibility mode. For the duration of the inter- rupt service routine, ISR is used instead of CSR, and the interrupt stack frame is identical to that of the original ST9: only the PC and Flags are pushed. This avoids saving the CSR on the stack in the event of an interrupt, thus ensuring a faster inter- rupt response time. It is not possible for an interrupt service routine to perform inter-segment calls or jumps: these in- structions would update the CSR, which, in this case, is not used (ISR is used instead). The code segment size for all interrupt service routines is thus limited to 64K bytes. ST9+ mode (ENCSR = 1) If ENCSR is set, ISR is only used to point to the in- terrupt vector table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and flags, and CSR is then loaded with the con- tents of ISR. In this case,iretwill also restore CSR from the stack. This approach allows interrupt service rou- tines to access the entire 4 Mbytes of address space. The drawback is that the interrupt response time is slightly increased, because of the need to also save CSR on the stack. Full compatibility with the original ST9 is lost in this case, because the interrupt stack frame is differ- ent.

4.3 INTERRUPT PRIORITY LEVELS

The ST9 supports a fully programmable interrupt priority structure. Nine priority levels are available to define the channel priority relationships: – The on-chip peripheral channels and the eight external interrupt sources can be programmed within eight priority levels. Each channel has a 3- bit field, PRL (Priority Level), that defines its pri- ority level in the range from 0 (highest priority) to 7 (lowest priority). – The 9th level (Top Level Priority) is reserved for the Timer/Watchdog or the External Pseudo Non-Maskable Interrupt. An Interrupt service routine at this level cannot be interrupted in any arbitration mode. Its mask can be both maskable (TLI) or non-maskable (TLNM).

4.4 PRIORITY LEVEL ARBITRATION

The 3 bits of CPL (Current Priority Level) in the Central Interrupt Control Register contain the pri- ority of the currently running program (CPU priori- ty). CPL is set to 7 (lowest priority) upon reset and can be modified during program execution either by software or automatically by hardware accord- ing to the selected Arbitration Mode. During every instruction, an arbitration phase takes place, during which, for every channel capa- ble of generating an Interrupt, each priority level is compared to all the other requests (interrupts or DMA). If the highest priority request is an interrupt, its PRL value must be strictly lower (that is, higher pri- ority) than the CPL value stored in the CICR regis- ter (R230) in order to be acknowledged. The Top Level Interrupt overrides every other priority.

4.4.1 Priority level 7 (Lowest)

Interrupt requests at PRL level 7 cannot be ac- knowledged, as this PRL value (the lowest possi- ble priority) cannot be strictly lower than the CPL value. This can be of use in a fully polled interrupt environment.

4.4.2 Maximum depth of nesting

No more than 8 routines can be nested. If an inter- rupt routine at level N is being serviced, no other Interrupts located at level N can interrupt it. This guarantees a maximum number of 8 nested levels including the Top Level Interrupt request.

4.4.3 Simultaneous Interrupts

If two or more requests occur at the same time and at the same priority level, an on-chip daisy chain, specific to every ST9 version, selects the channel ENCSR Bit 0 1 Mode ST9 Compatible ST9+ Pushed/Popped Registers PC, FLAGR PC, FLAGR, CSR Max. Code Size for interrupt service routine 64KB Within 1 segment No limit Across segments

Table 9. Daisy Chain Priority

4.4.4 Dynamic Priority Level Modification

Figure 20. Example of Dynamic priority

4.5 ARBITRATION MODES

mode is the standard interrupt arbitration mode. quired, depending on the request priority levels.

4.5.1 Concurrent Mode

– The PC low byte is pushed onto system stack. – The PC high byte is pushed onto system stack. – The Flag register is pushed onto system stack. the Vector Table, pointed to by the IVR. – The Flag register is popped from system stack. – The PC high byte is popped from system stack. – The PC low byte is popped from system stack. – If ENCSR is reset, CSR is used instead of ISR. executed during the interrupt service routine). cause undesirable interrupt response sequences.

Figure 21. Simple Example of a Sequence of Interrupt Requests with:

terminated, thus making the outermost routine fail. Figure 22. Complex Example of a Sequence of Interrupt Requests with:

7 MAIN

4.5.2 Nested Mode

is 3, the bit 3 will be set). the priority level of the suspended routine. – The PC low byte is pushed onto system stack. – The PC high byte is pushed onto system stack. – The Flag register is pushed onto system stack. the Vector Table, pointed to by the IVR. Figure 23. Simple Example of a Sequence of Interrupt Requests with:

– The Flag register is popped from system stack. – The PC high byte is popped from system stack. – The PC low byte is popped from system stack. Figure 24. Complex Example of a Sequence of Interrupt Requests with:

4.6 EXTERNAL INTERRUPTS

rupts sources grouped into four pairs. Table 10. External Interrupt Channel Grouping has the odd (lower) priority level. Figure 25. Priority Level Examples Figure 25 shows an example of priority levels. rupt control bits and vectors. Watchdog peripheral (when IA0S = “0”). INTS = “1”) or the on-chip Standard Timer. INT_SEL = “0”) or the on-chip RCCU. for both peripherals and interrupts. Table 11. Multiplexed Interrupt Sources

Figure 26. External Interrupts Control Bits and

4.7 TOP LEVEL INTERRUPT

reset condition) the source is the external pin NMI. bled in order to allow a Top Level Request. ing some sources due to a change in TLIS. Top Level Interrupt request.

4.8 ON-CHIP PERIPHERAL INTERRUPTS

interrupts and give the status for Interrupt polling. – Interrupt Vector Register(IVR, up to 7 bits). contains the interrupt routine start address. Figure 27. Top Level Interrupt Structure

4.9 INTERRUPT RESPONSE TIME

The interrupt arbitration protocol functions com- pletely asynchronously from instruction flow and requires 5 clock cycles. One more CPUCLK cycle is required when an interrupt is acknowledged. Requests are sampled every 5 CPUCLK cycles. If the interrupt request comes from an external pin, the trigger event must occur a minimum of one INTCLK cycle before the sampling time. When an arbitration results in an interrupt request being generated, the interrupt logic checks if the current instruction (which could be at any stage of execution) can be safely aborted; if this is the case, instruction execution is terminated immedi- ately and the interrupt request is serviced; if not, the CPU waits until the current instruction is termi- nated and then services the request. Instruction execution can normally be aborted provided no write operation has been performed. For an interrupt deriving from an external interrupt channel, the response time between a user event and the start of the interrupt service routine can range from a minimum of 26 clock cycles to a max- imum of 55 clock cycles (DIV instruction), 53 clock cycles (DIVWS and MUL instructions) or 49 for other instructions. For a non-maskable Top Level interrupt, the re- sponse time between a user event and the start of the interrupt service routine can range from a min- imum of 22 clock cycles to a maximum of 51 clock cycles (DIV instruction), 49 clock cycles (DIVWS and MUL instructions) or 45 for other instructions. In order to guarantee edge detection, input signals must be kept low/high for a minimum of one INTCLK cycle. An interrupt machine cycle requires a basic 18 in- ternal clock cycles (CPUCLK), to which must be added a further 2 clock cycles if the stack is in the Register File. 2 more clock cycles must further be added if the CSR is pushed (ENCSR =1). The interrupt machine cycle duration forms part of the two examples of interrupt response time previ- ously quoted; it includes the time required to push values on the stack, as well as interrupt vector handling. In Wait for Interrupt mode, a further cycle is re- quired as wake-up delay.

4.10 INTERRUPT REGISTERS

CENTRAL INTERRUPT CONTROL REGISTER (CICR) R230 - Read/Write Register Group: System Reset value: 1000 0111 (87h) Bit 7 =GCEN : Global Counter Enable. This bit enables the 16-bit Multifunction Timer pe- ripheral. 0: MFT disabled 1: MFT enabled Bit 6 =TLIP: Top Level Interrupt Pending. This bit is set by hardware when Top Level Inter- rupt (TLI) trigger event occurs. It is cleared by hardware when a TLI is acknowledged. It can also be set by software to implement a software TLI. 0: No TLI pending 1: TLI pending Bit 5 =TLI: Top Level Interrupt. This bit is set and cleared by software. 0: A Top Level Interrupt is generared when TLIP is set, only if TLNM=1 in the NICR register (inde- pendently of the value of the IEN bit). 1: A Top Level Interrupt request is generated when IEN=1 and the TLIP bit are set. Bit 4 =IEN:Interrupt Enable. This bit is cleared by the interrupt machine cycle (except for a TLI). It is set by theiretinstruction (except for a return from TLI). It is set by theEIinstruction. It is cleared by theDIinstruction. 0: Maskable interrupts disabled 1: Maskable Interrupts enabled Note: The IEN bit can also be changed by soft- ware using any instruction that operates on regis- ter CICR, however in this case, take care to avoid spurious interrupts, since IEN cannot be cleared in the middle of an interrupt arbitration. Only modify the IEN bit when interrupts are disabled or when no peripheral can generate interrupts. For exam- ple, if the state of IEN is not known in advance, and its value must be restored from a previous push of CICR on the stack, use the sequenceDI; POP CICRto make sure that no interrupts are be- ing arbitrated when CICR is modified. Bit 3 =IAM : Interrupt Arbitration Mode. This bit is set and cleared by software. 0: Concurrent Mode 1: Nested Mode Bit 2:0 =CPL[2:0]: Current Priority Level. These bits define the Current Priority Level. CPL=0 is the highest priority. CPL=7 is the lowest priority. These bits may be modified directly by the interrupt hardware when Nested Interrupt Mode is used. EXTERNAL INTERRUPT TRIGGER REGISTER (EITR) R242 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h) Bit 7 =TED1 : INTD1 Trigger Event Bit 6 =TED0 :INTD0 Trigger Event Bit 5 =TEC1 :INTC1 Trigger Event Bit 4 =TEC0 :INTC0 Trigger Event Bit 3 =TEB1 :INTB1 Trigger Event Bit 2 =TEB0 :INTB0 Trigger Event Bit 1 =TEA1 :INTA1 Trigger Event Bit 0 =TEA0 :INTA0 Trigger Event These bits are set and cleared by software. 0: Select falling edge as interrupt trigger event 1: Select rising edge as interrupt trigger event GCEN TLIP TLI IEN IAM CPL2 CPL1 CPL0 TED1 TED0 TEC1 TEC0 TEB1 TEB0 TEA1 TEA0

INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT PENDING REGISTER (EIPR) R243 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h) Bit 7 =IPD1:INTD1 Interrupt Pending bit Bit 6 =IPD0:INTD0 Interrupt Pending bit Bit 5 =IPC1:INTC1 Interrupt Pending bit Bit 4 =IPC0:INTC0 Interrupt Pending bit Bit 3 =IPB1:INTB1 Interrupt Pending bit Bit 2 =IPB0:INTB0 Interrupt Pending bit Bit 1 =IPA1:INTA1 Interrupt Pending bit Bit 0 =IPA0:INTA0 Interrupt Pending bit These bits are set by hardware on occurrence of a trigger event (as specified in the EITR register) and are cleared by hardware on interrupt acknowl- edge. They can also be set by software to imple- ment a software interrupt. 0: No interrupt pending 1: Interrupt pending EXTERNAL INTERRUPT MASK-BIT REGISTER (EIMR) R244 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h) Bit 7 =IMD1 : INTD1 Interrupt Mask Bit 6 =IMD0 :INTD0 Interrupt Mask Bit 5 =IMC1 :INTC1 Interrupt Mask Bit 4 =IMC0 :INTC0 Interrupt Mask Bit 3 =IMB1 :INTB1 Interrupt Mask Bit 2 =IMB0 :INTB0 Interrupt Mask Bit 1 =IMA1 :INTA1 Interrupt Mask Bit 0 =IMA0 :INTA0 Interrupt Mask These bits are set and cleared by software. 0: Interrupt masked 1: Interrupt not masked (an interrupt is generated if the IPxx and IEN bits = 1) EXTERNAL INTERRUPT PRIORITY LEVEL REGISTER (EIPLR) R245 - Read/Write Register Page: 0 Reset value: 1111 1111 (FFh) Bit 7:6 =PL2D, PL1D: INTD0, D1 Priority Level. Bit 5:4 =PL2C, PL1C:INTC0, C1 Priority Level. Bit 3:2 =PL2B, PL1B:INTB0, B1 Priority Level. Bit 1:0 =PL2A, PL1A:INTA0, A1 Priority Level. These bits are set and cleared by software. The priority is a three-bit value. The LSB is fixed by hardware at 0 for Channels A0, B0, C0 and D0 and at 1 for Channels A1, B1, C1 and D1. IPD1 IPD0 IPC1 IPC0 IPB1 IPB0 IPA1 IPA0 IMD1 IMD0 IMC1 IMC0 IMB1 IMB0 IMA1 IMA0 PL2D PL1D PL2C PL1C PL2B PL1B PL2A PL1A PL2x PL1x Hardware bit Priority 00 0 0 (Highest) 01 0 10 0 11 0 7 (Lowest)

INTERRUPT REGISTERS (Cont’d) EXTERNAL INTERRUPT VECTOR REGISTER (EIVR) R246 - Read/Write Register Page: 0 Reset value: xxxx 0110b (x6h) Bit 7:4 =V[7:4]:Most significant nibble of External Interrupt Vector. These bits are not initialized by reset. For a repre- sentation of how the full vector is generated from V[7:4] and the selected external interrupt channel, refer to Figure 26. Bit 3 =TLTEV :Top Level Trigger Event bit. This bit is set and cleared by software. 0: Select falling edge as NMI trigger event 1: Select rising edge as NMI trigger event Bit 2 =TLIS:Top Level Input Selection. This bit is set and cleared by software. 0: Watchdog End of Count is TL interrupt source 1: NMI is TL interrupt source Bit 1 =IA0S: Interrupt Channel A0 Selection. This bit is set and cleared by software. 0: Watchdog End of Count is INTA0 source 1: External Interrupt pin is INTA0 source Bit 0 =EWEN :External Wait Enable. This bit is set and cleared by software. 0: WAITN pin disabled 1: WAITN pin enabled (to stretch the external memory access cycle). Note:For more details on Wait mode refer to the section describing the WAITN pin in the External Memory Chapter. NESTED INTERRUPT CONTROL (NICR) R247 - Read/Write Register Page: 0 Reset value: 0000 0000 (00h) Bit 7 =TLNM : Top Level Not Maskable. This bit is set by software and cleared only by a hardware reset. 0: Top Level Interrupt Maskable. A top level re- quest is generated if the IEN, TLI and TLIP bits 1: Top Level Interrupt Not Maskable. A top level request is generated if the TLIP bit =1 Bit 6:0 =HL[6:0]: Hold Levelx These bits are set by hardware when, in Nested Mode, an interrupt service routine at level x is in- terrupted from a request with higher priority (other than the Top Level interrupt request). They are cleared by hardware at theiretexecution when the routine at level x is recovered. V7 V6 V5 V4 TLTEV TLIS IAOS EWEN TLNM HL6 HL5 HL4 HL3 HL2 HL1 HL0

INTERRUPT REGISTERS (Cont’d) EXTERNAL MEMORY REGISTER 2 (EMR2) R246 - Read/Write Register Page: 21 Reset value: 0000 1111 (0Fh) Bit 7, 5:0 = Reserved, keep in reset state. Refer to the external Memory Interface Chapter. Bit 6 =ENCSR :Enable Code Segment Register. This bit is set and cleared by software. It affects the ST9 CPU behaviour whenever an interrupt re- quest is issued. 0: The CPU works in original ST9 compatibility mode. For the duration of the interrupt service routine, ISR is used instead of CSR, and the in- terrupt stack frame is identical to that of the orig- inal ST9: only the PC and Flags are pushed. This avoids saving the CSR on the stack in the event of an interrupt, thus ensuring a faster in- terrupt response time. The drawback is that it is not possible for an interrupt service routine to perform inter-segment calls or jumps: these in- structions would update the CSR, which, in this case, is not used (ISR is used instead). The code segment size for all interrupt service rou- tines is thus limited to 64K bytes. 1: ISR is only used to point to the interrupt vector table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and flags, and CSR is then loaded with the contents of ISR. In this case,iretwill also restore CSR from the stack. This approach allows interrupt service routines to access the entire 4 Mbytes of address space; the drawback is that the inter- rupt response time is slightly increased, be- cause of the need to also save CSR on the stack. Full compatibility with the original ST9 is lost in this case, because the interrupt stack frame is different; this difference, however, should not affect the vast majority of programs.

0 ENCSR 0 0 1 1 1 1

5 ON-CHIP DIRECT MEMORY ACCESS (DMA)

5.1 INTRODUCTION

between peripherals and memory or Register File. isters are allocated for the Pointer and Counter.

5.2 DMA PRIORITY LEVELS

can be acknowledged when the CPL=0. the DMA transaction is not interruptable. Figure 28. DMA Data Transfer

5.3 DMA TRANSACTIONS

that have still to be performed. be located in the Register File. Figure 29. DMA Between Register File and Peripheral

bit DCPR.RM (bit 0 of DCPR) must be cleared. of DAPR) must be cleared or set respectively. Mask bit (DM) is set, a DMA request is generated. if the top level interrupt service is in progress. Figure 30. DMA Between Memory and Peripheral

ST90158 - ON-CHIP DIRECT MEMORY ACCESS (DMA) DMA TRANSACTIONS (Cont’d)

5.4 DMA CYCLE TIME

The interrupt and DMA arbitration protocol func- tions completely asynchronously from instruction flow. Requests are sampled every 5 CPUCLK cycles. DMA transactions are executed if their priority al- lows it. A DMA transfer with the Register file requires 8 CPUCLK cycles. A DMA transfer with memory requires 16 CPUCLK cycles, plus any required wait states.

5.5 SWAP MODE

An extra feature which may be found on the DMA channels of some peripherals (e.g. the MultiFunc- tion Timer) is the Swap mode. This feature allows transfer from two DMA tables alternatively. All the DMA descriptors in the Register File are thus dou- bled. Two DMA transaction counters and two DMA address pointers allow the definition of two fully in- dependent tables (they only have to belong to the same space, Register File or Memory). The DMA transaction is programmed to start on one of the two tables (say table 0) and, at the end of the block, the DMA controller automatically swaps to the other table (table 1) by pointing to the other DMA descriptors. In this case, the DMA mask (DM bit) control bit is not cleared, but the End Of Block interrupt request is generated to allow the optional updating of the first data table (table 0). Until the swap mode is disabled, the DMA control- ler will continue to swap between DMA Table 0 and DMA Table 1. n

ST90158 - ON-CHIP DIRECT MEMORY ACCESS (DMA)

5.6 DMA REGISTERS

As each peripheral DMA channel has its own spe- cific control registers, the following register list should be considered as a general example. The names and register bit allocations shown here may be different from those found in the peripheral chapters. DMA COUNTER POINTER REGISTER (DCPR) Read/Write Address set by Peripheral Reset value: undefined Bit 7:1 =C[7:1]: DMA Transaction Counter Point- er. Software should write the pointer to the DMA Transaction Counter in these bits. Bit 0 =RM : Register File/Memory Selector. This bit is set and cleared by software. 0: DMA transactions are with memory (see also DAPR.DP) 1: DMA transactions are with the Register File GENERIC EXTERNAL PERIPHERAL INTER- RUPT AND DMA CONTROL (IDCR) Read/Write Address set by Peripheral Reset value: undefined Bit 5 =IP:Interrupt Pending. This bit is set by hardware when the Trigger Event occurs. It is cleared by hardware when the request is acknowledged. It can be set/cleared by software in order to generate/cancel a pending request. 0: No interrupt pending 1: Interrupt pending Bit 4 =DM : DMA Request Mask. This bit is set and cleared by software. It is also cleared when the transaction counter reaches zero (unless SWAP mode is active). 0: No DMA request is generated when IP is set. 1: DMA request is generated when IP is set Bit 3 =IM: End of block Interrupt Mask. This bit is set and cleared by software. 0: No End of block interrupt request is generated when IP is set 1: End of Block interrupt is generated when IP is set. DMA requests depend on the DM bit value as shown in the table below. Bit 2:0 =PRL[2:0]: Source Priority Level. These bits are set and cleared by software. Refer to Section 5.2 DMA PRIORITY LEVELS for a de- scription of priority levels. DMA ADDRESS POINTER REGISTER (DAPR) Read/Write Address set by Peripheral Reset value: undefined Bit 7:1 =A[7:1]: DMA Address Register(s) Pointer Software should write the pointer to the DMA Ad- dress Register(s) in these bits. Bit 0 =PS :Memory Segment Pointer Selector: This bit is set and cleared by software. It is only meaningful if DAPR.RM=0. 0: The ISR register is used to extend the address of data transferred by DMA (see MMU chapter). 1: The DMASR register is used to extend the ad- dress of data transferred by DMA (see MMU chapter). C7 C6 C5 C4 C3 C2 C1 RM IP DM IM PRL2 PRL1 PRL0 DM IM Meaning

10 A DMA request generated without End of Block

interrupt when IP=1

11 A DMA request generated with End of Block in-

terrupt when IP=1

00 No End of block interrupt or DMA request is

generated when IP=1

01 An End of block Interrupt is generated without

associated DMA request (not used) PRL2 PRL1 PRL0 Source Priority Level

0000 H ighest

1117 L o west

6 RESET AND CLOCK CONTROL UNIT (RCCU)

6.1 INTRODUCTION

manages the internal clock signals. lowest possible power consumption.

6.2 CLOCK CONTROL UNIT

(see Figure 37 and Figure 39).

6.2.1 Clock Control Unit Overview

can divide the CLOCK1 input clock signal by two. rived from a single crystal frequency. Figure 31. Clock Control Unit Simplified Block Diagram

6.3 CLOCK MANAGEMENT

This is a System Register (R235, Group E). prescaler factors are handled by this register. This is a Paged Register (R240, Page 55). the HALT instruction are handled by this register. This is a Paged Register (R242, Page 55). well as control bits for clock selection. This is a Paged Register (R246, Page 55). programmed in this register. Figure 32. Clock Control Unit Programming LPOWFI (CLKCTL) selects Low Power operation automatically on entering WFI mode. WFI_CKSEL (CLKCTL) selects the CK_AF clock automatically, if present, on entering WFI mode. XTSTOP (CLK_FLAG) automatically stops the Xtal oscillator when the CK_AF clock is present and selected.

6.3.1 PLL Clock Multiplier Programming

cycle signal to the PLL multiplier circuit. programmed to 111, the PLL is switched off. CLK_FLAG Register selects the multiplier clock. INTCLK, according to supply voltage. verter precision (if present) decreases.

6.3.2 CPU Clock Prescaling

for the instruction executer of the ST9 CPU core. ripherals are doing most of the work. level is stretched to replace the missing cycles. riod required by the function. Figure 33. CPU Clock Prescaling

6.3.3 Peripheral Clock

6.3.4 Low Power Modes

CPU CLK is stopped but INTCLK is unchanged. setting the appropriate bits.

6.3.5 Interrupt Generation

Table 12. Summary of Operating Modes using main Crystal Controlled Oscillator INTERRUPT If LPOWFI=0, no changes occur on INTCLK, but CPUCLK is stopped anyway.

Figure 34. Example of Low Power mode programming in WFI using CK_AF external clock

2 MHz

20 MHz

Figure 35. Example of Low Power mode programming in WFI using CLOCK2/16

12 MHz

125 KHz

ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU)

6.4 CLOCK CONTROL REGISTERS

MODE REGISTER (MODER) R235 - Read/Write System Register Reset Value: 1110 0000 (E0h) *Note: This register contains bits which relate to other functions; these are described in the chapter dealing with Device Architecture. Only those bits relating to Clock functions are described here. Bit 5 =DIV2:OSCIN Divided by 2. This bit controls the divide by 2 circuit which oper- ates on the OSCIN Clock. 0: No division of the OSCIN Clock 1: OSCIN clock is internally divided by 2 Bit 4:2 =PRS[2:0]: Clock Prescaling. These bits define the prescaler value used to pres- cale CPUCLK from INTCLK. When these three bits are reset, the CPUCLK is not prescaled, and is equal to INTCLK; in all other cases, the internal clock is prescaled by the value of these three bits plus one. CLOCK CONTROL REGISTER (CLKCTL) R240 - Read Write Register Page: 55 Reset Value: 0000 0000 (00h) Bit 7 =INT_SEL : Interrupt Selection. 0: The external interrupt channel input signal is se- lected (Reset state) 1: Select the internal RCCU interrupt as the source of the interrupt request Bit 4:6 =Reserved for test purposes Must be kept reset for normal operation. Bit 3 =SRESEN :Software Reset Enable. 0: The HALT instruction turns off the quartz, the PLL and the CCU 1: A Reset is generated when HALT is executed Bit 2 =CKAF_SEL :Alternate Function Clock Se- lect. 0: CK_AF clock not selected 1: Select CK_AF clock Note: To check if the selection has actually oc- curred, check that CKAF_ST is set. If no clock is present on the CK_AF pin, the selection will not occur. Bit 1 =WFI_CKSEL : WFI Clock Select. This bit selects the clock used in Low power WFI mode if LPOWFI = 1. 0: INTCLK during WFI is CLOCK2/16 1: INTCLK during WFI is CK_AF, providing it is present. In effect this bit sets CKAF_SEL in WFI mode WARNING : When the CK_AF is selected as Low Power WFI clock but the XTAL is not turned off (R242.4 = 0), after exiting from the WFI, CK_AF will be still selected as system clock. In this case, reset the R240.2 bit to switch back to the XT. Bit 0 =LPOWFI : Low Power mode during Wait For Interrupt. 0: Low Power mode during WFI disabled. When WFI is executed, the CPUCLK is stopped and INTCLK is unchanged 1: The ST9 enters Low Power mode when the WFI instruction is executed. The clock during this state depends on WFI_CKSEL - - DIV2 PRS2 PRS1 PRS0 - - INT_S EL --- SRE- SEN CKAF_S EL WFI_CKS EL LPOW FI

ST90158 - RESET AND CLOCK CONTROL UNIT (RCCU) CLOCK CONTROL REGISTERS (Cont’d) CLOCK FLAG REGISTER (CLK_FLAG) R242 -Read/Write Register Page: 55 Reset Value: 0100 10x0 after a Watchdog Reset Reset Value: 0010 10x0 after a Software Reset Reset Value: 0000 10x0 after a Power-On Reset WARNING : If this register is accessed with a logi- cal instruction, such as AND or OR, some bits may not be set as expected. WARNING: If you select the CK_AF as system clock and turn off the oscillator (bits R240.2 and R242.4 at 1), and then switch back to the XT clock by resetting the R240.2 bit, you must wait for the oscillator to restart correctly (12ms). Bit 7 =EX_STP : External Stop flag This bit is set by hardware and cleared by soft- ware. 0: No External Stop condition occurred 1: External Stop condition occurred Bit 6 =WDGRES : Watchdog reset flag. This bit is read only. 0: No Watchdog reset occurred 1: Watchdog reset occurred Bit 5 =SOFTRES :Software Reset Flag. This bit is read only. 0: No software reset occurred 1: Software reset occurred (HALT instruction) Bit 4 =XTSTOP : External Stop Enable 0: External stop disabled 1: The Xtal oscillator will be stopped as soon as the CK_AF clock is present and selected, whether this is done explicitly by the user pro- gram, or as a result of WFI, if WFI_CKSEL has previously been set to select the CK_AF clock during WFI. WARNING: When the program writes ‘1’ to the XTSTOP bit, it will still be read as 0 and is only set when the CK_AF clock is running (CKAF_ST=1). Take care, as any operation such as a subsequent AND with ‘1’ or an OR with ‘0’ to the XTSTOP bit will reset it and the oscillator will not be stopped even if CKAF_ST is subsequently set. Bit 3 =XT_DIV16 :CLOCK/16 Selection This bit is set and cleared by software. An interrupt is generated when the bit is toggled. 0: CLOCK2/16 is selected and the PLL is off 1: The input is CLOCK2 (or the PLL output de- pending on the value of CSU_CKSEL) WARNING: After this bit is modified from 0 to 1, take care that the PLL lock-in time has elapsed be- fore setting the CSU_CKSEL bit. Bit 2 =CKAF_ST : (Read Only) If set, indicates that the alternate function clock has been selected. If no clock signal is present on the CK_AF pin, the selection will not occur. If re- set, the PLL clock, CLOCK2 or CLOCK2/16 is se- lected (depending on bit 0). Bit 0 =CSU_CKSEL : CSU Clock Select This bit is set and cleared by software. It is also cleared by hardware when: – bits DX[2:0] (PLLCONF) are set to 111; – the quartz is stopped (by hardware or software); – WFI is executed while the LPOWFI bit is set; – the XT_DIV16 bit (CLK_FLAG) is forced to ’0’. This prevents the PLL, when not yet locked, from providing an irregular clock. Furthermore, a ‘0’ stored in this bit speeds up the PLL’s locking. 0: CLOCK2 provides the system clock 1: The PLL Multiplier provides the system clock. NOTE : Setting the CKAF_SEL bit overrides any other clock selection. Resetting the XT_DIV16 bit EX_ STP WDGRE S SOF- TRES XT- STOP XT_ DIV16 CKAF_ ST - CSU_ CK- SEL

Bit 5:4 =MX[1:0]:PLL Multiplication Factor. Refer to Table 13 for multiplier settings. PLL output clock divider factor. Refer to Table 14 for divider settings. Table 13. PLL Multiplication Factors Table 14. Divider Configuration Figure 36. RCCU General Timing

111 CLOCK2

6.5 OSCILLATOR CHARACTERISTICS

circuit with tri-state output. out or when an external reset is applied. Table 15. Oscillator Transconductance Figure 37. Crystal Oscillator Table 16. Crystal Internal Resistance(Ω ) (5V Table 17. Crystal Internal Resistance(Ω ) (3V itance of the board and of the device). crystal only (not ceramic resonator). Figure 38. Internal Oscillator Schematic Figure 39. External Clock

5 Mhz 110 120 210 340

4 Mhz 150 200 330 510

3 Mhz 270 350 560 850

5 Mhz 35 45 75 120

4 Mhz 55 70 125 195

3 Mhz 100 135 220 350

Murata Electronics CERALOCK resonators have been tested with the ST90158 at 3, 3.68, 4 and 5 MHz. Some resonators have built-in capacitors (see Table 18). The test circuit is shown in Figure 40. Figure 40. Test circuit Table 18 shows the recommended conditions at different frequencies. Table 18. Obtained Results nator (it is needed only with a crystal).

6.6 RESET/STOP MANAGER

– A Watchdog end of count condition. ware initiated reset will leave both these bits reset. set to the Bidirectional Weak Pull-up mode. is driven low, a Reset cycle is initiated. Figure 41. Oscillator Start-up Sequence and Reset Timing

code (AAh, 55h) written to the appropriate register. chip reset generated by the Timer/Watchdog. depending on the Boot ROM contents. Vector located in the lowest two bytes of memory.

6.6.1 RESET Pin Timing

nal Program memory with wait cycles insertion. Figure 42. Recommended Signal to be Applied on RESET Pin

6.7 EXTERNAL STOP MODE

cillators without resetting the device. clock will be frozen in the high state.

0.7 VDD

0.3 VDD

7 EXTERNAL MEMORY INTERFACE (EXTMI)

7.1 INTRODUCTION

also affected by WCR - R252 Page 0. clock phases, named T1 and T2. ble until the following T1 phase. Figure 43. Page 21 Registers

ST90158 - EXTERNAL MEMORY INTERFACE (EXTMI)

7.2 EXTERNAL MEMORY SIGNALS

The access to external memory is made using the AS, DS, DS2, RW, Port 0, Port1, and WAIT signals described below. Refer to Figure 45

7.2.1 AS: Address Strobe

AS (Output, Active low, Tristate) is active during the System Clock high-level phase of each T1 memory cycle: an AS rising edge indicates that Memory Address and Read/Write Memory control signals are valid. AS is released in high-imped- ance during the bus acknowledge cycle or under the processor control by setting the HIMP bit (MODER.0, R235). Depending on the device AS is available as Alternate Function or as a dedicated pin. Under Reset, AS is held high with an internal weak pull-up. The behavior of this signal is affected by the MC, ASAF, ETO, BSZ, LAS[1:0] and UAS[1:0] bits in the EMR1 or EMR2 registers. Refer to the Regis- ter description.

7.2.2 DS: Data Strobe

DS (Output,Active low,Tristate) is active during the internal clock high-level phase of each T2 memory cycle. During an external memory read cycle, the data on Port 0 must be valid before the DS rising edge. During an external memory write cycle, the data on Port 0 are output on the falling edge of DS and they are valid on the rising edge of DS. When the internal memory is accessed DS is kept high during the whole memory cycle. DS is released in high-impedance during bus acknowledge cycle or under processor control by setting the HIMP bit (MODER.0, R235). Under Reset status, DS is held high with an internal weak pull-up. The behavior of this signal is affected by the MC, DS2EN, and BSZ bits in the EMR1 register. Refer to the Register description.

7.2.3 DS2: Data Strobe 2

This additional Data Strobe pin (Alternate Function Output, Active low, Tristate) is available on some ST9 devices only. It allows two external memories to be connected to the ST9, the upper memory block (A21=1 typically RAM) and the lower memo- ry block (A21=0 typically ROM) without any exter- nal logic. The selection between the upper and lower memory blocks depends on the A21 address pin value. The upper memory block is controlled by the DS pin while the lower memory block is controlled by the DS2 pin. When the internal memory is ad- dressed, DS2 is kept high during the whole mem- ory cycle. DS2 is released in high-impedance dur- ing bus acknowledge cycle or under processor control by setting the HIMP bit (MODER.0, R235). DS2 is enabled via software as the Alternate Func- tion output of the associated I/O port bit (refer to specific ST9 version to identify the specific port and pin). The behavior of this signal is affected by the DS2EN, and BSZ bits in the EMR1 register. Refer to the Register description.

Figure 44. Effects of DS2EN on the behavior of DS and DS2

Figure 45. External memory Read/Write with a programmable wait

7.2.4 RW: Read/Write

7.2.5 BREQ, BACK: Bus Request, Bus

devices (see Pin description). the processor internal clock during phase T2. Figure 46. External memory Read/Write sequence with external wait (WAIT pin)

signals are released in high-impedance. At MCU reset, the bus request function is disabled. the BRQEN bit in the MODER register.

7.2.6 PORT 0

7.2.7 PORT 1

to the Register description.

7.2.8 WAIT: External Memory Wait

ternal clock cycle is added to the memory cycle. Figure 47. Application Example

ST90158 - EXTERNAL MEMORY INTERFACE (EXTMI)

7.3 REGISTER DESCRIPTION

EXTERNAL MEMORY REGISTER 1 (EMR1) R245 - Read/Write Register Page: 21 Reset value: 1000 0000 (80h) Bit 7 = Reserved. Bit 6 =MC : Mode Control. 0: AS, DS and RW pins keep the ST9OLD mean- ing. 1: AS pin becomes ALE, Address Load Enable (AS inverted); Thus Memory Adress, Read/ Write signals are valid whenever a falling edge of ALE occurs. DS becomes OEN, Output ENable: it keeps the ST9OLD meaning during external read opera- tions, but is forced to “1” during external write operations. RW pin becomes WEN, Write ENable: it follows the ST9OLD DS meaning during external write operations, but is forced to “1” during external read operations. Bit 5 =DS2EN : Data Strobe 2 enable. 0: The DS2 pin is forced to “1” during the whole memory cycle. 1: If the lower memory block is addressed, the DS2 pin follows the ST9OLD DS meaning (if MC=0) or it becomes OEN (if MC=1). The DS pin is forced to 1 during the whole memory cy- cle. If the upper memory block is used, DS2 is forced to “1” during the whole memory cycle. The DS pin behaviour is not modified. Refer to Figure 44 Bit 4 =ASAF : Address Strobe as Alternate Func- tion. Depending on the device, AS can be either a ded- icated pin or a port Alternate Function. This bit is used only in the second case. 0: AS Alternate function disabled. 1: AS Alternate Function enabled. Bit 2 =ETO : External toggle. 0: The external memory interface pins (AS, DS, DS2, RW, Port0, Port1) toggle only if an access to external memory is performed. 1: When the internal memory protection is dis- abled (mask option available on some devices only), the above pins (except DS and DS2 which never toggle during internal memory accesses) toggle during both internal and external memory accesses. Bit 1 =BSZ : Bus size. 0: All the I/O ports including the external memory interface pins use smaller, less noisy output buffers. This may limit the operation frequency of the device, unless the clock is slow enough or sufficient wait states are inserted. 1: All the I/O ports including the external memory interface pins (AS, DS, DS2, R/W, Port 0, 1) use larger, more noisy output buffers . Bit 0 = Reserved. WARNING : External memory must be correctly addressed before and after a write operation on the EMR1 register. For example, if code is fetched from external memory using the ST9OLD external memory interface configuration (MC=0), setting the MC bit will cause the device to behave unpre- dictably. x MC DS2EN ASAF x ETO BSZ X

ST90158 - EXTERNAL MEMORY INTERFACE (EXTMI) REGISTER DESCRIPTION (Cont’d) EXTERNAL MEMORY REGISTER 2 (EMR2) R246 - Read/Write Register Page: 21 Reset value: 0000 1111 (0Fh) Bit 7 = Reserved. Bit 6 =ENCSR :Enable Code Segment Register. This bit affects the ST9 CPU behavior whenever an interrupt request is issued. 0: The CPU works in original ST9 compatibility mode concerning stack frame during interrupts. For the duration of the interrupt service routine, ISR is used instead of CSR, and the interrupt stack frame is identical to that of the original ST9: only the PC and Flags are pushed. This avoids saving the CSR on the stack in the event of an interrupt, thus ensuring a faster interrupt response time. The drawback is that it is not possible for an interrupt service routine to per- form inter-segment calls or jumps: these instruc- tions would update the CSR, which, in this case, is not used (ISR is used instead). The code seg- ment size for all interrupt service routines is thus limited to 64K bytes. 1: If ENCSR is set, ISR is only used to point to the interrupt vector table and to initialize the CSR at the beginning of the interrupt service routine: the old CSR is pushed onto the stack together with the PC and flags, and CSR is then loaded with the contents of ISR. In this case, iret will also re- store CSR from the stack. This approach allows interrupt service routines to access the entire 4Mbytes of address space; the drawback is that the interrupt response time is slightly increased, because of the need to also save CSR on the stack. Full compatibility with the original ST9 is lost in this case, because the interrupt stack frame is different; this difference, however, should not affect the vast majority of programs. Bit 5 =DPRREM : Data Page Registers remapping 0: The locations of the four MMU (Memory Man- agement Unit) Data Page Registers (DPR0, DPR1, DPR2 and DPR3) are in page 21. 1: The four MMU Data Page Registers are swapped with that of the Data Registers of ports 0-3. Refer to Figure 43 Bit 4 =MEMSEL : Memory Selection. Warning: Must be set by the user when using the external memory interface (Reset value is 0) Bit 3:2 =LAS[1:0]:Lower memory address strobe stretch. These two bits contain the number of wait cycles (from 0 to 3) to add to the System Clock to stretch AS during external lower memory block accesses (MSB of 22-bit internal address=0). The reset val- ue is 3. - ENCSR DPRREM MEM SEL LAS1 LAS0 UAS1 UAS0

ST90158 - EXTERNAL MEMORY INTERFACE (EXTMI) REGISTER DESCRIPTION (Cont’d) Bit 1:0 =UAS[1:0]:Upper memory address strobe stretch. These two bits contain the number of wait cycles (from 0 to 3) to add to the System Clock to stretch AS during external upper memory block accesses (MSB of 22-bit internal address=1). The reset val- ue is 3. WARNING : The EMR2 register cannot be written during an interrupt service routine. WAIT CONTROL REGISTER (WCR) R252 - Read/Write Register Page: 0 Reset Value: 0111 1111 (7Fh) Bit 7 = Reserved, forced by hardware to 0. Bit 6 =WDGEN : Watchdog Enable. For a description of this bit, refer to the Timer/ Watchdog chapter. WARNING : Clearing this bit has the effect of set- ting the Timer/Watchdog to Watchdog mode. Un- less this is desired, it must be set to “1”. Bit 5:3 =UDS[2:0]: Upper memory data strobe stretch. These bits contain the number of INTCLK cycles to be added automatically to DS for external upper memory block accesses. UDS = 0 adds no addi- tional wait cycles. UDS = 7 adds the maximum 7 INTCLK cycles (reset condition). Bit 2:0 =LDS[2:0]: Lower memory data strobe stretch. These bits contain the number of INTCLK cycles to be added automatically to DS or DS2 (depend- ing on the DS2EN bit of the EMR1 register) for ex- ternal lower memory block accesses. LDS = 0 adds no additional wait cycles, LDS = 7 adds the maximum 7 INTCLK cycles (reset condition). Note 1:The number of clock cycles added refers to INTCLK and NOT to CPUCLK. Note 2:The distinction between the Upper memo- ry block and the Lower memory block allows differ- ent wait cycles between the first 2 Mbytes and the second 2 Mbytes, and allows 2 different data strobe signals to be used to access 2 different memories. Typically, the RAM will be located above address 0x200000 and the ROM below address 0x1FFFFF, with different access times. No extra hardware is required as DS is used to access the upper memory block and DS2 is used to access the lower memory block. WARNING: The reset value of the Wait Control Register gives the maximum number of Wait cy- cles for external memory. To get optimum perfor- mance from the ST9, the user should write the UDS[2:0] and LDS[2:0] bits to 0, if the external ad- dressed memories are fast enough.

0 WDGEN UDS2 UDS1 UDS0 LDS2 LDS1 LDS0

8 I/O PORTS

8.1 INTRODUCTION

hardware to operate as Schmitt triggers.

8.2 SPECIFIC PORT CONFIGURATIONS

specific port styles and reset values.

8.3 PORT CONTROL REGISTERS

memory or “accumulator” locations. Figure 48. I/O Register Map

PORT CONTROL REGISTERS (Cont’d) During Reset, ports with weak pull-ups are set in bidirectional/weak pull-up mode and the output Data Register is set to FFh. This condition is also held after Reset, except for Ports 0 and 1 in ROM- less devices, and can be redefined under software control. Bidirectional ports without weak pull-ups are set in high impedance during reset. To ensure proper levels during reset, these ports must be externally connected to either V DD or VSS through external pull-up or pull-down resistors. Other reset conditions may apply in specific ST9 devices.

8.4 INPUT/OUTPUT BIT CONFIGURATION

By programming the control bits PxC0.n and PxC1.n (see Figure 49) it is possible to configure bit Px.n as Input, Output, Bidirectional or Alternate Function Output, where X is the number of the I/O port, and n the bit within the port (n = 0 to 7). When programmed as input, it is possible to select the input level as TTL or CMOS compatible by pro- gramming the relevant PxC2.n control bit, except where the Schmitt trigger option is assigned to the pin. The output buffer can be programmed as push- pull or open-drain. A weak pull-up configuration can be used to avoid external pull-ups when programmed as bidirec- tional (except where the weak pull-up option has been permanently disabled in the pin hardware as- signment). Each pin of an I/O port may assume software pro- grammable Alternate Functions (refer to the de- vice Pin Description and to Section 8.5 ALTER- NATE FUNCTION ARCHITECTURE). To output signals from the ST9 peripherals, the port must be configured as AF OUT. On ST9 devices with A/D Converter(s), configure the ports used for analog inputs as AF IN. The basic structure of the bit Px.n of a general pur- pose port Px is shown in Figure 50. Independently of the chosen configuration, when the user addresses the port as the destination reg- ister of an instruction, the port is written to and the data is transferred from the internal Data Bus to the Output Master Latches. When the port is ad- dressed as the source register of an instruction, the port is read and the data (stored in the Input Latch) is transferred to the internal Data Bus. When Px.n is programmed as an Input: (See Figure 51). – The Output Buffer is forced tristate. – The data present on the I/O pin is sampled into the Input Latch at the beginning of each instruc- tion execution. – The data stored in the Output Master Latch is copied into the Output Slave Latch at the end of the execution of each instruction. Thus, if bit Px.n is reconfigured as an Output or Bidirectional, the data stored in the Output Slave Latch will be re- flected on the I/O pin.

Figure 49. Control Bits Table 19. Port Bit Configuration Table (n = 0, 1... 7; X = port number) (1)For A/D Converter inputs.

8.5 ALTERNATE FUNCTION ARCHITECTURE

Each I/O pin may be connected to three different types of internal signal: – Data bus Input/Output – Alternate Function Input – Alternate Function Output

8.5.1 Pin Declared as I/O

A pin declared as I/O, is connected to the I/O buff- er. This pin may be an Input, an Output, or a bidi- rectional I/O, depending on the value stored in (PxC2, PxC1 and PxC0).

8.5.2 Pin Declared as an Alternate Input

A single pin may be directly connected to several Alternate inputs. In this case, the user must select the required input mode (with the PxC2, PxC1, PxC0 bits) and enable the selected Alternate Function in the Control Register of the peripheral. No specific port configuration is required to enable an Alternate Function input, since the input buffer is directly connected to each alternate function module on the shared pin. As more than one mod- ule can use the same input, it is up to the user soft- ware to enable the required module as necessary. Parallel I/Os remain operational even when using an Alternate Function input. The exception to this is when an I/O port bit is permanently assigned by hardware as an A/D bit. In this case , after soft- ware programming of the bit in AF-OD-TTL, the Al- ternate function output is forced to logic level 1. The analog voltage level on the corresponding pin is directly input to the A/D.

8.5.3 Pin Declared as an Alternate Function

The user must select the AF OUT configuration using the PxC2, PxC1, PxC0 bits. Several Alter- nate Function outputs may drive a common pin. In such case, the Alternate Function output signals are logically ANDed before driving the common pin. The user must therefore enable the required Alternate Function Output by software. WARNING : When a pin is connected both to an al- ternate function output and to an alternate function input, it should be noted that the output signal will always be present on the alternate function input.

8.6 I/O STATUS AFTER WFI, HALT AND RESET

The status of the I/O ports during the Wait For In- terrupt, Halt and Reset operational modes is shown in the following table. The External Memory Interface ports are shown separately. If only the in- ternal memory is being used and the ports are act- ing as I/O, the status is the same as shown for the other I/O ports. Mode Ext. Mem - I/O Ports I/O PortsP0 P1, P2, P6 WFI High Imped- ance or next address (de- pending on the last memory op- eration per- formed on Port) Next Address Not Affected (clock outputs running) HALT High Imped- ance Next Address Not Affected (clock outputs stopped) RESET Alternate function push- pull (ROMless device) Bidirectional Weak Pull-up (High im- pedance when disa- bled in hardware).

9 ON-CHIP PERIPHERALS

9.1 TIMER/WATCHDOG (WDT)

in the first section of the data sheet.

9.1.1 Introduction

Figure 55. Timer/Watchdog Block Diagram 1Pin not present on some ST9 devices.

ST90158 - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d)

9.1.2 Functional Description

9.1.2.1 External Signals

The HW0SW1 pin can be used to permanently en- The WDIN Input pin can be used in one of four modes: – Event Counter Mode – Gated External Input Mode – Triggerable Input Mode – Retriggerable Input Mode The WDOUT output pin can be used to generate a square wave or a Pulse Width Modulated signal. An interrupt, generated when the WDT is running as the 16-bit Timer/Counter, can be used as a Top Level Interrupt or as an interrupt source connected to channel A0 of the external interrupt structure (replacing the INT0 interrupt input). The counter can be driven either by an external clock, or internally by INTCLK divided by 4.

9.1.2.2 Initialisation

The prescaler (WDTPR) and counter (WDTRL, WDTRH) registers must be loaded with initial val- ues before starting the Timer/Counter. If this is not done, counting will start with reset values.

9.1.2.3 Start/Stop

The ST_SP bit enables downcounting. When this bit is set, the Timer will start at the beginning of the following instruction. Resetting this bit stops the counter. If the counter is stopped and restarted, counting will resume from the last value unless a new con- stant has been entered in the Timer registers (WDTRL, WDTRH). A new constant can be written in the WDTRH, WDTRL, WDTPR registers while the counter is running. The new value of the WDTRH, WDTRL registers will be loaded at the next End of Count (EOC) condition while the new value of the WDTPR register will be effective immediately. End of Count is when the counter is 0. When Watchdog mode is enabled the state of the ST_SP bit is irrelevant.

9.1.2.4 Single/Continuous Mode

The S_C bit allows selection of single or continu- ous mode.This Mode bit can be written with the Timer stopped or running. It is possible to toggle the S_C bit and start the counter with the same in- struction. Single Mode On reaching the End Of Count condition, the Timer stops, reloads the constant, and resets the Start/ Stop bit. Software can check the current status by reading this bit. To restart the Timer, set the Start/ Stop bit. Note:If the Timer constant has been modified dur- ing the stop period, it is reloaded at start time. Continuous Mode On reaching the End Of Count condition, the coun- ter automatically reloads the constant and restarts. It is stopped only if the Start/Stop bit is reset.

9.1.2.5 Input Section

If the Timer/Counter input is enabled (INEN bit) it can count pulses input on the WDIN pin. Other- wise it counts the internal clock/4. For instance, when INTCLK = 20MHz, the End Of Count rate is: 3.35 seconds for Maximum Count (Timer Const. = FFFFh, Prescaler Const. = FFh) 200 ns for Minimum Count (Timer Const. = 0000h, Prescaler Const. = 00h) The Input pin can be used in one of four modes: – Event Counter Mode – Gated External Input Mode – Triggerable Input Mode – Retriggerable Input Mode The mode is configurable in the WDTCR.

9.1.2.6 Event Counter Mode

In this mode the Timer is driven by the external clock applied to the input pin, thus operating as an event counter. The event is defined as a high to low transition of the input signal. Spacing between trailing edges should be at least 8 INTCLK periods (or 400ns with INTCLK = 20MHz). Counting starts at the next input event after the ST_SP bit is set and stops when the ST_SP bit is reset.

ST90158 - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d)

9.1.2.7 Gated Input Mode

This mode can be used for pulse width measure- ment. The Timer is clocked by INTCLK/4, and is started and stopped by means of the input pin and the ST_SP bit. When the input pin is high, the Tim- er counts. When it is low, counting stops. The maximum input pin frequency is equivalent to INTCLK/8.

9.1.2.8 Triggerable Input Mode

The Timer (clocked internally by INTCLK/4) is started by the following sequence: – setting the Start-Stop bit, followed by – a High to Low transition on the input pin. To stop the Timer, reset the ST_SP bit.

9.1.2.9 Retriggerable Input Mode

In this mode, the Timer (clocked internally by INTCLK/4) is started by setting the ST_SP bit. A High to Low transition on the input pin causes counting to restart from the initial value. When the Timer is stopped (ST_SP bit reset), a High to Low transition of the input pin has no effect.

9.1.2.10 Timer/Counter Output Modes

Output modes are selected by means of the OUT- EN (Output Enable) and OUTMD (Output Mode) bits of the WDTCR register. No Output Mode (OUTEN = “0”) The output is disabled and the corresponding pin is set high, in order to allow other alternate func- tions to use the I/O pin. Square Wave Output Mode (OUTEN = “1”, OUTMD = “0”) The Timer outputs a signal with a frequency equal to half the End of Count repetition rate on the WD- OUT pin. With an INTCLK frequency of 20MHz, this allows a square wave signal to be generated whose period can range from 400ns to 6.7 sec- onds. Pulse Width Modulated Output Mode (OUTEN = “1”, OUTMD = “1”) The state of the WROUT bit is transferred to the output pin (WDOUT) at the End of Count, and is held until the next End of Count condition. The user can thus generate PWM signals by modifying the status of the WROUT pin between End of Count events, based on software counters decre- mented by the Timer Watchdog interrupt.

9.1.3 Watchdog Timer Operation

This mode is used to detect the occurrence of a software fault, usually generated by external inter- ference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence of operation. The Watchdog, when enabled, resets the MCU, unless the pro- gram executes the correct write sequence before expiry of the programmed time period. The appli- cation program must be designed so as to correct- ly write to the WDTLR Watchdog register at regu- lar intervals during all phases of normal operation.

9.1.3.1 Hardware Watchdog/Software

The HW0SW1 pin (when available) selects Hard- ware Watchdog or Software Watchdog. If HW0SW1 is held low: – The Watchdog is enabled by hardware immedi- ately after an external reset. (Note: Software re- set or Watchdog reset have no effect on the Watchdog enable status). – The initial counter value (FFFFh) cannot be mod- ified, however software can change the prescaler value on the fly. – The WDGEN bit has no effect. (Note: it is not forced low). If HW0SW1 is held high, or is not present: – The Watchdog can be enabled by resetting the WDGEN bit.

9.1.3.2 Starting the Watchdog

In Watchdog mode the Timer is clocked by INTCLK/4. If the Watchdog is software enabled, the time base must be written in the timer registers before enter- ing Watchdog mode by resetting the WDGEN bit. Once reset, this bit cannot be changed by soft- ware. If the Watchdog is hardware enabled, the time base is fixed by the reset value of the registers. Resetting WDGEN causes the counter to start, re- gardless of the value of the Start-Stop bit. In Watchdog mode, only the Prescaler Constant may be modified. If the End of Count condition is reached a System Reset is generated.

9.1.3.3 Preventing Watchdog System Reset

starts from the preset value. WDTLR register between the writing operations.

9.1.3.4 Non-Stop Operation

Continuous Mode, driven by the internal clock. this context it is meaningless. Figure 56. Watchdog Timer Mode

9.1.4 WDT Interrupts

source forchannel A0 of the external interrupt logic. the appropriate interrupt pending bit. Figure 57. Interrupt Sources Table 20. Interrupt Configuration interrupts), only the INTA0 interrupt is taken into account.

ST90158 - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d)

9.1.5 Register Description

The Timer/Watchdog is associated with 4 registers mapped into Group F, Page 0 of the Register File. WDTHR : Timer/Watchdog High Register WDTLR : Timer/Watchdog Low Register WDTPR : Timer/Watchdog Prescaler Register WDTCR : Timer/Watchdog Control Register Three additional control bits are mapped in the fol- lowing registers on Page 0: Watchdog Mode Enable, (WCR.6) Top Level Interrupt Selection, (EIVR.2) Interrupt A0 Channel Selection, (EIVR.1) Note: The registers containing these bits also con- tain other functions. Only the bits relevant to the operation of the Timer/Watchdog are shown here. Counter Register This 16 bit register (WDTLR, WDTHR) is used to load the 16 bit counter value. The registers can be read or written “on the fly”. TIMER/WATCHDOG HIGH REGISTER (WDTHR) R248 - Read/Write Register Page: 0 Reset value: 1111 1111 (FFh) Bit 7:0 =R[15:8] Counter Most Significant Bits. TIMER/WATCHDOG LOW REGISTER (WDTLR) R249 - Read/Write Register Page: 0 Reset value: 1111 1111b (FFh) Bit 7:0 =R[7:0] Counter Least Significant Bits. TIMER/WATCHDOG PRESCALER REGISTER (WDTPR) R250 - Read/Write Register Page: 0 Reset value: 1111 1111 (FFh) Bit 7:0 =PR[7:0]Prescaler value. A programmable value from 1 (00h) to 256 (FFh). Warning:In order to prevent incorrect operation of the Timer/Watchdog, the prescaler (WDTPR) and counter (WDTRL, WDTRH) registers must be ini- tialised before starting the Timer/Watchdog. If this is not done, counting will start with the reset (un-in- itialised) values. WATCHDOG TIMER CONTROL REGISTER (WDTCR) R251- Read/Write Register Page: 0 Reset value: 0001 0010 (12h) Bit 7 =ST_SP :Start/Stop Bit. This bit is set and cleared by software. 0: Stop counting 1: Start counting (see Warning above) Bit 6 =S_C :Single/Continuous. This bit is set and cleared by software. 0: Continuous Mode 1: Single Mode Bit 5:4 =INMD[1:2]:Input mode selection bits. These bits select the input mode: R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 PR7 PR6 PR5 PR4 PR3 PR2 PR1 PR0 ST_SP S_C INMD1 INMD2 INEN OUTMD WROUT OUTEN INMD1 INMD2 INPUT MODE 0 0 Event Counter 0 1 Gated Input (Reset value) 1 0 Triggerable Input 1 1 Retriggerable Input

ST90158 - TIMER/WATCHDOG (WDT) TIMER/WATCHDOG (Cont’d) Bit 3 =INEN :Input Enable. This bit is set and cleared by software. 0: Disable input section 1: Enable input section Bit 2 =OUTMD :Output Mode. This bit is set and cleared by software. 0: The output is toggled at every End of Count 1: The value of the WROUT bit is transferred to the output pin on every End Of Count if OUTEN=1. Bit 1 =WROUT : Write Out. The status of this bit is transferred to the Output pin when OUTMD is set; it is user definable to al- low PWM output (on Reset WROUT is set). Bit 0 =OUTEN :Output Enable bit. This bit is set and cleared by software. 0: Disable output 1: Enable output WAIT CONTROL REGISTER (WCR) R252 - Read/Write Register Page: 0 Reset value: 0111 1111 (7Fh) Bit 6 =WDGEN : Watchdog Enable(active low). Resetting this bit via software enters the Watch- dog mode. Once reset, it cannot be set anymore by the user program. At System Reset, the Watch- dog mode is disabled. Note:This bit is ignored if the Hardware Watchdog option is enabled by pin HW0SW1 (if available). EXTERNAL INTERRUPT VECTOR REGISTER (EIVR) R246 - Read/Write Register Page: 0 Reset value: xxxx 0110 (x6h) Bit 2 =TLIS: Top Level Input Selection. This bit is set and cleared by software. 0: Watchdog End of Count is TL interrupt source 1: NMI is TL interrupt source Bit 1 =IA0S: Interrupt Channel A0 Selection. This bit is set and cleared by software. 0: Watchdog End of Count is INTA0 source 1: External Interrupt pin is INTA0 source Warning: To avoid spurious interrupt requests, the IA0S bit should be accessed only when the in- terrupt logic is disabled (i.e. after the DI instruc- tion). It is also necessary to clear any possible in- terrupt pending requests on channel A0 before en- abling this interrupt channel. A delay instruction (e.g. a NOP instruction) must be inserted between the reset of the interrupt pending bit and the IA0S write instruction. Other bits are described in the Interrupt section. x WDGEN x x x x x x x x x x x TLIS IA0S x

9.2 MULTIFUNCTION TIMER (MFT)

9.2.1 Introduction

put clock may be INTCLK/3 or an external source. pare at a fixed repetition rate. combined operating mode is available. some devices to control other on-chip peripherals. Figure 58. MFT Simplified Block Diagram

Figure 59. Detailed Block Diagram

ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d)

9.2.2 Functional Description

The MFT operating modes are selected by pro- gramming the Timer Control Register (TCR) and the Timer Mode Register (TMR).

9.2.2.1 Trigger Events

A trigger event may be generated by software (by setting either the CP0 or the CP1 bits in the T_FLAGR register) or by an external source which may be programmed to respond to the rising edge, the falling edge or both by programming bits A0- A1 and B0-B1 in the T_ICR register. This trigger event can be used to perform a capture or a load, depending on the Timer mode (configured using the bits in Table 24). An event on the TxINA input or setting the CP0 bit triggers a capture to, or a load from the REG0R register (except in Bicapture mode, see Section 9.2.2.11). An event on the TxINB input or setting the CP1 bit triggers a capture to, or a load from the REG1R register. In addition, in the special case of ”Load from REG0R and monitor on REG1R”, it is possible to use the TxINB input as a trigger for REG0R.”

9.2.2.2 One Shot Mode

When the counter generates an overflow (in up- count mode), or an underflow (in down-count mode), that is to say when an End Of Count condi- tion is reached, the counter stops and no counter reload occurs. The counter may only be restarted by an external trigger on TxINA or B or a by soft- ware trigger on CP0 only. One Shot Mode is en- tered by setting the CO bit in TMR.

9.2.2.3 Continuous Mode

Whenever the counter reaches an End Of Count condition, the counting sequence is automatically restarted and the counter is reloaded from REG0R (or from REG1R, when selected in Biload Mode). Continuous Mode is entered by resetting the C0 bit in TMR.

9.2.2.4 Triggered And Retriggered Modes

A triggered event may be generated by software (by setting either the CP0 or the CP1 bit in the T_FLAGR register), or by an external source which may be programmed to respond to the rising edge, the falling edge or both, by programming bits A0-A1 and B0-B1 in T_ICR. In One Shot and Triggered Mode, every trigger event arriving before an End Of Count, is masked. In One Shot and Retriggered Mode, every trigger received while the counter is running, automatical- ly reloads the counter from REG0R. Triggered/Re- triggered Mode is set by the REN bit in TMR. The TxINA input refers to REG0R and the TxINB input refers to REG1R. WARNING . If the Triggered Mode is selected when the counter is in Continuous Mode, every trigger is disabled, it is not therefore possible to synchronise the counting cycle by hardware or software.

9.2.2.5 Gated Mode

In this mode, counting takes place only when the external gate input is at a logic low level. The se- lection of TxINA or TxINB as the gate input is made by programming the IN0-IN3 bits in T_ICR.

9.2.2.6 Capture Mode

The REG0R and REG1R registers may be inde- pendently set in Capture Mode by setting RM0 or RM1 in TMR, so that a capture of the current count value can be performed either on REG0R or on REG1R, initiated by software (by setting CP0 or CP1 in the T_FLAGR register) or by an event on the external input pins. WARNING . Care should be taken when two soft- ware captures are to be performed on the same register. In this case, at least one instruction must be present between the first CP0/CP1 bit set and the subsequent CP0/CP1 bit reset instructions.

9.2.2.7 Up/Down Mode

The counter can count up or down depending on the state of the UDC bit (Up/Down Count) in TCR, or on the configuration of the external input pins, which have priority over UDC (see Input pin as- signment in T_ICR). The UDCS bit returns the counter up/down current status (see also the Up/ Down Autodiscrimination mode in the Input Pin Assignment Section).

9.2.2.8 Free Running Mode

9.2.2.9 Monitor Mode

9.2.2.10 Autoclear Mode

Mode, through the CCP0 and CCMP0 bits in TCR.

9.2.2.11 Bivalue Mode

Table 21. Bivalue Modes REG0R as a reload register (RM0 reset in TMR). of BM bit, the first reload is always from REG0R).

9.2.2.12 Parallel Mode

nected to the system clock line. are driven by the same frequency in parallel mode.

9.2.2.13 Autodiscriminator Mode

effect in this configuration. Figure 60. Parallel Mode Description

9.2.3 Input Pin Assignment

Table 22. Input Pin Function twice the prescaler clock period (INTCLK/3). the system clock (INTCLK) period.

ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d)

9.2.3.1 TxINA = I/O - TxINB = I/O

Input pins A and B are not used by the Timer. The counter clock is internally generated and the up/ down selection may be made only by software via the UDC (Software Up/Down) bit in the TCR regis- ter.

9.2.3.2 TxINA = I/O - TxINB = Trigger

The signal applied to input pin B acts as a trigger signal on REG1R register. The prescaler clock is internally generated and the up/down selection may be made only by software via the UDC (Soft- ware Up/Down) bit in the TCR register.

9.2.3.3 TxINA = Gate - TxINB = I/O

The signal applied to input pin A acts as a gate sig- nal for the internal clock (i.e. the counter runs only when the gate signal is at a low level). The counter clock is internally generated and the up/down con- trol may be made only by software via the UDC (Software Up/Down) bit in the TCR register.

9.2.3.4 TxINA = Gate - TxINB = Trigger

Both input pins A and B are connected to the timer, with the resulting effect of combining the actions relating to the previously described configuration s. 9.2.3.5 TxINA = I/O - TxINB = Ext. Clock The signal applied to input pin B is used as the ex- ternal clock for the prescaler. The up/down selec- tion may be made only by software via the UDC (Software Up/Down) bit in the TCR register.

9.2.3.6 TxINA = Trigger - TxINB = I/O

The signal applied to input pin A acts as a trigger for REG0R, initiating the action for which the reg- ister was programmed (i.e. a reload or capture). The prescaler clock is internally generated and the up/down selection may be made only by software via the UDC (Software Up/Down) bit in the TCR register. (*) The timer is in One shot mode and REGOR in Reload mode 9.2.3.7 TxINA = Gate - TxINB = Ext. Clock The signal applied to input pin B, gated by the sig- nal applied to input pin A, acts as external clock for the prescaler. The up/down control may be made only by software action through the UDC bit in the TCR register.

9.2.3.8 TxINA = Trigger - TxINB = Trigger

The signal applied to input pin A (or B) acts as trig- ger signal for REG0R (or REG1R), initiating the action for which the register has been pro- grammed. The counter clock is internally generat- ed and the up/down selection may be made only by software via the UDC (Software Up/Down) bit in the TCR register.

ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d)

9.2.3.9 TxINA = Clock Up - TxINB = Clock Down

The edge received on input pin A (or B) performs a one step up (or down) count, so that the counter clock and the up/down control are external. Setting the UDC bit in the TCR register has no effect in this configuration, and input pin B has priority on input pin A.

9.2.3.10 TxINA = Up/Down - TxINB = Ext Clock

An High (or Low) level applied to input pin A sets the counter in the up (or down) count mode, while the signal applied to input pin B is used as clock for the prescaler. Setting the UDC bit in the TCR reg- ister has no effect in this configuration.

9.2.3.11 TxINA = Trigger Up - TxINB = Trigger

Up/down control is performed through both input pins A and B. A edge on input pin A sets the up count mode, while a edge on input pin B (which has priority on input pin A) sets the down count mode. The counter clock is internally generated, and setting the UDC bit in the TCR register has no effect in this configuration.

9.2.3.12 TxINA = Up/Down - TxINB = I/O

An High (or Low) level of the signal applied on in- put pin A sets the counter in the up (or down) count mode. The counter clock is internally generated. Setting the UDC bit in the TCR register has no ef- fect in this configuration.

ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d)

9.2.3.13 Autodiscrimination Mode

The phase between two pulses (respectively on in- put pin B and input pin A) generates a one step up (or down) count, so that the up/down control and the counter clock are both external. Thus, if the ris- ing edge of TxINB arrives when TxINA is at a low level, the timer is incremented (no action if the ris- ing edge of TxINB arrives when TxINA is at a high level). If the falling edge of TxINB arrives when TxINA is at a low level, the timer is decremented (no action if the falling edge of TxINB arrives when TxINA is at a high level). Setting the UDC bit in the TCR register has no ef- fect in this configuration. 9.2.3.14 TxINA = Trigger - TxINB = Ext. Clock The signal applied to input pin A acts as a trigger signal on REG0R, initiating the action for which the register was programmed (i.e. a reload or cap- ture), while the signal applied to input pin B is used as the clock for the prescaler. (*) The timer is in One shot mode and REG0R in reload mode 9.2.3.15 TxINA = Ext. Clock - TxINB = Trigger The signal applied to input pin B acts as a trigger, performing a capture on REG1R, while the signal applied to input pin A is used as the clock for the prescaler.

9.2.3.16 TxINA = Trigger - TxINB = Gate

The signal applied to input pin A acts as a trigger signal on REG0R, initiating the action for which the register was programmed (i.e. a reload or cap- ture), while the signal applied to input pin B acts as a gate signal for the internal clock (i.e. the counter runs only when the gate signal is at a low level).

ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d)

9.2.4 Output Pin Assignment

Two external outputs are available when pro- grammed as Alternate Function Outputs of the I/O pins. Two registers Output A Control Register (OACR) and Output B Control Register (OBCR) define the driver for the outputs and the actions to be per- formed. Each of the two output pins can be driven from any of the three possible sources: – Compare Register 0 event logic – Compare Register 1 event logic – Overflow/Underflow event logic. Each of these three sources can cause one of the following four actions on any of the two outputs: – Nop – Set – Reset – Toggle Furthermore an On Chip Event signal can be driv- en by two of the three sources: the Over/Under- flow event and Compare 0 event by programming the CEV bit of the OACR register and the OEV bit of OBCR register respectively. This signal can be used internally to synchronise another on-chip pe- ripheral. Output Waveforms Depending on the programming of OACR and OB- CR, the following example waveforms can be gen- erated on TxOUTA and TxOUTB pins. For a configuration where TxOUTA is driven by the Over/Underflow (OUF) and the Compare 0 event (CM0), and TxOUTB is driven by the Over/Under- flow and Compare 1 event (CM1): OACR is programmed with TxOUTA preset to “0”, OUF sets TxOUTA, CM0 resets TxOUTA and CM1 does not affect the output. OBCR is programmed with TxOUTB preset to “0”, OUF sets TxOUTB, CM1 resets TxOUTB while CM0 does not affect the output. For a configuration where TxOUTA is driven by the Over/Underflow, by Compare 0 and by Compare 1; TxOUTB is driven by both Compare 0 and Com- pare 1. OACR is programmed with TxOUTA pre- set to “0”. OUF toggles Output 0, as do CM0 and CM1. OBCR is programmed with TxOUTB preset to “1”. OUF does not affect the output; CM0 resets TxOUTB and CM1 sets it. OACR = [101100X0] OBCR = [111000X0] T0OUTA T0OUTB OUF COMP1 OUF COMP1 OUF COMP0 OUF COMP0 OACR = [010101X0] OBCR = [100011X1] T0OUTA T0OUTB COMP1 COMP1 OUF OUF COMP0 COMP0 COMP0 COMP0 COMP1 COMP1

ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) For a configuration where TxOUTA is driven by the Over/Underflow and by Compare 0, and TxOUTB is driven by the Over/Underflow and by Compare 1. OACR is programmed with TxOUTA preset to “0”. OUF sets TxOUTA while CM0 resets it, and CM1 has no effect. OBCR is programmed with Tx- OUTB preset to “1”. OUF toggles TxOUTB, CM1 sets it and CM0 has no effect. For a configuration where TxOUTA is driven by the Over/Underflow and by Compare 0, and TxOUTB is driven by Compare 0 and 1. OACR is pro- grammed with TxOUTA preset to “0”. OUF sets TxOUTA, CM0 resets it and CM1 has no effect. OBCR is programmed with TxOUTB preset to “0”. OUF has no effect, CM0 sets TxOUTB and CM1 toggles it. Output Waveform Samples In Biload Mode TxOUTA is programmed to monitor the two time intervals, t1 and t2, of the Biload Mode, while Tx- OUTB is independent of the Over/Underflow and is driven by the different values of Compare 0 and Compare 1. OACR is programmed with TxOUTA preset to “0”. OUF toggles the output and CM0 and CM1 do not affect TxOUTA. OBCR is programmed with TxOUTB preset to “0”. OUF has no effect, while CM1 resets TxOUTB and CM0 sets it. Depending on the CM1/CM0 values, three differ- ent sample waveforms have been drawn based on the above mentioned configuration of OBCR. In the last case, with a different programmed value of OBCR, only Compare 0 drives TxOUTB, toggling the output. Note (*) Depending on the CMP1R/CMP0R values OACR = [101100X0] OBCR = [000111X0] T0OUTA T0OUTB OUF OUFCOMP0 COMP0 COMP0 COMP0 COMP1 COMP1

9.2.5 Interrupt and DMA

9.2.5.1 Timer Interrupt

Table 23. Timer Interrupt Structure MR.7) which masks all interrupts.

9.2.5.2 Timer DMA

mask bits in the IDMR register.

9.2.5.3 DMA Pointers

Figure 61. Pointer Mapping for Transfers

Figure 62. Pointer Mapping for Register to

9.2.5.4 DMA Transaction Priorities

gardless of the other Timer internal sources, i.e. curs between the two byte transfers.

9.2.5.5 DMA Swap Mode

condition occurs, the block transfer is completed. related to the correct channel).

ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d)

9.2.5.6 DMA End Of Block Interrupt Routine

An interrupt request is generated after each block transfer (EOB) and its priority is the same as that assigned in the usual interrupt request, for the two channels. As a consequence, they will be serviced only when no DMA request occurs, and will be subject to a possible OUF Interrupt request, which has higher priority. The following is a typical EOB procedure (with swap mode enabled): – Test Toggle bit and Jump. – Reload Pointers (odd or even depending on tog- gle bit status). – Reset EOB bit: this bit must be reset only after the old pair of pointers has been restored, so that, if a new EOB condition occurs, the next pair of pointers is ready for swapping. – Verify the software protection condition (see Section 9.2.5.7). – Read the corresponding Overrun bit: this con- firms that no DMA request has been lost in the meantime. – Reset the corresponding pending bit. – Reenable DMA with the corresponding DMA mask bit(must always be done after resetting the pending bit) – Return. WARNING : The EOB bits are read/writeonly for test purposes. Writing a logical “1” by software (when the SWEN bit is set) will cause a spurious interrupt request. These bits are normally only re- set by software.

9.2.5.7 DMA Software Protection

A second EOB condition may occur before the first EOB routine is completed, this would cause a not yet updated pointer pair to be addressed, with con- sequent overwriting of memory. To prevent these errors, a protection mechanism is provided, such that the attempted setting of the EOB bit before it has been reset by software will cause the DMA mask on that channel to be reset (DMA disabled), thus blocking any further DMA operation. As shown above, this mask bit should always be checked in each EOB routine, to ensure that all DMA transfers are properly served.

9.2.6 Register Description

Note:In the register description on the following pages, register and page numbers are given using the example of Timer 0. On devices with more than one timer, refer to the device register map for the adresses and page numbers.

ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) CAPTURE LOAD 0 HIGH REGISTER (REG0HR) R240 - Read/Write Register Page: 10 Reset value: undefined This register is used to capture values from the Up/Down counter or load preset values (MSB). CAPTURE LOAD 0 LOW REGISTER (REG0LR) R241 - Read/Write Register Page: 10 Reset value: undefined This register is used to capture values from the Up/Down counter or load preset values (LSB). CAPTURE LOAD 1 HIGH REGISTER (REG1HR) R242 - Read/Write Register Page: 10 Reset value: undefined This register is used to capture values from the Up/Down counter or load preset values (MSB). CAPTURE LOAD 1 LOW REGISTER (REG1LR) R243 - Read/Write Register Page: 10 Reset value: undefined This register is used to capture values from the Up/Down counter or load preset values (LSB). COMPARE 0 HIGH REGISTER (CMP0HR) R244 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) This register is used to store the MSB of the 16-bit value to be compared to the Up/Down counter content. COMPARE 0 LOW REGISTER (CMP0LR) R245 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) This register is used to store the LSB of the 16-bit value to be compared to the Up/Down counter content. COMPARE 1 HIGH REGISTER (CMP1HR) R246 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) This register is used to store the MSB of the 16-bit value to be compared to the Up/Down counter content. COMPARE 1 LOW REGISTER (CMP1LR) R247 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) This register is used to store the LSB of the 16-bit value to be compared to the Up/Down counter content. R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) TIMER CONTROL REGISTER (TCR) R248 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) Bit 7 =CEN :Counter enable. This bit is ANDed with the Global Counter Enable bit (GCEN) in the CICR register (R230). The GCEN bit is set after the Reset cycle. 0: Stop the counter and prescaler 1: Start the counter and prescaler (without reload). Note: Even if CEN=0, capture and loading will take place on a trigger event. Bit 6 =CCP0 : Clear on capture. 0: No effect 1: Clear the counter and reload the prescaler on a REG0R or REG1R capture event Bit 5 =CCMP0 : Clear on Compare. 0: No effect 1: Clear the counter and reload the prescaler on a CMP0R compare event Bit 4 =CCL :Counter clear. This bit is reset by hardware after being set by software (this bit always returns “0” when read). 0: No effect 1: Clear the counter without generating an inter- rupt request Bit 3 =UDC : Up/Down software selection. If the direction of the counter is not fixed by hard- ware (TxINA and/or TxINB pins, see par. 10.3) it can be controlled by software using the UDC bit. 0: Down counting 1: Up counting Bit 2 =UDCS :Up/Down count status. This bit is read only and indicates the direction of the counter. 0: Down counting 1: Up counting Bit 1 =OF0 :OVF/UNF state. This bit is read only. 0: No overflow or underflow occurred 1: Overflow or underflow occurred during a Cap- ture on Register 0 Bit 0 =CS Counter Status. This bit is read only and indicates the status of the counter. 0: Counter halted 1: Counter running CEN CCP CCMP

0 CCL UDC UDC

Bit 7 =OE1 :Output 1 enable. 1: Enable the Output 0 (TxOUTA pin). to select the timer operating mode (see Table 24). Table 24. Timer Operating Modes Bit 2 =ECK Timer clock control. Bit 0 =CO :Continous/One shot mode.

ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) EXTERNAL INPUT CONTROL REGISTER (T_ICR) R250 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) Bit 7:4 =IN[3:0]:Input pin function. These bits are set and cleared by software. Bit 3:2 =A[0:1]:TxINA Pin event. These bits are set and cleared by software. Bit 1:0 =B[0:1]:TxINB Pin event. These bits are set and cleared by software. PRESCALER REGISTER (PRSR) R251 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) This register holds the preset value for the 8-bit prescaler. The PRSR content may be modified at any time, but it will be loaded into the prescaler at the following prescaler underflow, or as a conse- quence of a counter reload (either by software or upon external request). Following a RESET condition, the prescaler is au- tomatically loaded with 00h, so that the prescaler divides by 1 and the maximum counter clock is generated (OSCIN frequency divided by 6 when MODER.5 = DIV2 bit is set). The binary value programmed in the PRSR regis- ter is equal to the divider value minus one. For ex- ample, loading PRSR with 24 causes the prescal- er to divide by 25. IN3 IN2 IN1 IN0 A0 A1 B0 B1 IN[3:0] bits TxINA Pin Function TxINB Input Pin Function 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 not used not used Gate Gate not used Trigger Gate Trigger Clock Up Up/Down Trigger Up Up/Down Autodiscr. Trigger Ext. Clock Trigger not used Trigger not used Trigger Ext. Clock not used Ext. Clock Trigger Clock Down Ext. Clock Trigger Down not used Autodiscr. Ext. Clock Trigger Gate A0 A1 TxINA Pin Event No operation Falling edge sensitive Rising edge sensitive Rising and falling edges B0 B1 TxINB Pin Event No operation Falling edge sensitive Rising edge sensitive Rising and falling edges P7 P6 P5 P4 P3 P2 P1 P0

ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) OUTPUT A CONTROL REGISTER (OACR) R252 - Read/Write Register Page: 10 Reset value: 0000 0000 Note: Whenever more than one event occurs si- multaneously, the action taken will be the result of ANDing the event bits xxE1-xxE0. Bit 7:6 =C0E[0:1]: COMP0 event bits. These bits are set and cleared by software. Bit 5:4 =C1E[0:1]:COMP1 event bits. These bits are set and cleared by software. Bit 3:2 =OUE[0:1]:OVF/UNF event bits. These bits are set and cleared by software. Note:Whenever more than one event occurs si- multaneously, the action taken will be the result of ANDing the event xxE1-xxE0 bits. Bit 1 =CEV : On-Chip event on CMP0R. This bit is set and cleared by software. 0: No action 1: A successful compare on CMP0R activates the on-chip event signal (a single pulse is generat- ed) Bit 0 =OP : TxOUTA preset value. This bit is set and cleared by software and by hard- ware. The value of this bit is the preset value of the TxOUTA pin. Reading this bit returns the current state of the TxOUTA pin (useful when it is selected in toggle mode). C0E0 C0E1 C1E0 C1E1 OUE0 OUE1 CEV 0P C0E0 C0E1 Action on TxOUTA pin ona suc- cessful compare of the CMP0R register 0 0 Set 0 1 Toggle 1 0 Reset 1 1 NOP C1E0 C1E1 Action on TxOUTA pin on a suc- cessful compare of the CMP1R reg- ister 0 0 Set 0 1 Toggle 1 0 Reset 1 1 NOP OUE0 OUE1 Action on TxOUTA pin on an Over- flow or Underflow on the U/D coun- ter 0 0 Set 0 1 Toggle 1 0 Reset 1 1 NOP

ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) OUTPUT B CONTROL REGISTER (OBCR) R253 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) Note: Whenever more than one event occurs si- multaneously, the action taken will be the result of ANDing the event bits xxE1-xxE0. Bit 7:6 =C0E[0:1]: COMP0 event bits. These bits are set and cleared by software. Bit 5:4 =C1E[0:1]:COMP1 event bits. These bits are set and cleared by software. Bit 3:2 =OUE[0:1]:OVF/UNF event bits. These bits are set and cleared by software. Bit 1 =OEV :On-Chip event on OVF/UNF. This bit is set and cleared by software. 0: No action 1: An underflow/overflow activates the on-chip event signal (a single pulse is generated) Bit 0 =OP :TxOUTB preset value. This bit is set and cleared by software and by hard- ware. The value of this bit is the preset value of the TxOUTB pin. Reading this bit returns the current state of the TxOUTB pin (useful when it is selected in toggle mode). C0E0 C0E1 C1E0 C1E1 OUE0 OUE1 OEV 0P C0E0 C0E1 Action on TxOUTB pin ona suc- cessful compare of the CMP0R register 0 0 Set 0 1 Toggle 1 0 Reset 1 1 NOP C1E0 C1E1 Action on TxOUTB pin on a suc- cessful compare of the CMP1R reg- ister 0 0 Set 0 1 Toggle 1 0 Reset 1 1 NOP OUE0 OUE1 Action on TxOUTB pin on an Over- flow or Underflow on the U/D coun- ter 0 0 Set 0 1 Toggle 1 0 Reset 1 1 NOP

ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) FLAG REGISTER (T_FLAGR) R254 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) Bit 7 =CP0 :Capture 0 flag. This bit is set by hardware after a capture on REG0R register. An interrupt is generated de- pending on the value of the GTIEN, CP0I bits in the IDMR register and the A0 bit in the T_FLAGR register. The CP0 bit must be cleared by software. Setting by software acts as a software load/cap- ture to/from the REG0R register. 0: No Capture 0 event 1: Capture 0 event occurred Bit 6 =CP1 : Capture 1 flag. This bit is set by hardware after a capture on REG1R register. An interrupt is generated de- pending on the value of the GTIEN, CP0I bits in the IDMR register and the A0 bit in the T_FLAGR register. The CP1 bit must be cleared by software. Setting by software acts as a capture event on the REG1R register, except when in Bicapture mode. 0: No Capture 1 event 1: Capture 1 event occurred Bit 5 =CM0 : Compare 0 flag. This bit is set by hardware after a successful com- pare on the CMP0R register. An interrupt is gener- ated if the GTIEN and CM0I bits in the IDMR reg- ister are set. The CM0 bit is cleared by software. 0: No Compare 0 event 1: Compare 0 event occurred Bit 4 =CM1 : Compare 1 flag. This bit is set after a successful compare on CMP1R register. An interrupt is generated if the GTIEN and CM1I bits in the IDMR register are set. The CM1 bit is cleared by software. 0: No Compare 1 event 1: Compare 1 event occurred Bit 3 =OUF :Overflow/Underflow. This bit is set by hardware after a counter Over/ Underflow condition. An interrupt is generated if GTIEN and OUI=1 in the IDMR register. The OUF bit is cleared by software. 0: No counter overflow/underflow 1: Counter overflow/underflow Bit 2 =OCP0 : Overrun on Capture 0. This bit is set by hardware when more than one INT/DMA requests occur before the CP0 flag is cleared by software or whenever a capture is sim- ulated by setting the CP0 flag by software. The OCP0 flag is cleared by software. 0: No capture 0 overrun 1: Capture 0 overrun Bit 1 =OCM0 : Overrun on compare 0. This bit is set by hardware when more than one INT/DMA requests occur before the CM0 flag is cleared by software.The OCM0 flag is cleared by software. 0: No compare 0 overrun 1: Compare 0 overrun Bit 0 =A0 : Capture interrupt function. This bit is set and cleared by software. 0: Configure the capture interrupt as an OR func- tion of REG0R/REG1R captures 1: Configure the capture interrupt as an AND func- tion of REG0R/REG1R captures CP0 CP1 CM0 CM1 OUF OCP OCM 0 A0

ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) INTERRUPT/DMA MASK REGISTER (IDMR) R255 - Read/Write Register Page: 10 Reset value: 0000 0000 (00h) Bit 7 =GTIEN :Global timer interrupt enable. This bit is set and cleared by software. 0: Disable all Timer interrupts 1: Enable all timer Timer Interrupts from enabled sources Bit 6 =CP0D : Capture 0 DMA mask. This bit is set by software to enable a Capt0 DMA transfer and cleared by hardware at the end of the block transfer. 0: Disable capture on REG0R DMA 1: Enable capture on REG0R DMA Bit 5 =CP0I: Capture 0 interrupt mask. 0: Disable capture on REG0R interrupt 1: Enable capture on REG0R interrupt (or Capt0 DMA End of Block interrupt if CP0D=1) Bit 4 =CP1I: Capture 1 interrupt mask. This bit is set and cleared by software. 0: Disable capture on REG1R interrupt 1: Enable capture on REG1R interrupt Bit 3 =CM0D : Compare 0 DMA mask. This bit is set by software to enable a Comp0 DMA transfer and cleared by hardware at the end of the block transfer. 0: Disable compare on CMP0R DMA 1: Enable compare on CMP0R DMA Bit 2 =CM0I : Compare 0 Interrupt mask. This bit is set and cleared by software. 0: Disable compare on CMP0R interrupt 1: Enable compare on CMP0R interrupt (or Comp0 DMA End of Block interrupt if CM0D=1) Bit 1 =CM1I :Compare 1 Interrupt mask. This bit is set and cleared by software. 0: Disable compare on CMP1R interrupt 1: Enable compare on CMP1R interrupt Bit 0 =OUI: Overflow/Underflow interrupt mask. This bit is set and cleared by software. 0: Disable Overflow/Underflow interrupt 1: Enable Overflow/Underflow interrupt DMA COUNTER POINTER REGISTER (DCPR) R240 - Read/Write Register Page: 9 Reset value: undefined Bit 7:2 =DCP[7:2]: MSBs of DMA counter register address. These are the most significant bits of the DMA counter register address programmable by soft- ware. The DCP2 bit may also be toggled by hard- ware if the Timer DMA section for the Compare 0 channel is configured in Swap mode. Bit 1 =DMA-SRCE : DMA source selection. This bit is set and cleared by hardware. 0: DMA source is a Capture on REG0R register 1: DMA destination is a Compare on CMP0R reg- ister Bit 0 =REG/MEM :DMA area selection. This bit is set and cleared by software. It selects the source and destination of the DMA area 0: DMA from/to memory 1: DMA from/to Register File GT- IEN CP0D CP0I CP1I CM0 D CM0I CM1I OUI DCP7 DCP6 DCP5 DCP4 DCP3 DCP2 DMA SRCE REG/ MEM

ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) DMA ADDRESS POINTER REGISTER (DAPR) R241 - Read/Write Register Page: 9 Reset value: undefined Bit 7:2 =DAP[7:2]:MSB of DMA address register location. These are the most significant bits of the DMA ad- dress register location programmable by software. The DAP2 bit may also be toggled by hardware if the Timer DMA section for the Compare 0 channel is configured in Swap mode. Note: During a DMA transfer with the Register File, the DAPR is not used; however, in Swap mode, DAPR(2) is used to point to the correct ta- ble. Bit 1 =DMA-SRCE : DMA source selection. This bit is fixed by hardware. 0: DMA source is a Capture on REG0R register 1: DMA destination is a Compare on the CMP0R register Bit 0 =PRG/DAT: DMA memory selection. This bit is set and cleared by software. It is only meaningful if DCPR.REG/MEM=0. 0: The ISR register is used to extend the address of data transferred by DMA (see MMU chapter). 1: The DMASR register is used to extend the ad- dress of data transferred by DMA (see MMU chapter). INTERRUPT VECTOR REGISTER (T_IVR) R242 - Read/Write Register Page: 9 Reset value:xxxx xxx0 This register is used as a vector, pointing to the 16-bit interrupt vectors in memory which contain the starting addresses of the three interrupt sub- routines managed by each timer. Only one Interrupt Vector Register is available for each timer, and it is able to manage three interrupt groups, because the 3 least significant bits are fixed by hardware depending on the group which generated the interrupt request. In order to determine which request generated the interrupt within a group, the T_FLAGR register can be used to check the relevant interrupt source. Bit 7:3 =V[4:0]: MSB of the vector address. These bits are user programmabl e and contain the five most significant bits of the Timer interrupt vec- tor addresses in memory. In any case, an 8-bit ad- dress can be used to indicate the Timer interrupt vector locations, because they are within the first 256 memory locations (see Interrupt and DMA chapters). Bit 2:1 =W[1:0]: Vector address bits. These bits are equivalent to bit 1 and bit 2 of the Timer interrupt vector addresses in memory. They are fixed by hardware, depending on the group of sources which generated the interrupt request as follows:. Bit 0 = This bit is forced by hardware to 0. DAP DAP

6 DAP5 DAP4 DAP3 DAP2 DMA

/DAT REG/MEM PRG/DAT DMA Source/Destination ISR register used to address memory DMASR register used to address memory Register file Register file V4 V3 V2 V1 V0 W1 W0 0 W1 W0 Interrupt Source Overflow/Underflow even interrupt Not available Capture event interrupt Compare event interrupt

ST90158 - MULTIFUNCTION TIMER (MFT) MULTIFUNCTION TIMER (Cont’d) INTERRUPT/DMA CONTROL REGISTER (IDCR) R243 - Read/Write Register Page: 9 Reset value: 1100 0111 (C7h) Bit 7 =CPE :Capture 0 EOB. This bit is set by hardware when the End Of Block condition is reached during a Capture 0 DMA op- eration with the Swap mode enabled. When Swap mode is disabled (SWEN bit = “0”), the CPE bit is forced to 1 by hardware. 0: No end of block condition 1: Capture 0 End of block Bit 6 =CME : Compare 0 EOB. This bit is set by hardware when the End Of Block condition is reached during a Compare 0 DMA op- eration with the Swap mode enabled. When the Swap mode is disabled (SWEN bit = “0”), the CME bit is forced to 1 by hardware. 0: No end of block condition 1: Compare 0 End of block Bit 5 =DCTS : DMA capture transfer source. This bit is set and cleared by software. It selects the source of the DMA operation related to the channel associated with the Capture 0. Note:The I/O port source is available only on spe- cific devices. 0: REG0R register 1: I/O port. Bit 4 =DCTD : DMA compare transfer destination. This bit is set and cleared by software. It selects the destination of the DMA operation related to the channel associated with Compare 0. Note:The I/O port destination is available only on specific devices. 0: CMP0R register 1: I/O port Bit 3 =SWEN : Swap function enable. This bit is set and cleared by software. 0: Disable Swap mode 1: Enable Swap mode for both DMA channels. Bit 2:0 =PL[2:0]:Interrupt/DMA priority level. With these three bits it is possible to select the In- terrupt and DMA priority level of each timer, as one of eight levels (see Interrupt/DMA chapter). I/O CONNECTION REGISTER (IOCR) R248 - Read/Write Register Page: 9 Reset value: 1111 1100 (FCh) Bit 7:2 = not used. Bit 1 =SC1 : Select connection odd. This bit is set and cleared by software. It selects if the TxOUTA and TxINA pins for Timer 1 and Timer 3 are connected on-chip or not. 0: T1OUTA / T1INA and T3OUTA/ T3INA uncon- nected 1: T1OUTA connected internally to T1INA and T3OUTA connected internally to T3INA Bit 0 =SC0 :Select connection even. This bit is set and cleared by software. It selects if the TxOUTA and TxINA pins for Timer 0 and Timer 2 are connected on-chip or not. 0: T0OUTA / T0INA and T2OUTA/ T2INA uncon- nected 1: T0OUTA connected internally to T0INA and T2OUTA connected internally to T2INA Note:Timer 1 and 2 are available only on some devices. Refer to the device block diagram and register map. CPE CME DCTS DCT D SWE N PL2 PL1 PL0 SC1 SC0

9.3 STANDARD TIMER (STIM)

9.3.1 Introduction

as Alternate Functions of an I/O port bit. or Pulse Width Modulated signal. clock connected to the STIN pin. one of the external interrupt channels. Counter Underflow, whenever 00h is reached. Figure 63. Standard Timer Block Diagram Note 1:Pin not present on all ST9 devices.

ST90158 - STANDARD TIMER (STIM) STANDARD TIMER (Cont’d)

9.3.2 Functional Description

9.3.2.1 Timer/Counter control

Start-stop Count.The ST-SP bit (STC.7) is used in order to start and stop counting. An instruction which sets this bit will cause the Standard Timer to start counting at the beginning of the next instruc- tion. Resetting this bit will stop the counter. If the counter is stopped and restarted, counting will resume from the value held at the stop condi- tion, unless a new constant has been entered in the Standard Timer registers during the stop peri- od. In this case, the new constant will be loaded as soon as counting is restarted. A new constant can be written in STH, STL, STP registers while the counter is running. The new value of the STH and STL registers will be loaded at the next End of Count condition, while the new value of the STP register will be loaded immedi- ately. WARNING: Inorder to prevent incorrect counting of the StandardTimer,theprescaler(STP) andcounter (STL, STH) registers must be initialised before the starting of the timer. If this is not done, counting will start with the reset values (STH=FFh, STL=FFh, STP=FFh). Single/Continuous Mode. The S-C bit (STC.6) selects between the Single or Continuous mode. SINGLE MODE: at the End of Count, the Standard Timer stops, reloads the constant and resets the Start/Stop bit (the user programmer can inspect the timer current status by reading this bit). Setting the Start/Stop bit will restart the counter. CONTINUOUS MODE: At the End of the Count, the counter automatically reloads the constant and re- starts.Itisonly stoppedbyresettingtheStart/Stop bit. The S-C bit can be written either with the timer stopped or running. It is possible to toggle the S-C bit and start the Standard Timer with the same in- struction.

9.3.2.2 Standard Timer Input Modes (ST9

devices with Standard Timer Input STIN) Bits INMD2, INMD1 and INEN are used to select the input modes. The Input Enable (INEN) bit ena- bles the input mode selected by the INMD2 and INMD1 bits. If the input is disabled (INEN=”0”), the values of INMD2 and INMD1 are not taken into ac- count. In this case, this unit acts as a 16-bit timer (plus prescaler) directly driven by INTCLK/4 and transitions on the input pin have no effect. Event Counter Mode(INMD1 = ”0”, INMD2 = ”0”) The Standard Timer is driven by the signal applied to the input pin (STIN) which acts as an external clock. The unit works therefore as an event coun- ter. The event is a high to low transition on STIN. Spacing between trailing edges should be at least the period of INTCLK multiplied by 8 (i.e. the max- imum Standard Timer input frequency is 2.5 MHz with INTCLK = 20MHz). Gated Input Mode(INMD1 = ”0”, INMD2 = “1”) The Timer uses the internal clock (INTCLK divided by 4) and starts and stops the Timer according to the state of STIN pin. When the status of the STIN is High the Standard Timer count operation pro- ceeds, and when Low, counting is stopped. Triggerable Input Mode(INMD1= “1”,INMD2=“0”) The Standard Timer is started by: a) setting the Start-Stop bit, AND b) a High to Low (low trigger) transition on STIN. In order to stop the Standard Timer in this mode, it is only necessary to reset the Start-Stop bit. Retriggerable Input Mode(INMD1 = “1”, INMD2 = “1”) In this mode, when the Standard Timer is running (with internal clock), a High to Low transition on STIN causes the counting to start from the last constant loaded into the STL/STH and STP regis- ters. When the Standard Timer is stopped (ST-SP bit equal to zero), a High to Low transition on STIN has no effect.

9.3.2.3 Time Base Generator (ST9 devices

without Standard Timer Input STIN) For devices where STIN is replaced by a connec- tion to CLOCK2, the condition (INMD1 = “0”, INMD2 = “0”) will allow the Standard Timer to gen- erate a stable time base independent from the PLL programming.

ST90158 - STANDARD TIMER (STIM) STANDARD TIMER (Cont’d)

9.3.2.4 Standard Timer Output Modes

OUTPUT modes are selected using 2 bits of the STC register: OUTMD1 and OUTMD2. No Output Mode (OUTMD1 = “0”, OUTMD2 = “0”) The output is disabled and the corresponding pin is set high, in order to allow other alternate func- tions to use the I/O pin. Square Wave Output Mode (OUTMD1 = “0”, OUTMD2 = “1”) The Standard Timer toggles the state of the STOUT pin on every End Of Count condition. With INTCLK = 12MHz, this allows generation of a square wave with a period ranging from 666ns to 11.18 seconds. PWM Output Mode (OUTMD1 = “1”) The value of the OUTMD2 bit is transferred to the STOUT output pin at the End Of Count. This al- lows the user to generate PWM signals, by modi- fying the status of OUTMD2 between End of Count events, based on software counters decremented on the Standard Timer interrupt.

9.3.3 Interrupt Selection

The Standard Timer may generate an interrupt re- quest at every End of Count. Bit 2 of the STC register (INTS) selects the inter- rupt source between the Standard Timer interrupt and the external interrupt pin. Thus the Standard Timer Interrupt uses the interrupt channel and takes the priority and vector of the external inter- rupt channel. If INTS is set to “1”, the Standard Timer interrupt is disabled; otherwise, an interrupt request is gener- ated at every End of Count. Note: When enabling or disabling the Standard Timer Interrupt (writing INTS in the STC register) an edge may be generated on the interrupt chan- nel, causing an unwanted interrupt. To avoid this spurious interrupt request, the INTS bit should be accessed only when the interrupt log- ic is disabled (i.e. after the DI instruction). It is also necessary to clear any possible interrupt pending requests on the corresponding external interrupt channel before enabling it. A delay instruction (i.e. a NOP instruction) must be inserted between the reset of the interrupt pending bit and the INTS write instruction.

9.3.4 Register Mapping

Depending on the ST9 device there may be up to 4 Standard Timers (refer to the block diagram in the first section of the data sheet). Each Standard Timer has 4 registers mapped into Page 11 in Group F of the Register File In the register description on the following page, register addresses refer to STIM0 only. Note:The four standard timers are not implement- ed on all ST9 devices. Refer to the block diagram of the device for the number of timers. STD Timer Register Register Address STIM0 STH0 R240 (F0h) STL0 R241 (F1h) STP0 R242 (F2h) STC0 R243 (F3h) STIM1 STH1 R244 (F4h) STL1 R245 (F5h) STP1 R246 (F6h) STC1 R247 (F7h) STIM2 STH2 R248 (F8h) STL2 R249 (F9h) STP2 R250 (FAh) STC2 R251 (FBh) STIM3 STH3 R252 (FCh) STL3 R253 (FDh) STP3 R254 (FEh) STC3 R255 (FFh)

ST90158 - STANDARD TIMER (STIM) STANDARD TIMER (Cont’d)

9.3.5 Register Description

COUNTER HIGH BYTE REGISTER (STH) R240 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh) Bit 7:0 =ST.[15:8]: Counter High-Byte. COUNTER LOW BYTE REGISTER (STL) R241 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh) Bit 7:0 =ST.[7:0]: Counter Low Byte. Writing to the STH and STL registers allows the user to enter the Standard Timer constant, while reading it provides the counter’s current value. Thus it is possible to read the counter on-the-fly. STANDARD TIMER PRESCALER REGISTER (STP) R242 - Read/Write Register Page: 11 Reset value: 1111 1111 (FFh) Bit 7:0 =STP.[7:0]: Prescaler. The Prescaler value for the Standard Timer is pro- grammed into this register. When reading the STP register, the returned value corresponds to the programmed data instead of the current data. 00h: No prescaler 01h: Divide by 2 FFh: Divide by 256 STANDARD TIMER CONTROL REGISTER (STC) R243 - Read/Write Register Page: 11 Reset value: 0001 0100 (14h) Bit 7 =ST-SP : Start-Stop Bit. This bit is set and cleared by software. 0: Stop counting 1: Start counting Bit 6 =S-C:Single-Continuous Mode Select. This bit is set and cleared by software. 0: Continuous Mode 1: Single Mode Bit 5:4 =INMD[1:2]:Input Mode Selection. These bits select the Input functions as shown in Section 9.3.2.2, when enabled by INEN. Bit 3 =INEN :Input Enable. This bit is set and cleared by software. If neither the STIN pin nor the CLOCK2 line are present, INEN must be 0. 0: Input section disabled 1: Input section enabled Bit 2 =INTS: Interrupt Selection. 0: Standard Timer interrupt enabled 1: Standard Timer interrupt is disabled and the ex- ternal interrupt pin is enabled. Bit 1:0 =OUTMD[1:2] : Output Mode Selection. These bits select the output functions as described in Section 9.3.2.4. ST- SP S-C INMD INMD

2 INEN INTS OUTM

00 Event Counter mode

01 Gated input mode

10 Triggerable mode

11 Retriggerable mode

00 No output mode

01 Square wave output mode

9.4 SERIAL PERIPHERAL INTERFACE (SPI)

9.4.1 Introduction

bus and IM-bus communication standards. selects or IM-bus address identifier signals.

9.4.2 Device-Specific Options

Configuration Chapter for the device pin-out. Figure 64. Block Diagram

9.4.3 Functional Description

synchronized with the same clock signal, SCK. empty” and “Rx full” status bits. ble to the CPU during a subsequent read cycle. Figure 65 below shows a typical SPI network. Figure 65. A Typical SPI Network

9.4.3.1 Input Signal Description

9.4.3.2 Output Signal Description

the line, as SDO is configured as an open drain). from different masters in a multi-master system. Control Register (SPICR), select the clock rate. (mostly used with more complex protocols).

Figure 66. SPI I/O Pins

9.4.4 Interrupt Structure

– End of transmission (after each byte). – S-bus/I2C-bus start or stop condition. Table 25. Interrupt Configuration

1 X End of a byte transmission

9.4.5 Working With Other Protocols

before changing the SPI protocol. how to manage these protocols. an interrupt request is performed. Figure 67. S-Bus / I

Table 26. Typical I2C-bus Sequences Figure 68. SPI Data and Clock Timing (for I2C protocol)

9.4.7 S-Bus Interface

Figure 71. The additional line is referred as SEN. ware control (see Figure 67). Figure 70. Mixed S-bus and I Figure 71. S-bus Configuration

9.4.8 IM-bus Interface

Ω pull-up resistors are required). generate the stop condition. Figure 72. ST9 and IM-bus Peripheral Figure 73. IM bus Timing

ST90158 - SERIAL PERIPHERAL INTERFACE (SPI) SERIAL PERIPHERAL INTERFACE (Cont’d)

9.4.9 Register Description

It is possible to have up to 3 independent SPIs in the same device (refer to the device block dia- gram). In this case they are named SPI0 thru SPI2. If the device has one SPI converter it uses the register adresses of SPI0. The register map is the following: Note: In the register description on the following pages, register and page numbers are given using the example of SPI0. SPI DATA REGISTER (SPIDR) R253 - Read/Write Register Page: 0 Reset Value: undefined Bit 7:0 =D[0:7]: SPI Data. This register contains the data transmitted and re- ceived by the SPI. Data is transmitted bit 7 first, and incoming data is received into bit 0. Transmis- sion is started by writing to this register. Note: SPIDR state remains undefined until the end of transmission of the first byte. SPI CONTROL REGISTER (SPICR) R254 -Read/Write Register Page: 0 Reset Value: 0000 0000 (00h) Bit 7 =SPEN : Serial Peripheral Enable. 0: SCK and SDO are kept tristate. 1: Both alternate functions SCK and SDO are ena- bled. Note:furthermore, SPEN (together with the BMS bit) affects the selection of the source for interrupt channel B0. Transmission starts when data is writ- ten to the SPIDR Register. Bit 6 =BMS :S-bus/I2C-bus Mode Selector. 0: Perform a re-initialisation of the SPI logic, thus allowing recovery procedures after a RX/TX fail- ure. 1: Enable S-bus/I 2C-bus arbitration, clock synchro- nization and Start/ Stop detection (SPI used in an S-bus/I2C-bus protocol). Note:when the BMS bit is reset, it affects (togeth- er with the SPEN bit) the selection of the source for interrupt channel B0. Bit 5 =ARB :Arbitration flag bit. This bit is set by hardware and can be reset by software. 0: S-bus/I2C-bus stop condition is detected. 1: Arbitration lost by the SPI in S-bus/I2C-bus mode. Note:when ARB is set automatically, the SDO pin is set to a high value until a write instruction on SPIDR is performed. Bit 4 =BUSY :SPI Busy Flag. This bit is set by hardware. It allows the user to monitor the SPI status by polling its value. 0: No transmission in progress. 1: Transmission in progress. Bit 3 =CPOL : Transmission Clock Polarity. CPOL controls the normal or steady state value of the clock when data is not being transferred. Please refer to the following table and to Figure 74 to see this bit action (together with the CPHA bit). Note:As the SCK line is held in a high impedance state when the SPI is disabled (SPEN = “0”), the SCK pin must be connected to V SS or to VCC through a resistor, depending on the CPOL state. Polarity should be set during the initialisation rou- tine, in accordance with the setting of all peripher- als, and should not be changed during program execution. Register SPIn Page SPIDR R253 SPI0 0 SPICR R254 SPI0 0 SPIDR1 R253 SPI1 7 SPICR1 R254 SPI1 7 SPIDR2 R245 SPI2 7 SPICR2 R246 SPI2 7 D7 D6 D5 D4 D3 D2 D1 D0 SPEN BMS ARB BUSY CPOL CPHA SPR1 SPR0

Bit 2 =CPHA :Transmission Clock Phase. cates active clock edges and strobe times. Figure 74. SPI Data and Clock Timing

9.5 SERIAL COMMUNICATIONS INTERFACE (SCI)

9.5.1 Introduction

address interrupt generation. – 5, 6, 7, or 8 bit word length. – Complete status reporting capabilities. – Line break generation and detection. Figure 75. SCI Block Diagram

9.5.2 Functional Description

(1X, 16X) and in the protocol used. Figure 76. SCI Functional Schematic Note:Some pins may not be available on some devices. Refer to the device Pinout Description.

9.5.3 SCI Operating Modes

9.5.3.1 Asynchronous Mode

sampled 16 times per clock period. ator output) is set to suit.

9.5.3.2 Asynchronous Mode with Synchronous

each data bit is sampled once per clock period. INTCLK periods between clock and data. the SCI on the rising edge of the receive clock. Figure 77. Sampling Times in Asynchronous Format

ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d)

9.5.3.3 Serial Expansion Mode

This mode is used to communicate with an exter- nal synchronous peripheral. The transmitter only provides the clock waveform during the period that data is being transmitted on the CLKOUT pin (the Data Envelope). Data is latched on the rising edge of this clock. Whenever the SCI is to receive data in serial port expansion mode, the clock must be supplied ex- ternally, and be synchronous with the transmitted data. The SCI latches the incoming data on the ris- ing edge of the received clock, which is input on the RXCLK pin.

9.5.3.4 Synchronous Mode

This mode is used to access an external synchro- nous peripheral, dummy start/stop bits are not in- cluded in the data frame. Polarity, stand-by level and active edges of I/O signals are fully and sepa- rately programmable for both inputs and outputs. It’s necessary to set the SMEN bit of the Synchro- nous Input Control Register (SICR) to enable this mode and all the related extra features (otherwise disabled). The transmitter will provide the clock waveform only during the period when the data is being transmitted via the CLKOUT pin, which can be en- abled by setting both the XTCLK and OCLK bits of the Clock Configuration Register. Whenever the SCI is to receive data in synchronous mode, the clock waveform must be supplied externally via the RXCLK pin and be synchronous with the data. For correct receiver operation, the XRX bit of the Clock Configuration Register must be set. Two external signals, Request-To-Send and Data- Carrier-Detect (RTS/DCD), can be enabled to syn- chronise the data exchange between two serial units. The RTS output becomes active just before the first active edge of CLKOUT and indicates to the target device that the MCU is about to send a synchronous frame; it returns to its stand-by state following the last active edge of CLKOUT (MSB transmitted). The DCD input can be considered as a gate that filters RXCLK and informs the MCU that a trans- mitting device is transmitting a data frame. Polarity of RTS/DCD is individually programmable, as for clocks and data. The data word is programmable from 5 to 8 bits, as for the other modes; parity, address/9th, stop bits and break cannot be inserted into the transmitted frame. Programming of the related bits of the SCI control registers is irrelevant in Synchronous Mode: all the corresponding interrupt requests must, in any case, be masked in order to avoid in- correct operation during data reception.

Figure 78. SCI Operating Modes Note:In all operating modes, the Least Significant Bit is transmitted/received first.

9.5.4 Serial Frame Format

condition is detected as a high to low transition. chronous modes. LSB are transmitted first. to indicate that the data is an address (bit set). tional data bit or to mark control words (9th bit). Figure 79. SCI Character Formats

9.5.4.1 Data transfer

the program into the Transmitter Buffer Register. unused most significant bits will be set. the transmitter/receiver clock. INTCLK or the Receiver clock input via RXCLK. plete word length and until the SB bit is Reset. frame for the Synchronous mode. ure 82 for these different configurations. Table 27. Address Interrupt Modes

9.5.5 Clocks And Serial Transmission Rates

vided in the 3 other modes (CD set). in accordance with the setting of the CD bit. Input Clock frequency divided by the Divisor value. 0 or 1 will stop the divider.

9.5.6 SCI Initialization Procedure

new value and start counting. clock are internally synchronized to INTCLK. Figure 83. SCI Baud Rate Generator Initialization Sequence

Table 28. SCI Baud Rate Generator Divider Values Example 1 Table 29. SCI Baud Rate Generator Divider Values Example 2

9.5.7 Input Signals

input to the SCI receiver shift register. INTCLK. The use of the TXCLK pin is optional. riod before the first active edge of the input clock.

9.5.8 Output Signals

SCI transmitter in all operating modes. enables the Serial Expansion Mode. disables it for PLM applications. level can be programmed high or low. Figure 84. Receiver and Transmitter Clock Frequencies

0 INTCLK/4 16x mode

0 INTCLK/2 16x mode

9.5.9 Interrupts and DMA

9.5.9.1 Interrupts

SCI peripheral are illustrated in Figure 85. mer during the Interrupt Service routine. er vectors to be resolved to an 8 byte block size. more details relating to Synchronous mode. Table 30. SCI Interrupt Internal Priority

Table 31. SCI Interrupt Vectors Figure 85. SCI Interrupts: Example of Typical Usage

ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d)

9.5.9.2 DMA

Two DMA channels are associated with the SCI, for transmit and for receive. These follow the reg- ister scheme as described in the DMA chapter. DMA Reception To perform a DMA transfer in reception mode: 1. Initialize the DMA counter (RDCPR) and DMA address (RDAPR) registers 2. Enable DMA by setting the RXD bit in the IDPR register. 3. DMA transfer is started when data is received by the SCI. DMA Transmission To perform a DMA transfer in transmission mode: 1. Initialize the DMA counter (TDCPR) and DMA address (TDAPR) registers. 2. Enable DMA by setting the TXD bit in the IDPR register. 3. DMA transfer is started by writing a byte in the Transmitter Buffer register (TXBR). If this byte is the first data byte to be transmitted, the DMA counter and address registers must be initialized to begin DMA transmission at the sec- ond byte. Alternatively, DMA transfer can be start- ed by writing a dummy byte in the TXBR register. DMA Interrupts When DMA is active, the Received Data Pending and the Transmitter Shift Register Empty interrupt sources are replaced by the DMA End Of Block re- ceive and transmit interrupt sources. Note: To handle DMA transfer correctly in trans- mission, the BSN bit in the IMR register must be cleared. This selects the Transmitter Shift Register Empty event as the DMA interrupt source. The transfer of the last byte of a DMA data block will be followed by a DMA End Of Block transmit or receive interrupt, setting the TXEOB or RXEOB bit. A typical Transmission End Of Block interrupt rou- tine will perform the following actions: 1. Restore the DMA counter register (TDCPR). 2. Restore the DMA address register (TDAPR). 3. Clear the Transmitter Shift Register Empty bit TXSEM in the S_ISR register to avoid spurious interrupts. 4. Clear the Transmitter End Of Block (TXEOB) pending bit in the IMR register. 5. Set the TXD bit in the IDPR register to enable DMA. 6. Load the Transmitter Buffer Register (TXBR) with the next byte to transmit. The above procedure handles the case where a further DMA transfer is to be performed. Error Interrupt Handling If an error interrupt occurs while DMA is enabled in reception mode, DMA transfer is stopped. To resume DMA transfer, the error interrupt han- dling routine must clear the corresponding error flag. In the case of an Overrun error, the routine must also read the RXBR register. Character Search Mode with DMA In Character Search Mode with DMA, when a character match occurs, this character is not trans- ferred. DMA continues with the next received char- acter. To avoid an Overrun error occurring, the Character Match interrupt service routine must read the RXBR register.

ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d)

9.5.10 Register Description

The SCI registers are located in the following pag- es in the ST9: SCI number 0: page 24 (18h) SCI number 1: page 25 (19h) (when present) The SCI is controlled by the following registers: Address Register R240 (F0h) Receiver DMA Transaction Counter Pointer Register R241 (F1h) Receiver DMA Source Address Pointer Register R242 (F2h) Transmitter DMA Transaction Counter Pointer Register R243 (F3h) Transmitter DMA Destination Address Pointer Register R244 (F4h) Interrupt Vector Register R245 (F5h) Address Compare Register R246 (F6h) Interrupt Mask Register R247 (F7h) Interrupt Status Register R248 (F8h) Receive Buffer Register same Address as Transmitter Buffer Register (Read Only) R248 (F8h) Transmitter Buffer Register same Address as Receive Buffer Register (Write only) R249 (F9h) Interrupt/DMA Priority Register R250 (FAh) Character Configuration Register R251 (FBh) Clock Configuration Register R252 (FCh) Baud Rate Generator High Register R253 (FDh) Baud Rate Generator Low Register R254 (FEh) Synchronous Input Control Register R255 (FFh) Synchronous Output Control Register

ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) RECEIVER DMA COUNTER POINTER (RDCPR) R240 - Read/Write Reset value: undefined Bit 7:1 =RC[7:1]: Receiver DMA Counter Pointer. These bits contain the address of the receiver DMA transaction counter in the Register File. Bit 0 =RR/M :Receiver Register File/Memory Se- lector. 0: Select Memory space as destination. 1: Select the Register File as destination. RECEIVER DMA ADDRESS POINTER (RDAPR) R241 - Read/Write Reset value: undefined Bit 7:1 =RA[7:1]: Receiver DMA Address Pointer. These bits contain the address of the pointer (in the Register File) of the receiver DMA data source. Bit 0 =RPS :Receiver DMA Memory Pointer Se- lector. This bit is only significant if memory has been se- lected for DMA transfers (RR/M = 0 in the RDCPR register). 0: Select ISR register for receiver DMA transfers address extension. 1: Select DMASR register for receiver DMA trans- fers address extension. TRANSMITTER DMA COUNTER POINTER (TDCPR) R242 - Read/Write Reset value: undefined Bit 7:1 =TC[7:1]: Transmitter DMA Counter Point- er. These bits contain the address of the transmitter DMA transaction counter in the Register File. Bit 0 =TR/M : Transmitter Register File/Memory Selector. 0: Select Memory space as source. 1: Select the Register File as source. TRANSMITTER DMA ADDRESS POINTER (TDAPR) R243 - Read/Write Reset value: undefined Bit 7:1 =TA[7:1]: Transmitter DMA Address Point- er. These bits contain the address of the pointer (in the Register File) of the transmitter DMA data source. Bit 0 =TPS : Transmitter DMA Memory Pointer Se- lector. This bit is only significant if memory has been se- lected for DMA transfers (TR/M = 0 in the TDCPR register). 0: Select ISR register for transmitter DMA transfers address extension. 1: Select DMASR register for transmitter DMA transfers address extension. RC7 RC6 RC5 RC4 RC3 RC2 RC1 RR/M RA7 RA6 RA5 RA4 RA3 RA2 RA1 RPS TC7 TC6 TC5 TC4 TC3 TC2 TC1 TR/M TA7 TA6 TA5 TA4 TA3 TA2 TA1 TPS

ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT VECTOR REGISTER (S_IVR) R244 - Read/Write Reset value: undefined Bit 7:3 =V[7:3]: SCI Interrupt Vector Base Ad- dress. User programmable interrupt vector bits for trans- mitter and receiver. Bit 2:1 =EV[2:1]:Encoded Interrupt Source. Both bits EV2 and EV1 are read only and set by hardware according to the interrupt source. Bit 0 =D0 : This bit is forced by hardware to 0. ADDRESS/DATA COMPARE REGISTER (ACR) R245 - Read/Write Reset value: undefined Bit 7:0 =AC[7:0]: Address/Compare Character. With either 9th bit address mode, address after break mode, or character search, the received ad- dress will be compared to the value stored in this register. When a valid address matches this regis- ter content, the Receiver Address Pending bit (RXAP in the S_ISR register) is set. After the RXAP bit is set in an addressed mode, all received data words will be transferred to the Receiver Buff- er Register. V7 V6 V5 V4 V3 EV2 EV1 0 EV2 EV1 Interrupt source 0 0 Receiver Error (Overrun, Framing, Parity) 0 1 Break Detect or Address Match

10 Received Data Pending/Receiver DMA

11 Transmitter buffer or shift register empty

transmitter DMA End of Block AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT MASK REGISTER (IMR) R246 - Read/Write Reset value: 0xx00000 Bit 7 =BSN : Buffer or shift register empty inter- rupt. This bit selects the source of the transmitter regis- ter empty interrupt. 0: Select a Shift Register Empty as source of a Transmitter Register Empty interrupt. 1: Select a Buffer Register Empty as source of a Transmitter Register Empty interrupt. Bit 6 =RXEOB : Received End of Block. This bit is set by hardware only and must be reset by software. RXEOB is set after a receiver DMA cycle to mark the end of a data block. 0: Clear the interrupt request. 1: Mark the end of a received block of data. Bit 5 =TXEOB :Transmitter End of Block. This bit is set by hardware only and must be reset by software. TXEOB is set after a transmitter DMA cycle to mark the end of a data block. 0: Clear the interrupt request. 1: Mark the end of a transmitted block of data. Bit 4 =RXE : Receiver Error Mask. 0: Disable Receiver error interrupts (OE, PE, and FE pending bits in the S_ISR register). 1: Enable Receiver error interrupts. Bit 3 =RXA :Receiver Address Mask. 0: Disable Receiver Address interrupt (RXAP pending bit in the S_ISR register). 1: Enable Receiver Address interrupt. Bit 2 =RXB :Receiver Break Mask. 0: Disable Receiver Break interrupt (RXBP pend- ing bit in the S_ISR register). 1: Enable Receiver Break interrupt. Bit 1 =RXDI :Receiver Data Interrupt Mask. 0: Disable Receiver Data Pending and Receiver End of Block interrupts (RXDP and RXEOB pending bits in the S_ISR register). 1: Enable Receiver Data Pending and Receiver End of Block interrupts. Note:RXDI has no effect on DMA transfers. Bit 0 =TXDI:Transmitter Data Interrupt Mask. 0: Disable Transmitter Buffer Register Empty, Transmitter Shift Register Empty, or Transmitter End of Block interrupts (TXBEM, TXSEM, and TXEOB bits in the S_ISR register). 1: Enable Transmitter Buffer Register Empty, Transmitter Shift Register Empty, or Transmitter End of Block interrupts. Note:TXDI has no effect on DMA transfers. BSN RXEOB TXEOB RXE RXA RXB RXDI TXDI

ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT STATUS REGISTER (S_ISR) R247 - Read/Write Reset value: undefined Bit 7 =OE : Overrun Error Pending. This bit is set by hardware if the data in the Receiv- er Buffer Register was not read by the CPU before the next character was transferred into the Receiv- er Buffer Register (the previous data is lost). 0: No Overrun Error. 1: Overrun Error occurred. Bit 6 =FE : Framing Error Pending bit. This bit is set by hardware if the received data word did not have a valid stop bit. 0: No Framing Error. 1: Framing Error occurred. Note: In the case where a framing error occurs when the SCI is programmed in address mode and is monitoring an address, the interrupt is as- serted and the corrupted data element is trans- ferred to the Receiver Buffer Register. Bit 5 =PE : Parity Error Pending. This bit is set by hardware if the received word did not have the correct even or odd parity bit. 0: No Parity Error. 1: Parity Error occurred. Bit 4 =RXAP : Receiver Address Pending. RXAP is set by hardware after an interrupt ac- knowledged in the address mode. 0: No interrupt in address mode. 1: Interrupt in address mode occurred. Note:The source of this interrupt is given by the couple of bits (AMEN, AM) as detailed in the IDPR register description. Bit 3 =RXBP : Receiver Break Pending bit. This bit is set by hardware if the received data in- put is held low for the full word transmission time (start bit, data bits, parity bit, stop bit). 0: No break received. 1: Break event occurred. Bit 2 =RXDP : Receiver Data Pending bit. This bit is set by hardware when data is loaded into the Receiver Buffer Register. 0: No data received. 1: Data received in Receiver Buffer Register. Bit 1 =TXBEM :Transmitter Buffer Register Emp- ty. This bit is set by hardware if the Buffer Register is empty. 0: No Buffer Register Empty event. 1: Buffer Register Empty. Bit 0 =TXSEM : Transmitter Shift Register Empty. This bit is set by hardware if the Shift Register has completed the transmission of the available data. 0: No Shift Register Empty event. 1: Shift Register Empty. Note:The Interrupt Status Register bits can be re- set but cannot be set by the user. The interrupt source must be cleared by resetting the related bit when executing the interrupt service routine (natu- rally the other pending bits should not be reset). OE FE PE RXAP RXBP RXDP TXBEM TXSEM

ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) RECEIVER BUFFER REGISTER (RXBR) R248 - Read only Reset value: undefined Bit 7:0 =RD[7:0]: Received Data. This register stores the data portion of the re- ceived word. The data will be transferred from the Receiver Shift Register into the Receiver Buffer Register at the end of the word. All receiver inter- rupt conditions will be updated at the time of trans- fer. If the selected character format is less than 8 bits, unused most significant bits will forced to “1”. Note: RXBR and TXBR are two physically differ- ent registers located at the same address. TRANSMITTER BUFFER REGISTER (TXBR) R248 - Write only Reset value: undefined Bit 7:0 =TD[7:0]: Transmit Data. The ST9 core will load the data for transmission into this register. The SCI will transfer the data from the buffer into the Shift Register when availa- ble. At the transfer, the Transmitter Buffer Register interrupt is updated. If the selected word format is less than 8 bits, the unused most significant bits are not significant. Note:TXBR and RXBR are two physically differ- ent registers located at the same address. RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 TD7 TD6 TD5 TD4 TD3 TD2 TD1 TD0

ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) INTERRUPT/DMA PRIORITY REGISTER (IDPR) R249 - Read/Write Reset value: undefined Bit 7 =AMEN : Address Mode Enable. This bit, together with the AM bit (in the CHCR reg- ister), decodes the desired addressing/9th data bit/character match operation. In Address mode the SCI monitors the input serial data until its address is detected Note:Upon reception of address, the RXAP bit (in the Interrupt Status Register) is set and an inter- rupt cycle can begin. The address character will not be transferred into the Receiver Buffer Regis- ter but all data following the matched SCI address and preceding the next address word will be trans- ferred to the Receiver Buffer Register and the proper interrupts updated. If the address does not match, all data following this unmatched address will not be transferred to the Receiver Buffer Reg- ister. In any of the cases the RXAP bit must be reset by software before the next word is transferred into the Buffer Register. When AMEN is reset and AM is set, a useful char- acter search function is performed. This allows the SCI to generate an interrupt whenever a specific character is encountered (e.g. Carriage Return). Bit 6 =SB : Set Break. 0: Stop the break transmission after minimum break length. 1: Transmit a break following the transmission of all data in the Transmitter Shift Register and the Buffer Register. Note:The break will be a low level on the transmit- ter data output for at least one complete word for- mat. If software does not reset SB before the min- imum break length has finished, the break condi- tion will continue until software resets SB. The SCI terminates the break condition with a high level on the transmitter data output for one transmission clock period. Bit 5 =SA : Set Address. If an address/9th data bit mode is selected, SA val- ue will be loaded for transmission into the Shift Register. This bit is cleared by hardware after its load. 0: Indicate it is not an address word. 1: Indicate an address word. Note: Proper procedure would be, when the Transmitter Buffer Register is empty, to load the value of SA and then load the data into the Trans- mitter Buffer Register. Bit 4 =RXD : Receiver DMA Mask. This bit is reset by hardware when the transaction counter value decrements to zero. At that time a receiver End of Block interrupt can occur. 0: Disable Receiver DMA request (the RXDP bit in the S_ISR register can request an interrupt). 1: Enable Receiver DMA request (the RXDP bit in the S_ISR register can request a DMA transfer). Bit 3 =TXD : Transmitter DMA Mask. This bit is reset by hardware when the transaction counter value decrements to zero. At that time a transmitter End Of Block interrupt can occur. 0: Disable Transmitter DMA request (TXBEM or TXSEM bits in S_ISR can request an interrupt). 1: Enable Transmitter DMA request (TXBEM or TXSEM bits in S_ISR can request a DMA trans- fer). Bit 2:0 =PRL[2:0]: SCI Interrupt/DMA Priority bits. The priority for the SCI is encoded with (PRL2,PRL1,PRL0). Priority level 0 is the highest, while level 7 represents no priority. When the user has defined a priority level for the SCI, priorities within the SCI are hardware defined. These SCI internal priorities are: AMEN SB SA RXD TXD PRL2 PRL1 PRL0 AMEN AM 0 0 Address interrupt if 9th data bit = 1 0 1 Address interrupt if character match

10 Address interrupt if character match

and 9th data bit =1

11 Address interrupt if character match

with word immediately following Break Receiver DMA request highest priority Transmitter DMA request Receiver interrupt Transmitter interrupt lowest priority

ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) CHARACTER CONFIGURATION REGISTER (CHCR) R250 - Read/Write Reset value: undefined Bit 7 =AM :Address Mode. This bit, together with the AMEN bit (in the IDPR register), decodes the desired addressing/9th data bit/character match operation. Please refer to the table in the IDPR register description. Bit 6 =EP : Even Parity. 0: Select odd parity (when parity is enabled). 1: Select even parity (when parity is enabled). Bit 5 =PEN : Parity Enable. 0: No parity bit. 1: Parity bit generated (transmit data) or checked (received data). Note: If the address/9th bit is enabled, the parity bit will precede the address/9th bit (the 9th bit is never included in the parity calculation). Bit 4 =AB :Address/9th Bit. 0: No Address/9th bit. 1: Address/9th bit included in the character format between the parity bit and the first stop bit. This bit can be used to address the SCI or as a ninth data bit. Bit 3:2 =SB[1:0]:Number of Stop Bits.. Bit 1:0 =WL[1:0]:Number of Data Bits AM EP PEN AB SB1 SB0 WL1 WL0 SB1 SB0 Number of stop bits in 16X mode in 1X mode 00 1 1 0 1 1.5 2 10 2 2 1 1 2.5 3 WL1 WL0 Data Length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits

ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) CLOCK CONFIGURATION REGISTER (CCR) R251 - Read/Write Reset value: 0000 0000 (00h) Bit 7 =XTCLK This bit, together with the OCLK bit, selects the source for the transmitter clock. The following ta- ble shows the coding of XTCLK and OCLK. Bit 6 =OCLK This bit, together with the XTCLK bit, selects the source for the transmitter clock. The following ta- ble shows the coding of XTCLK and OCLK. Bit 5 =XRX : External Receiver Clock Source. 0: External receiver clock source not used. 1: Select the external receiver clock source. Note:The external receiver clock frequency must be 16 times the data rate, or equal to the data rate, depending on the status of the CD bit. Bit 4 = XBRG : Baud Rate Generator Clock Source. 0: Select INTCLK for the baud rate generator. 1: Select the external receiver clock for the baud rate generator. Bit 3 =CD :Clock Divisor. The status of CD will determine the SCI configura- tion (synchronous/asynchronous). 0: Select 16X clock mode for both receiver and transmitter. 1: Select 1X clock mode for both receiver and transmitter. Note:In 1X clock mode, the transmitter will trans- mit data at one data bit per clock period. In 16X mode each data bit period will be 16 clock periods long. Bit 2 =AEN :Auto Echo Enable. 0: No auto echo mode. 1: Put the SCI in auto echo mode. Note: Auto Echo mode has the following effect: the SCI transmitter is disconnected from the data- out pin SOUT, which is driven directly by the re- ceiver data-in pin, SIN. The receiver remains con- nected to SIN and is operational, unless loopback mode is also selected. Bit 1 =LBEN :Loopback Enable. 0: No loopback mode. 1: Put the SCI in loopback mode. Note:In this mode, the transmitter output is set to a high level, the receiver input is disconnected, and the output of the Transmitter Shift Register is looped back into the Receiver Shift Register input. All interrupt sources (transmitter and receiver) are operational. Bit 0 =STPEN :Stick Parity Enable. 0: The transmitter and the receiver will follow the parity of even parity bit EP in the CHCR register. 1: The transmitter and the receiver will use the op- posite parity type selected by the even parity bit EP in the CHCR register. XTCLK OCLK XRX XBRG CD AEN LBEN STPEN XTCLK OCLK Pin Function 0 0 Pin is used as a general I/O 0 1 Pin = TXCLK (used as an input)

10 Pin = CLKOUT (outputs the Baud

Rate Generator clock) Pin =CLKOUT (outputs the Serial expansion and synchronous mode clock) EP SPEN Parity (Transmitter & Receiver) 0 (odd) 0 Odd 1 (even) 0 Even 0 (odd) 1 Even 1 (even) 1 Odd 9

ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) BAUD RATE GENERATOR HIGH REGISTER (BRGHR) R252 - Read/Write Reset value: undefined BAUD RATE GENERATOR LOW REGISTER (BRGLR) R253 -Read/Write Reset value: undefined Bit 15:0 =Baud Rate Generator MSB and LSB. The Baud Rate generator is a programmable di- vide by “N” counter which can be used to generate the clocks for the transmitter and/or receiver. This counter divides the clock input by the value in the Baud Rate Generator Register. The minimum baud rate divisor is 2 and the maximum divisor is 16-1. After initialization of the baud rate genera- tor, the divisor value is immediately loaded into the counter. This prevents potentially long random counts on the initial load. If set to 0 or 1, the Baud Rate Generator is stopped. SYNCHRONOUS INPUT CONTROL (SICR) R254 - Read/Write Reset value: 0000 0011 (03h) Bit 7 =SMEN : Synchronous Mode Enable. 0: Disable all features relating to Synchronous mode (the contents of SICR and SOCR are ig- nored). 1: Select Synchronous mode with its programmed I/O configuration. Bit 6 =INPL: SIN Input Polarity. 0: Polarity not inverted. 1: Polarity inverted. Note: INPL only affects received data. In Auto- Echo mode SOUT = SIN even if INPL is set. In Loop-Back mode the state of the INPL bit is irrele- vant. Bit 5 =XCKPL : Receiver Clock Polarity. 0: RXCLK is active on the rising edge. 1: RXCLK is active on the falling edge. Note: XCKPL only affects the receiver clock. In Auto-Echo mode CLKOUT = RXCLK independ- ently of the XCKPL status. In Loop-Back the state of the XCKPL bit is irrelevant. Bit 4 =DCDEN : DCD Input Enable. 0: Disable hardware synchronization. 1: Enable hardware synchronization. Note:When DCDEN is set, RXCLK drives the re- ceiver section only during the active level of the DCD input (DCD works as a gate on RXCLK, in- forming the MCU that a transmitting device is sending a synchronous frame to it). Bit 3 =DCDPL : DCD Input Polarity. 0: The DCD input is active when LOW. 1: The DCD input is active when HIGH. Note:DCDPL only affects the gating activity of the receiver clock. In Auto-Echo mode RTS = DCD in- dependently of DCDPL. In Loop-Back mode, the state of DCDPL is irrelevant. Bit 2 =INPEN : All Input Disable. 0: Enable SIN/RXCLK/DCD inputs. 1: Disable SIN/RXCLK/DCD inputs. Bit 1:0 = “Don’t Care” 15 8 BG15 BG14 BG13 BG12 BG11 BG10 BG9 BG8 BG7 BG6 BG5 BG4 BG3 BG2 BG1 BG0 SMEN INPL XCKPL DCDE N DCDP L INPEN X X

ST90158 - SERIAL COMMUNICATIONS INTERFACE (SCI) SERIAL COMMUNICATIONS INTERFACE (Cont’d) SYNCHRONOUS OUTPUT CONTROL (SOCR) R255 - Read/Write Reset value: 0000 0001 (01h) Bit 7 =OUTPL : SOUT Output Polarity. 0: Polarity not inverted. 1: Polarity inverted. Note: OUTPL only affects the data sent by the transmitter section. In Auto-Echo mode SOUT = SIN even if OUTPL=1. In Loop-Back mode, the state of OUTPL is irrelevant. Bit 6 =OUTSB : SOUT Output Stand-By Level. 0: SOUT stand-by level is HIGH. 1: SOUT stand-by level is LOW. Bit 5 =OCKPL :Transmitter Clock Polarity. 0: CLKOUT is active on the rising edge. 1: CLKOUT is active on the falling edge. Note:OCKPL only affects the transmitter clock. In Auto-Echo mode CLKOUT = RXCLK independ- ently of the state of OCKPL. In Loop-Back mode the state of OCKPL is irrelevant. Bit 4 =OCKSB : Transmitter Clock Stand-By Lev- el. 0: The CLKOUT stand-by level is HIGH. 1: The CLKOUT stand-by level is LOW. Bit 3 =RTSEN :RTS and SDS Output Enable. 0: Disable the RTS and SDS hardware synchroni- sation. 1: Enable the RTS and SDS hardware synchroni- sation. Notes: – When RTSEN is set, the RTS output becomes active just before the first active edge of CLK- OUT and indicates to target device that the MCU is about to send a synchronous frame; it returns to its stand-by value just after the last active edge of CLKOUT (MSB transmitted). – When RTSEN is set, the SDS output becomes active high and indicates to the target device that the MCU is about to send the first bit of a syn- chronous frame on the Serial Output Pin (SOUT); it returns to low level as soon as the second bit is sent on the Serial Output Pin (SOUT). In this way a positive pulse is generated each time that the first bit of a synchronous frame is present on the Serial Output Pin (SOUT). Bit 2 =RTSPL : RTS Output Polarity. 0: The RTS output is active when LOW. 1: The RTS output is active when HIGH. Note:RTSPL only affects the RTS activity on the output pin. In Auto-Echo mode RTS = DCD inde- pendently from the RTSPL value. In Loop-Back mode RTSPL value is ’Don’t Care’. Bit 1 =OUTDIS : Disable all outputs. This feature is available on specific devices only (see device pin-out description). When OUTDIS=1, all output pins (if configured in Alternate Function mode) will be put in High Im- pedance for networking. 0: SOUT/CLKOUT/enabled 1: SOUT/CLKOUT/RTS put in high impedance Bit 0 = “Don’t Care” OUTP L OUTS B OCKP L OCKS B RTSE N RTS PL OUT DIS X

9.6 EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D)

9.6.1 Introduction

feeding a successive approximation converter. and the analog VDD reference. which determines the full scale converted value. Figure 86. Block Diagram

ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) Single and continuous conversion modes are available. Conversion may be triggered by an ex- ternal signal or, internally, by the Multifunction Timer. A Power-Down programmable bit allows the A/D to be set in low-power idle mode. The A/D’s Interrupt Unit provides two maskable channels (Analog Watchdog and End of Conver- sion) with hardware fixed priority, and up to 7 pro- grammable priority levels. CAUTION : A/D INPUT PIN CONFIGURATION The input Analog channel is selected by using the I/O pin Alternate Function setting (PXC2, PXC1, PXC0 = 1,1,1) as described in the I/O ports sec- tion. The I/O pin configuration of the port connect- ed to the A/D converter is modified in order to pre- vent the analog voltage present on the I/O pin from causing high power dissipation across the input buffer. Deselected analog channels should also be maintained in Alternate function configuration for the same reason.

9.6.2 Functional Description

9.6.2.1 Operating Modes

Two operating modes are available: Continuous Mode and Single Mode. To enter one of these modes it is necessary to program the CONT bit of the Control Logic Register. Continuous Mode is selected when CONT is set, while Single Mode is selected when CONT is reset. Both modes operate in AUTOSCAN configuration, allowing sequential conversion of the input chan- nels. The number of analog inputs to be converted may be set by software, by setting the number of the first channel to be converted into the Control Register (SC2, SC1, SC0 bits). As each conver- sion is completed, the channel number is automat- ically incremented, up to channel 7. For example, if SC2, SC1, SC0 are set to 0,1,1, conversion will proceed from channel 3 to channel 7, whereas, if SC2, SC1, SC0 are set to 1,1,1, only channel 7 will be converted. When the ST bit of the Control Logic Register is set, either by software or by hardware (by an inter- nal or external synchronisation trigger signal), the analog inputs are sequentially converted (from the first selected channel up to channel 7) and the re- sults are stored in the relevant Data Registers. InSingle Mode (CONT = “0”), the ST bit is reset by hardware following conversion of channel 7; an End of Conversion (ECV) interrupt request is is- sued and the A/D waits for a new start event. InContinuous Mode (CONT = “1”), a continuous conversion flow is initiated by the start event. When conversion of channel 7 is complete, con- version of channel ’s’ is initiated (where ’s’ is spec- ified by the setting of the SC2, SC1 and SC0 bits); this will continue until the ST bit is reset by soft- ware. In all cases, an ECV interrupt is issued each time channel 7 conversion ends. When channel ’i’ is converted (’s’ <’i’ <7), the relat- ed Data Register is reloaded with the new conver- sion result and the previous value is lost. The End of Conversion (ECV) interrupt service routine can be used to save the current values before a new conversion sequence (so as to create signal sam- ple tables in the Register File or in Memory).

9.6.2.2 Triggering and Synchronisation

In both modes, conversion may be triggered by in- ternal or external conditions; externally this may be tied to EXTRG, as an Alternate Function input on an I/O port pin, and internally, it may be tied to INTRG, generated by a Multifunction Timer pe- ripheral. Both external and internal events can be separately masked by programming the EXTG/ INTG bits of the Control Logic Register (CLR). The events are internally ORed, thus avoiding potential hardware conflicts. However, the correct proce- dure is to enable only one alternate synchronisa- tion condition at any time. The effect either of these synchronisation modes is to set the ST bit by hardware. This bit is reset, in Single Mode only, at the end of each group of con- versions. In Continuous Mode, all trigger pulses after the first are ignored. The synchronisation sources must be at a logic low level for at least the duration of one INTCLK cycle and, in Single Mode, the period between trig- ger pulses must be greater than the total time re- quired for a group of conversions. If a trigger oc- curs when the ST bit is still set, i.e. when conver- sion is still in progress, it will be ignored. On devices where two A/D Converters are present they can be triggered from the same source.

9.6.2.3 Analog Watchdogs

Two internal Analog Watchdogs are available for highly flexible automatic threshold monitoring of external analog signal levels. Converter External Trigger On Chip Event (Internal trigger) A/D 0 EXTRG pin MFT 0A/D 1

their respective Lower thresholds. MSBs being associated with a threshold condition. Following a hardware reset, these flags are reset.

9.6.2.4 Power Down Mode

Figure 87. A/D Trigger Source

Figure 88. Application Example: Analog Watchdog used in Motorspeed Control

9.6.3 Interrupts

of the correct interrupt service routine. service routines are stored. of Conversion request, which is held pending. Watchdog Request flag in the AD_ICR Register.

9.6.3.1 Register Mapping

converter it uses the register addresses of A/D 0.

70 Lower

70 Upper

ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d)

9.6.4 Register Description

DATA REGISTERS (DiR) The conversion results for the 8 available chan- nels are loaded into the 8 Data registers following conversion of the corresponding analog input. CHANNEL 0 DATA REGISTER (D0R) R240 - Read/Write Register Page: 63 Reset Value: undefined Bit 7:0 =D0.[7:0]: Channel 0 Data. CHANNEL 1 DATA REGISTER (D1R) R241 - Read/Write Register Page: 63 Reset Value: undefined Bit 7:0 =D1.[7:0]: Channel 1 Data. CHANNEL 2 DATA REGISTER (D2R) R242 - Read/Write Register Page: 63 Reset Value: undefined Bit 7:0 =D2.[7:0]: Channel 2 Data. CHANNEL 3 DATA REGISTER (D3R) R243 - Read/Write Register Page: 63 Reset Value: undefined Bit 7:0 =D3.[7:0]: Channel 3 Data. CHANNEL 4 DATA REGISTER (D4R) R244 - Read/Write Register Page: 63 Reset Value: undefined Bit 7:0 =D4.[7:0]:Channel 4 Data CHANNEL 5 DATA REGISTER (D5R) R245 - Read/Write Register Page: 63 Reset Value: undefined Bit 7:0 =D5.[7:0]: Channel 5 Data. CHANNEL 6 DATA REGISTER (D6R) R246 - Read/Write Register Page: 63 Reset Value: undefined Bit 7:0 =D6.[7:0]:Channel 6 Data CHANNEL 7 DATA REGISTER (D7R) R247 - Read/Write Register Page: 63 Reset Value: undefined

ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) CHANNEL 6 LOWER THRESHOLD REGISTER (LT6R) R248 - Read/Write Register Page: 63 Reset Value: undefined Bit 7:0 =LT6.[7:0]:Channel 6 Lower Threshold User-defined lower threshold value for Channel 6, to be compared with the conversion results. CHANNEL 7 LOWER THRESHOLD REGISTER (LT7R) R249 - Read/Write Register Page: 63 Reset Value: undefined Bit 7:0 =LT7.[7:0]:Channel 7 Lower Threshold. User-defined lower threshold value for Channel 7, to be compared with the conversion results. CHANNEL 6 UPPER THRESHOLD REGISTER (UT6R) R250 - Read/Write Register Page: 63 Reset Value: undefined Bit 7:0 =UT6.[7:0]: Channel 6 Upper Threshold value. User-defined upper threshold value for Channel 6, to be compared with the conversion results. CHANNEL 7 UPPER THRESHOLD REGISTER (UT7R) R251 - Read/Write Register Page: 63 Reset Value: undefined Bit 7:0 =UT7.[7:0]: Channel 7 Upper Threshold value User-defined upper threshold value for Channel 7, to be compared with the conversion results. COMPARE RESULT REGISTER (CRR) R252 - Read/Write Register Page: 63 Reset Value: 0000 1111 (0Fh) These bits are set by hardware and cleared by software. Bit 7 =C7U : Compare Reg 7 Upper threshold 0: Threshold not reached 1: Channel 7 converted data is greater than or equal to UT7R threshold register value. Bit 6 =C6U :Compare Reg 6Upper threshold 0: Threshold not reached 1: Channel 6 converted data is greater than or equal to UT6R threshold register value. Bit 5 =C7L :Compare Reg 7 Lower threshold 0: Threshold not reached 1: Channel 7 converted data is less than the LT7R threshold register value. Bit 4 =C6L :Compare Reg 6 Lower threshold 0: Threshold not reached 1: Channel 6 converted data is less than the LT6R threshold register value. Bit 3:0 = Reserved, returns “1” when read. Note: Any software reset request generated by writing to the AD_ICR, will also cause all the com- pare status bits to be cleared. UT6. UT6. UT6. UT6. UT6. UT6. UT6. UT6. UT7. UT7. UT7. UT7. UT7. UT7. UT7. UT7. C7U C6U C7L C6L 1 1 1 1

ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) CONTROL LOGIC REGISTER (CLR) The Control Logic Register (CLR) manages the A/D converter logic. Writing to this register will cause the current conversion to be aborted and the autoscan logic to be re-initialized. CONTROL LOGIC REGISTER (CLR) R253 - Read/Write Register Page: 63 Reset Value: 0000 0000 (00h) Bit 7:5 =SC[2:0]: Start Conversion Address. These 3 bits define the starting analog input chan- nel (Autoscan mode). The first channel addressed by SC[2:0] is converted, then the channel number is incremented for the successive conversion, until channel 7 (111) is converted. When SC2, SC1 and SC0 are all set, only channel 7 will be converted. Bit 4 =EXTG : External Trigger Enable. This bit is set and cleared by software. 0: External trigger disabled. 1: External trigger enabled. Allows a conversion sequence to be started on the subsequent edge of the external signal applied to the EXTRG pin (when enabled as an Alternate Function). Bit 3 =INTG : Internal Trigger Enable. This bit is set and cleared by software. 0: Internal trigger disabled. 1: Internal trigger enabled. Allows a conversion se- quence to be started, synchronized by an inter- nal signal (On-chip Event signal) from a Multi- function Timer peripheral. Both External and Internal Trigger inputs are inter- nally ORed, thus avoiding Hardware conflicts; however, the correct procedure is to enable only one alternate synchronization input at a time. Note:The effect of either synchronization mode is to set the START/STOP bit, which is reset by hard- ware when in SINGLE mode, at the end of each sequence of conversions. Requirements: The External Synchronisation In- put must receive a low level pulse longer than an INTCLK period and, for both External and On-Chip Event synchronisation, the repetition period must be greater than the time required for the selected sequence of conversions. Bit 2 =POW : Power Up/Power Down. This bit is set and cleared by software. 0: Powerdown mode: all power-consuming logic is disabled, thus selecting a low power idle mode. 1: Power up mode: the A/D converter logic and an- alog circuitry is enabled. Bit 1 =CONT :Continuous/Single. 0: Single Mode: a single sequence of conversions is initiated whenever an external (or internal) trigger occurs, or when the ST bit is set by soft- ware. 1: Continuous Mode: the first sequence of conver- sions is started, either by software (by setting the ST bit), or by hardware (on an internal or ex- ternal trigger, depending on the setting of the INTG and EXTG bits); a continuous conversion sequence is then initiated. Bit 0 =ST : Start/Stop. 0: Stop conversion. When the A/D converter is running in Single Mode, this bit is hardware re- set at the end of a sequence of conversions. 1: Start a sequence of conversions. SC2 SC1 SC0 EXT G INTG POW CON T ST

ST90158 - EIGHT-CHANNEL ANALOG TO DIGITAL CONVERTER (A/D) ANALOG TO DIGITAL CONVERTER (Cont’d) INTERRUPT CONTROL REGISTER (AD_ICR) R254 - Read/Write Register Page: 63 Reset Value: 0000 1111 (0Fh) Bit 7 =ECV :End of Conversion. This bit is set by hardware after a group of conver- sions is completed. It must be reset by the user, before returning from the Interrupt Service Rou- tine. Setting this bit by software will cause a soft- ware interrupt request to be generated. 0: No End of Conversion event occurred 1: An End of Conversion event occurred Bit 6 =AWD : Analog Watchdog. This is automatically set by hardware whenever ei- ther of the two monitored analog inputs goes out of bounds. The threshold values are stored in regis- ters F8h and FAh for channel 6, and in registers F9h and FBh for channel 7 respectively. The Com- pare Result Register (CRR) keeps track of the an- alog inputs exceeding the thresholds. The AWD bit must be reset by the user, before re- turning from the Interrupt Service Routine. Setting this bit by software will cause a software interrupt request to be generated. 0: No Analog Watchdog event occurred 1: An Analog Watchdog event occurred Bit 5 =ECI: End of Conversion Interrupt Enable. This bit masks the End of Conversion interrupt re- quest. 0: Mask End of Conversion interrupts 1: Enable End of Conversion interrupts Bit 4 =AWDI : Analog Watchdog Interrupt Enable. This bit masks or enables the Analog Watchdog interrupt request. 0: Mask Analog Watchdog interrupts 1: Enable Analog Watchdog interrupts Bit 3 = Reserved. Bit 2:0 =PL[2:0]:A/D Interrupt Priority Level. These three bits allow selection of the Interrupt pri- ority level for the A/D. INTERRUPT VECTOR REGISTER (AD_IVR) R255 - Read/Write Register Page: 63 Reset Value: xxxx xx10 (x2h) Bit 7:2 =V[7:2]: A/D Interrupt Vector. This vector should be programmed by the User to point to the first memory location in the Interrupt Vector table containing the starting addresses of the A/D interrupt service routines. Bit 1 =W1 : Word Select. This bit is set and cleared by hardware, according to the A/D interrupt source. 0: Interrupt source is the Analog Watchdog, point- ing to the lower word of the A/D interrupt service block (defined by V[7:2]). 1:Interrupt source is the End of Conversion inter- rupt, thus pointing to the upper word. Note: When two requests occur simultaneously, the Analog Watchdog Request has priority over the End of Conversion request, which is held pending. Bit 0 = Reserved. Forced by hardware to 0. ECV AWD ECI AWDI X PL2 PL1 PL0 V7 V6 V5 V4 V3 V2 W1 0

ST90158 - ELECTRICAL CHARACTERISTICS

10 ELECTRICAL CHARACTERISTICS

This product contains devices to protect the inputs against damage due to high static voltages, how- ever it is advisable to take normal precaution to avoid application of any voltage higher than the specified maximum rated voltages. For proper operation it is recommended that V I and VO be higher than VSS and lower than VDD . Reliability is enhanced if unused inputs are con- nected to an appropriate logic voltage level (V DD or VSS ). Power Considerations.The average chip-junc- tion temperature, TJ, in Celsius can be obtained from: T J=TA + PD x RthJA Where: TA = Ambient Temperature. RthJA = Package thermal resistance (junction-to ambient). PD =P INT +P PORT . PINT =I DD xV DD (chip internal power). PPORT =Port power dissipation determined by the user) ABSOLUTE MAXIMUM RATINGS Note: Stresses above those listed as “absolute maximum ratings“ may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. All voltages are referenced to VSS PACKAGE THERMAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS Note 1.Operating temperature 0-70°C Note 2.1MHz when A/D is used Symbol Parameter Value Unit VDD Supply Voltage – 0.3 to 7.0 V AV DD A/D Converter Analog Reference V DD -0.3 to VDD + 0.3 V AV SS A/D Converter VSS VSS VI Input Voltage – 0.3 to V DD +0.3 V VAIN Analog Input Voltage (A/D Converter) VSS -0.3 to VDD + 0.3 V SSA -0.3 to VDDA + 0.3 V VO Output Voltage – 0.3 to V DD +0.3 V TSTG Storage Temperature – 55 to + 150 °C IINJ Pin Injection Current Digital and Analog Input -5 to +5 mA Maximum Accumulated Pin injection Current in the device -50 to +50 mA Symbol Parameter Package Value Unit RthJA Thermal junction to ambient TQFP80 40 °C/WPQFP80 40 Symbol Parameter Value UnitMin. Max. T A Operating Temperature -40 85 °C V DD Operating Supply Voltage (ROM) Operating Supply Voltage (OTP) Operating Supply Voltage (OTP Low Voltage version) 2.7 4.5 2.85 (1) 5.5 5.5 3.15 (1) V fINTCLK Internal Clock Frequency @ 4.5V - 5.5V Internal Clock Frequency @ 2.7V - 3.3V (ROM) Internal Clock Frequency @ 2.85V - 3.15V (OTP Low Voltage version) 0(2) MHz

ST90158 - ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS (VDD =5 V± 10%, TA = -40°C+8 5 °C, unless otherwise specified)(1) Note 1:All I/O Ports are configured in bidirectional weak pull-up mode with no DC load external clock pin (OSCIN) is driven by square wave external clock. No peripheral working. Note 2:VDD =3 V ±10% V ILMAX = 0.4 V (TTL and Schmitt trigger). Symbol Parameter Test Conditions Value UnitMin. Typ. Max. VIHCK Clock Input High Level External Clock 0.7 V DD VDD + 0.3 V VILCK Clock Input Low Level External Clock – 0.3 0.3 V DD V VIH Input High Level TTL 2.0 V DD + 0.3 V CMOS 0.7 V DD VDD + 0.3 V Schmitt Trigger 0.7 V DD VDD + 0.3 V V IL Input Low Level CMOS – 0.3 0.3 V DD V Schmitt Trigger – 0.3 0.8 (2) V VIHRS RESET Input High Level 0.7 V DD VDD + 0.3 V VILRS RESET Input Low Level –0.3 0.3 V DD V VHYRS RESET Input Hysteresis 0.3 1.5 V VOH Output High Level Push Pull, Iload = – 0.8mA V DD – 0.8 V VOL Output Low Level Push Pull or Open Drain, Iload = 1.6mA 0.4 V IWPU Weak Pull-up Current Bidirectional Weak Pull-up, VOL = 0V – 50 – 200 – 420 µA ILKIO I/O Pin Input Leakage Input/Tri-State, 0V < VIN <V DD –1 0 +1 0 µA ILKRS RESET Pin Input Leakage 0V < V IN <V DD –3 0 +3 0 µA ILKA/D A/D Conv. Input Leakage – 3 + 3 µA ILKAP Active Pull-up Input Leakage 0V < VIN < 0.8V – 10 + 10 µA ILKOS OSCIN Pin Input Leakage 0V < V IN <V DD ±3 µA

ST90158 - ELECTRICAL CHARACTERISTICS AC TEST CONDITIONS AC ELECTRICAL CHARACTERISTICS (VDD =5 V± 10%, TA = -40°C+8 5 °C, INTCLK = 16 MHz unless otherwise specified)1 Note 1:All I/O Ports are configured in bidirectional weak pull-up mode with no DC load, external clock pin (OSCIN) is driven by square wave external clock. Note 2:TA =2 5°C. At TA 85 °C the max. value is 25µA. (VDD =3 V± 10%, TA =0 °C+7 0 °C, , INTCLK = 14 MHz unless otherwise specified) Note 1:VDD =3 V±5% Symbol Parameter INTCLK ROM devices OTP devices Unit Typ. Max. Typ. Max. IDDRUN Run Mode Current, PLL on 16 MHz 32 34 50 55 mA IDDWFI WFI Mode Current, PLL on 16 MHz 11 12 16 18 mA IDDLPWFI Low Power WFI Mode Current 4 MHz/32 1.0 1.2 1.3 1.6 mA IHALT HALT Mode Current2 31 03 1 0 µA Symbol Parameter INTCLK ROM devices OTP LV devices (1) Unit Typ. Max. Typ. Max. IDDRUN Run Mode Current, PLL on 14 MHz 13 14.5 21 23.5 mA IDDWFI WFI Mode Current, PLL on 14 MHz 5 6.5 7 8.5 mA IDDLPWFI Low Power WFI Mode Current 4 MHz/32 0.3 0.4 0.4 0.5 mA IHALT HALT Mode Current 2 5 2 5 µA

ST90158 - ELECTRICAL CHARACTERISTICS EXTERNAL BUS TIMING TABLE (VDD =5 V± 10%, TA = -40°C+8 5 °C, Cload = 50pF, INTCLK = 16MHz, unless otherwise specified) Note:The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period, prescale value and number of wait cycles inserted. The values in the right hand two columns show the timing minimum and maximum for an external clock at 24 MHz divided by 2, prescaler value of zero and zero wait status. Legend : Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2; 2*OSCIN period when OSCIN is divided by 2; OSCIN period / PLL factor when the PLL is enabled TckH = INTCLK high pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN high pulse width) TckL = INTCLK low pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN low pulse width) P = clock prescaling value (=PRS; division factor = 1+P) Wa = wait cycles on AS; = max (P, programmed wait cycles in EMR2, requested wait cycles with WAIT) Wd = wait cycles on DS; = max (P, programmed wait cycles in WCR, requested wait cycles with WAIT) N ° Symbol Parameter Value (Note) UnitFormula Min. Max.

1 TsA (AS) Address Set-up Time before AS ↑ Tck*Wa+TckH-9 23 ns

2 ThAS (A) Address Hold Time after AS ↑ TckL-4 28 ns

3 TdAS (DR) AS ↑ to Data Available (read) Tck*(Wd+1)+3 65 ns

4 TwAS AS Low Pulse Width Tck*Wa+TckH-5 27 ns

5 TdAz (DS) Address Float to DS ↓ 00 n s

6 TwDS DS Low Pulse Width Tck*Wd+TckH-5 27 ns

7 TdDSR (DR) DS ↓ to Data Valid Delay (read) Tck*Wd+TckH+4 35 ns

8 ThDR (DS) Data to DS ↑ Hold Time (read) 7 7 ns

9 TdDS (A) DS ↑ to Address Active Delay TckL+11 43 ns

10 TdDS (AS) DS ↑ to AS↓ Delay TckL-4 28 ns

11 TsR/W (AS) R/W Set-up Time before AS ↑ Tck*Wa+TckH-17 15 ns

12 TdDSR (R/W) DS ↑ to R/W and Address Not Valid Delay TckL-1 31 ns

13 TdDW (DSW) Write Data Valid to DS ↓ Delay -16 -16 ns

14 TsD(DSW) Write Data Set-up before DS ↑ Tck*Wd+TckH-16 16 ns

15 ThDS (DW) Data Hold Time after DS ↑ (write) TckL-3 29 ns

16 TdA (DR) Address Valid to Data Valid Delay (read) Tck*(Wa+Wd+1)+TckH-7 86 ns

17 TdAs (DS) AS ↑ to DS↓ Delay TckL-6 26 ns

ST90158 - ELECTRICAL CHARACTERISTICS EXTERNAL BUS TIMING

ST90158 - ELECTRICAL CHARACTERISTICS EXTERNAL INTERRUPT TIMING TABLE (VDD =5 V± 10%, TA =- 4 0°C +85°C, Cload = 50pF, INTCLK = 12MHz, Push-pull output configuration, un- less otherwise specified) Note: The value left hand two columns show the formula used to calculate the timing minimum or maximum from the oscillator clock period, prescale value and number of wait cycles inserted. The value right hand two columns show the timing minimum and maximum for an external clock at 24 MHz divided by 2, prescale value of zero and zero wait status. EXTERNAL INTERRUPT TIMING N ° Symbol Parameter Value (Note) UnitOSCIN Divided b y2M i n . OSCIN Not Divided by 2 Min. Min. Max. 1T w L R Low Level Minimum Pulse Width in Rising Edge Mode 2TpC+12 TpC+12 95 ns 2T w H R High Level Minimum Pulse Width in Rising Edge Mode 2TpC+12 TpC+12 95 ns 3T w H F High Level Minimum Pulse Width in Falling Edge Mode 2TpC+12 TpC+12 95 ns 4T w L F Low Level Minimum Pulse Width in Falling Edge Mode 2TpC+12 TpC+12 95 ns

ST90158 - ELECTRICAL CHARACTERISTICS SPI TIMING TABLE (VDD =5 V± 10%, TA = -40°C+8 5 °C, Cload = 50pF, INTCLK = 12MHz, Output Alternate Function set as Push-pull) Note: TpC is the OSCIN Clock period. SPI TIMING N ° Symbol Parameter Value UnitMin. Max.

1 TsDI Input Data Set-up Time 100 ns

2 ThDI (1) Input Data Hold Time 1/2 TpC+100 ns

3 TdOV SCK to Output Data Valid 100 ns

4 ThDO Output Data Hold Time -20 ns

5 TwSKL SCK Low Pulse Width 300 ns

6 TwSKH SCK High Pulse Width 300 ns

ST90158 - ELECTRICAL CHARACTERISTICS WATCHDOG TIMING TABLE (VDD =5 V ± 10%, TA = -40°C+8 5 °C, Cload = 50pF, INTCLK = 12MHz, Push-pull output configuration, unless otherwise specified ) WATCHDOG TIMING N ° Symbol Parameter Values Unit Min. Max.

1 TwWDOL WDOUT Low Pulse Width 620 ns

2 TwWDOH WDOUT High Pulse Width 620 ns

3 TwWDIL WDIN High Pulse Width 350 ns

4 TwWDIH WDIN Low Pulse Width 350 ns

ST90158 - ELECTRICAL CHARACTERISTICS A/D EXTERNAL TRIGGER TIMING TABLE A/D EXTERNAL TRIGGER TIMING N ° Symbol Parameter OSCIN Divided by 2 (2) OSCIN Not Divided by 2 (2) Value (3) Unit 1T w LOW External trigger pulse width 2 x Tpc Tpc 83 - ns 2T w HIGH External trigger pulse distance 2 x Tpc Tpc 83 - ns 3T w EXT External trigger active edges distance (1) 276n x Tpc 138n x Tpc n x 11.5 - µs 4T d STR EXTRG falling edge and first conversion start Tpc 3x Tpc .5 x Tpc 1.5 x Tpc 41.5 125 ns

ST90158 - ELECTRICAL CHARACTERISTICS A/D INTERNAL TRIGGER TIMING TABLE A/D INTERNAL TRIGGER TIMING N ° Symbol Parameter OSCIN Divided by 2 (2) OSCIN Not Divided by 2 (2) Value (3) Unit 1T w HIGH Internal trigger pulse width Tpc .5 x Tpc 41.5 - ns 2T w LOW Internal trigger pulse distance 6 x Tpc 3 x Tpc 250 - ns 3T w EXT Internal trigger active edges distance (1) 276n x Tpc 138n x Tpc n x 11.5 - µs 4T w STR Internal delay between INTRG rising edge and first conversion start Tpc 3 x Tpc .5 x Tpc 1.5 x Tpc 41.5 125 ns ST (start conversion bit) INTRG VR0A1401

ST90158 - ELECTRICAL CHARACTERISTICS A/D CHANNEL ENABLE TIMING TABLE Notes: 1. n = number of autoscanned channels (1 < n < 8) 2. Variable clock (Tpc = OSCIN clock period) 3. INTCLK = 12MHzA/D CHANNEL ENABLE TIMING N ° Symbol Parameter OSCIN Divided by 2 (2) OSCIN Not Divided by 2 (2) Value (3) Unit 1T w EXT CEn Pulse width (1) 276n x Tpc 138n x Tpc n x 11.5 - µs

ST90158 - ELECTRICAL CHARACTERISTICS A/D ANALOG SPECIFICATIONS (VDD = 4.5V TO 5.0 V) Notes: 1. “LSBs”, as used here, has a value of AVDD/256 2. Including sample time 3. It must be intended as the internal series resistance before the sampling capacitor 4. This is a typical expected value, but not a tested production parameter. If V(i) is the value of the i-th transition level (0 < i < 254), the performance of the A/D converter has been valued as follows: OFFSET ERROR= deviation between the actual V(0) and the ideal V(0) (=1/2 LSB) GAIN ERROR= deviation between the actual V(254) and the ideal V(254) (=AVCC-3/2 LSB) DNL ERROR= max {[V(i) - V(i-1)]/LSB - 1} INL ERROR= max {[V(i) - V(0)]/LSB - i} ABS. ACCURACY= overall max conversion error S/N ratio has been valued by sampling a sinusoidal input waveform and then calculating its Fast Fourier Transform. 2. Absolute accuracy: 2.5 LSB at 3V. Parameter Typical Minimum Maximum Units (1) Notes Conversion time 138 INTCLK (2) Sample time 87.51 INTCLK Power-up time 60 µs Resolution 8 8 bits Monotonicity GUARANTEED No missing codes GUARANTEED Zero input reading 00 Hex Full scale reading FF Hex Offset error .5 1 LSBs (1,4) Gain error .5 1 LSBs (4) Diff. Non Linearity ±.3 ±.2 ±.5 LSBs (4) Int. Non Linearity 1 LSBs (4) Absolute Accuracy 1 LSBs (4)(5) A VCC /AVSS Resistance 13.5 16 11 K Ω Input Resistance 12 8 15 K Ω (3) Hold Capacitance 30 pF Input Leakage ±3 µA

ST90158 - ELECTRICAL CHARACTERISTICS MULTIFUNCTION TIMER UNIT EXTERNAL TIMING TABLE Notes: 1. n = 1 if the input is rising OR falling edge sensitive n = 3 if the input is rising AND falling edge sensitive 2. In Autodiscrimination mode 3. Variable clock ( Tpc = OSCIN period ) 4. INTCLK = 12 MHz MULTIFUNCTION TIMER UNIT EXTERNAL TIMING N ° Symbol Parameter OSCIN Divided by 2 (3) OSCIN Not Divided by 2 (3) Value (4) Unit Note Min. Max. 1T w CTW External clock/trigger pulse width 2n x Tpc n x Tpc n x 83 - ns 1 2T w CTD External clock/trigger pulse distance 2n x Tpc n x Tpc n x 83 - ns 1 3T w AED Distance between two active edges 6 x Tpc 3 x Tpc 249 - ns 4T w GW Gate pulse width 12 x Tpc 6 x Tpc 498 - ns 5T w LBA Distance between TINB pulse edge and the following TINA pulse edge 2xT p c T p c 8 3 - n s 2 6T w LAB Distance between TINA pulse edge and the following TINB pulse edge 00 - n s 2 7T w AD Distance between two TxINA pulses 0 0 - ns 2 8T w OWD Minimum output pulse width/distance 6 x Tpc 3 x Tpc 249 - ns

ST90158 - ELECTRICAL CHARACTERISTICS SCI TIMING TABLE (VDD =5 V± 10%, TA =-4 0°C to +85°C, Cload = 50pF, INTCLK = 12MHz, Output Alternate Function set as Push-pull) Note: FCK = 1/TCK SCI TIMING N ° Symbol Parameter Condition Value UnitMin. Max. FRxCKIN Frequency of RxCKIN 1 x mode F CK /8 Hz 16 x mode F CK /4 Hz Tw RxCKIN RxCKIN shortest pulse 1 x mode 4 T CK s 16 x mode 2 T CK s FTxCKIN Frequency of TxCKIN 1 x mode F CK /8 Hz 16 x mode F CK /4 Hz Tw TxCKIN TxCKIN shortest pulse 1 x mode 4 T CK s 16 x mode 2 T CK s 1T s DS DS (Data Stable) before rising edge of RxCKIN 1 x mode reception with RxCKIN T PC /2 ns 2T d D1 TxCKIN to Data out delay Time1 x mode transmission with external clock C load <100pF 2.5 TPC ns 3T d D2 CLKOUT to Data out delay Time 1 x mode transmission with CLKOUT 350 ns

11 GENERAL INFORMATION

11.1 PACKAGE MECHANICAL DATA

Figure 89. 80-Pin Thin Plastic Quad Flat Package

ST90158 - GENERAL INFORMATION 80-PIN CERAMIC QUAD FLAT PACKAGE

11.3 ORDERING INFORMATION

A 3.24 0.128 A1 0.20 0.008 D3 18.40 0.724 E3 12.00 0.472 e 0.80 0.031 G2 1.06 0.042 L 0.35 0.80 0.014 0.031 Number of Pins N8 0 CQFP080 Part Number Program Memory (Bytes) RAM (Bytes) Temp. Range Operating Supply Package ST90135M4Q6 16K ROM 512 -40°C +85°C 5V @ 16MHz 3V @ 14 MHz PQFP80 ST90135M5Q6 24K ROM 768 ST90135M6Q6 32K ROM 1K ST90158M7Q6 48K ROM 1.5K ST90158M9Q6 64K ROM 2KST90158M9T1 0 °C +70°C 3V @ 14 MHz TQFP80 ST90E158M9G0 64K EPROM 2K + 25 °C 5V @ 16MHz CQFP80-W ST90E158M9LVG0 3V @ 14 MHz CQFP80-W ST90T158M9Q6 64K OTP 2K -40°C +85°C 5V @ 16MHz PQFP80 ST90T158M9LVQ1 0°C +70°C 3V @ 14 MHz PQFP80 ST90T158M9LVT1 TQFP80 ST90R158Q6 ROMless 2K -40 °C +85°C 5V @ 16MHz PQFP80 ST90R158T1 ROMless 2K 0 °C +70°C 3V @ 14MHz TQFP80

ST90158 - GENERAL INFORMATION Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics  2000 STMicroelectronics - All Rights Reserved. Purchase of I 2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http:// www.st.com