ST8024_06 STMICROELECTRONICS | Alldatasheet
Document overview
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- PDF pages: 30
Technical content
Datasheet sections
- 1 Diagram
- 2 Pin configuration
- 3 Maximum ratings
- 4 Electrical characteristics
- 5 Functional description
- 5.1 Power supply
- 5.2 Voltage supervisor
- 5.2.1 Without external divider on pin PORADJ
- 5.2.2 With an external divider on pin PORADJ
- 5.2.3 Application examples
- 5.3 Clock circuitry
- 5.4 I/O Transceivers
- 5.5 Inactive mode
- 5.6 Activation sequence
- 5.7 Active mode
- 5.8 Deactivation sequence
- 5.10 Fault detection
- 6 Application
- 7 Package mechanical data
- 8 Revision history
■ Designed to be compatible with the NDS conditional access system ■ IC card interface ■ 3 or 5V supply for the IC (VDD and GND) ■ Three specifically protected half-duplex bi- directional buffered I/O lines to card contacts C4, C7 and C8 ■ DC/DC converter for VCC generation separately powered from a 5 V ± 20% supply DDP AND PGND) ■ 3 or 5V ±5% regulated card supply voltage CC) with appropriate decoupling has the following capabilities: –I CC < 80mA at VDDP = 4 to 6.5V – Handles current spikes of 40nA up to 20MHz – Controls rise and fall times – Filtered overload detection at approximately 120mA ■ Thermal and short-circuit protection on all card contacts ■ Automatic activation and deactivation sequences; initiated by software or by hardware in the event of a short-circuit, card take-off, overheating, V DD or VDDP drop-out ■ Enhanced ESD protection on card side (>6 kV) ■ 26MHz integrated crystal oscillator ■ Clock generation for cards up to 20MHz (divided by 1, 2, 4 or 8 through CLKDIV1 and CLKDIV2 signals) with synchronous frequency changes ■ Non-inverted control of RST via pin RSTIN ■ ISO 7816, GSM11.11 and EMV (payment systems) compatibility ■ Supply supervisor for spike-killing during power-on and power-off and power-on reset (threshold fixed internally or externally by a resistor bridge) ■ Built-in debounce on card presence contacts ■ One multiplexed status signal off
Description
The ST8024 is a complete low cost analog interface for asynchronous 3V and 5V smart cards. It can be placed between the card and the microcontroller with few external components to perform all supply protection and control functions. ST8024 is a direct replacement of ST8004. Main applications are: smartcard readers for Set Top Box, IC card readers for banking, identification, Pay TV. SO-28 TSSOP28 Order codes Part number Temperature range Package Packaging ST8024CDR -25 to 85 °C SO-28 (T ape & Reel) 1000 parts per reel ST8024CTR -25 to 85 °C TSSOP28 (Tape & Reel) 1000 parts per reel
1 Diagram
Figure 1. Block diagram
2 Pin configuration
Figure 2. Pin connections Table 1. Pin description
1 CLKDIV1 Control of CLK Frequency
2 CLKDIV2 Control of CLK Frequency
35 V / 3 V
4 PGND Power Ground for Step-Up converter
10 PRES Card Presence Input (Active High)
11 I/O Data Line to and from card (C7) (internal 11k Ω pull-up resistor connected to VCC)
12 AUX2 Auxiliary line to and from card (C8) (internal 11k Ω pull-up resistor connected to VCC)
13 AUX1 Auxiliary line to and from card (C4) (internal 11k Ω pull-up resistor connected to VCC)
14 CGND Ground for card signal (C5)
15 CLK Clock to card (C3)
16 RST Card Reset (C2)
18 V THSEL Deactivation threshold selector pin (under voltage lock-out)
19 CMDVCC Start activation sequence input (Active Low)
20 RSTIN Card Reset Input from MCU
21 V DD Supply Voltage
22 GND Ground
23 OFF Interrupt to MCU (active Low)
24 XTAL1 Crystal or external clock input
25 XTAL2 Crystal connection (leave this pin open if external clock is used)
26 I/OUC MCU data I/O line (internal 11k Ω pull-up resistor connected to VDD)
27 AUX1UC Non-inverting Receiver Input (internal 11k Ω pull-up resistor connected to VDD)
28 AUX2UC Non-inverting Receiver Input (internal 11k Ω pull-up resistor connected to VDD)
3 Maximum ratings
occur. Functional operation under these conditions is not implied. Note: 1 All card contacts are protected against any short with any other card contact.
2 Method 3015 (HBM, 1500 Ω, 100 pF) 3 positive pulses and 3 negative pulses on each pin
Table 2. Absolute maximum ratings Table 3. Thermal data Table 4. Recommended operating conditions
4 Electrical characteristics
Table 5. Electrical characteristics over recommended operating condition (VDD = 3.3V, VDDP =
Table 6. Step-up Converter (VDD = 3.3V, VDDP = 5V, fXT AL = 10MHz, unless otherwise noted. Table 7. Card supply voltage characteristics (VDD = 3.3V, VDDP = 5V, fXT AL = 10MHz,
Table 8. Crystal connection (pins XTAL1 and XTAL2) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, Table 9. Data Lines (PINS I/O, I/OUC, AUX1, AUX2, AUX1UC AND AUX2UC) (VDD = 3.3V, VDDP = Table 10. Data lines to card reader (pins I/O, AUX1 AND AUX2 with integrated 11k Ω Pull-up
Table 11. Data lines to microcontroller (pins I/O UC, AUX1UC AND AUX2UC with integrated 11kΩ Pull-up resistor to VDD (VDD = 3.3V, VDDP = 5V , fXTAL = 10MHz, unless otherwise noted. Table 12. Internal oscillator (VDD = 3.3V, VDDP = 5V, fXT AL = 10MHz, unless otherwise noted.Typical
Table 13. Reset output to card reader (pin RST) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless Table 14. Clock output to card reader (pin CLK) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless
Table 15. Control inputs (PINS CLKDIV1, CLKDIV2, CMDVCC , RSTIN AND 5V/3V Table 16. Card presence inputs (PINS PRES AND PRES) Table 17. Interrupt Output (PIN OFF NMOS Drain With Integrated 20 kΩ PULL-UP Resistor To Table 18. Protection And Limitation (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise
at the moment of measurement.
2 To meet these specifications, pin V CC should be decoupled to CGND using two ceramic
multilayer capacitors of low ESR both with values of 100 nF and 100 nF (see Figure 10.). 3 Permitted capacitor values are 100 + 100 nF , or 220 nF . 4 Transition time and duty factor definitions are shown in Figure 3.; δ = t1/(t1+ t2).
5 Pin CMDVCC is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2
present if at least one of the inputs PRES or PRES is active. Figure 3. Definition of output and input transition times Table 19. Timing (VDD = 3.3V , VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are
Functional description ST8024
5 Functional description
Throughout this document it is assumed that the reader is familiar with ISO7816 terminology.
5.1 Power supply
The supply pins for the IC are VDD and GND. VDD should be in the range of 2.7 to 6.5 V. All signals interfacing with the system controller are referred to VDD, therefore VDD should also supply the system controller. All card reader contacts remain inactive during power-on or power-off. The internal circuits are maintained in the reset state until V DD reaches Vth2 +Vhys2 and for the duration of the internal Power-on reset pulse, tW (see Figure 4.). When VDD falls below Vth2, an automatic deactivation of the contacts is performed. A DC/DC converter is incorporated to generate the 5 or 3 V card supply voltage (VCC). The DC/DC converter should be supplied separately by VDDP and PGND. Due to the possibility of large transient currents, the two 100 nF capacitors of the DC/DC converter should be located as near as possible to the IC and have an ESR less than 100 mΩ. The DC/DC converter functions as a voltage doubler or a voltage follower according to the respective values of V CC and VDDP (both have thresholds with a hysteresis of 100 mV). The DC/DC converter function changes as follows: V CC = 5 V and VDDP > 5.8 V; voltage follower VCC = 5 V and VDDP < 5.7 V; voltage doubler VCC = 3 V and VDDP > 4.1 V; voltage follower VCC = 3 V and VDDP < 4.0 V; voltage doubler. Supply voltages VDD and VDDP may be applied to the IC in any sequence. After powering the device, OFF remains LOW until CMDVCC is set HIGH. During power off, OFF falls LOW when VDD is below the falling threshold voltage.
5.2 Voltage supervisor
5.2.1 Without external divider on pin PORADJ
The voltage supervisor surveys the VDD supply. A defined reset pulse of approximately 8ms (tW) is used internally to keep the IC inactive during power-on or power-off of the VDD supply (see Figure 4.). As long as VDD is less than Vth2 + Vhys2, the IC remains inactive whatever the levels on the command lines. This state also lasts for the duration of tW after VDD has reached a level higher than Vth2 + Vhys2. When VDD falls below Vth2, a deactivation sequence of the contacts is performed.
Figure 4. Voltage supervisor
5.2.2 With an external divider on pin PORADJ
where Vbridge = 1.25 V typ. and Vhys(ext) = 60 mV typ.
- The reset pulse width tW is doubled to approximately 16 ms.
when the voltage on pin PORADJ exceeds 1 V. current on pin PORADJ does not cause inaccuracy of the bridge voltage.
5.2.3 Application examples
5.3 Clock circuitry
crystal operating at up to 26 MHz connected between pins XTAL1 and XTAL2. is made via inputs CLKDIV1 and CLKDIV2 (see Table 20).
instant of change have the correct width. CLK is guaranteed between 45 and 55% of the clock period. Figure 5. and Figure 6.
5.4 I/O Transceivers
equal to VDD. The first side of the transceiver to receive a falling edge becomes the master. limited internally to 15 mA and the maximum frequency on these lines is 1 MHz. Table 20. Clock frequency selection
- The status of pins CLKDIV1 and CLKDIV2 must not be changed simultaneously; a delay of 10 ns minimum
between changes is needed; the minimum duration of any state of CLK is eight periods of XTAL1.
5.5 Inactive mode
– The internal oscillator is running at its low frequency.
5.6 Activation sequence
check the presence of a card using the signals OFF and CMDVCC as shown in Table 21.
- CMDVCC is pulled LOW and the internal oscillator changes to its high frequency (t0).
- The voltage doubler is started (between t0 and t1).
- VCC rises from 0 to 5 V (or 3 V) with a controlled slope (t2 = t1 + 1.5 x T) where T is
64 times the period of the internal oscillator (approximately 25 µs).
- I/O, AUX1 and AUX2 are enabled (t3 = t1 + 4T) (these were pulled LOW until this
- CLK is applied to the C3 contact of the card reader (t4).
- RST is enabled (t5 = t1 + 7T).
- Reset RSTIN LOW between t3 and t5; CLK will start at this moment.
- RST remains LOW until t5, when RST is enabled to be the copy of RSTIN.
- After t5, RSTIN has no further affect on CLK; this allows a precise count of CLK
may be set HIGH in order to obtain an Answer To Request (ATR) from the card. Table 21. Card presence indicator
5.7 Active mode
exchanged between the card and the microcontroller via the I/O lines. internal non-volatile memory).
5.8 Deactivation sequence
- CLK is held LOW (t12 = t10 + 0.5 x T) where T is 64 times the period of the internal
oscillator (approximately 25 µs).
- I/O, AUX1 and AUX2 are pulled LOW (t13 = t10 + T).
- VCC starts to fall towards zero (t14 = t10 + 1.5 x T).
- The deactivation sequence is complete at tde, when VCC reaches its inactive state.
- VUP falls to zero (t15 = t10 + 5T) and all card contacts become low-impedance to GND;
I/OUC, AUX1UC and AUX2UC remain at VDD (pulled-up via a 11 kΩ resistor).
- The internal oscillator returns to its lower frequency.
Figure 7. Deactivation sequence
5.9 V CC Generator
nF capacitor with the same ESR should be tied to CGND near card reader contact C1.
5.10 Fault detection
again if a card is present). the PRES signals at card insertion or withdrawal. goes HIGH only at the end of the debounce time. the first true/false transition on PRES or PRES and output OFF goes LOW. Figure 8. Behavior of OFF , CMDVCC, PRES and VCC
Figure 9. Emergency deactivation sequence (card extraction)
6 Application
Figure 10. Application diagram (1) These capacitors must be of the low ESR-type and be placed near the IC (within 100 mm). (2) ST8024 and the microcontroller must use the same V DD supply. (3) Make short, straight connections between CG ND, C5 and the ground connection to the capacitor. (4) Mount one low ESR-type 100 nF capacitor close to pin V CC. (5) Mount one low ESR-type 100 nF capacitor close to C1 contact.
7 Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOP ACK is an ST trademark. ECOPACK specifications are available at: www.st.com
DIM. mm. inch A 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45˚ (typ.) D 17.70 18.10 0.697 0.713 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 16.51 0.650 F 7.40 7.60 0.291 0.300 L 0.50 1.27 0.020 0.050 S˚ ( m a x . ) SO-28 MECHANICAL DATA 0016023
DIM. mm. inch A 1.2 0.047 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 e 0.65 BSC 0.0256 BSC K0 ˚ 8 ˚0 ˚ 8 ˚ TSSOP28 MECHANICAL DATA 0128292B
DIM. mm. inch A 330 12.992 C 12.8 13.2 0.504 0.519 D 20.2 0.795 N 60 2.362 T 30.4 1.197 Ao 10.8 11.0 0.425 0.433 Bo 18.2 18.4 0.716 0.724 Ko 2.9 3.1 0.114 0.122 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 Tape & Reel SO-28 MECHANICAL DATA
DIM. mm. inch A 330 12.992 C 12.8 13.2 0.504 0.519 D 20.2 0.795 N 60 2.362 T 30.4 1.197 Ao 10.8 11.0 0.425 0.433 Bo 18.2 18.4 0.716 0.724 Ko 2.9 3.1 0.114 0.122 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 Tape & Reel SO-28 MECHANICAL DATA
DIM. mm. inch A 330 12.992 C 12.8 13.2 0.504 0.519 D 20.2 0.795 N 60 2.362 T 22.4 0.882 Ao 6.8 7 0.268 0.276 Bo 10.1 10.3 0.398 0.406 Ko 1.7 1.9 0.067 0.075 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 Tape & Reel TSSOP28 MECHANICAL DATA
8 Revision history
Table 22. Revision history 27-Jun-2006 5 Add package TSSOP28 and new template. 13-Dec-2006 6 The comment point 5 on page 22 has been removed.