ST8024

ST8024 STMICROELECTRONICS | Alldatasheet

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I 3 OR 5 V SUPPLY FOR THE IC (V DD AND GND) I THREE SPECIFICALLY PROTECTED HALF-DUPLEX BI-DIRECTIONAL BUFFERED I/O LINES TO CARD CONTACTS C4, C7 AND C8 I DC/DC CONVERTER FOR V CC GENERATION SEPARATELY POWERED FROM A 5 V ± 20% SUPPLY (VDDP AND PGND) I 3 OR 5 V ±5% REGULATED CARD SUPPLY VOLTAGE (V CC) WITH APPROPRIATE DECOUPLING HAS THE FOLLOWING CAPABILITIES: – I CC < 80 mA at VDDP = 4 to 6.5 V – HANDLES CURRENT SPIKES OF 40 nAs UP TO 20MHz – CONTROLS RISE AND FALL TIMES – FILTERED OVERLOAD DETECTION AT APPROXIMATELY 120 mA I THERMAL AND SHORT-CIRCUIT PROTECTION ON ALL CARD CONTACTS I AUTOMATIC ACTIVATION AND DEACTIVATION SEQUENCES; INITIATED BY SOFTWARE OR BY HARDWARE IN THE EVENT OF A SHORT-CIRCUIT, CARD TAKE-OFF, OVERHEATING, V DD OR VDDP DROP-OUT I ENHANCED ESD PROTECTION ON CARD SIDE (>6 kV) I 26 MHz INTEGRATED CRYSTAL OSCILLATOR I CLOCK GENERATION FOR CARDS UP TO

20 MHz (DIVIDED BY 1, 2, 4 OR 8

THROUGH CLKDIV1 AND CLKDIV2 SIGNALS) WITH SYNCHRONOUS FREQUENCY CHANGES I NON-INVERTED CONTROL OF RST VIA PIN RSTIN I ISO 7816, GSM11.11 AND EMV (PAYMENT SYSTEMS) COMPATIBILITY I SUPPLY SUPERVISOR FOR SPIKE-KILLING DURING POWER-ON AND POWER-OFF AND POWER-ON RESET (THRESHOLD FIXED INTERNALLY OR EXTERNALLY BY A RESISTOR BRIDGE) I BUILT-IN DEBOUNCE ON CARD PRESENCE CONTACTS I ONE MULTIPLEXED STATUS SIGNAL OFF

DESCRIPTION

The ST8024 is a complete low cost analog interface for asynchronous 3V and 5V smart cards. It can be placed between the card and the microcontroller with few external components to perform all supply protection and control functions. ST8024 is a direct replacement of ST8004. Main applications are: smartcard readers for Set Top Box, IC card readers for banking, identification, Pay TV. Table 1: Order Codes (*) Available on Request. Type Temperature Range Package Comments ST8024CD -25 to 85 °C SO-28 (Tube) 27 parts per tube / 12 tube per box ST8024CDR -25 to 85 °C SO-28 (Tape & Reel) 1000 parts per reel ST8024CTR (*) -25 to 85 °C TSSOP28 (Tape & Reel) 2500 parts per reel ST8024 SMARTCARD INTERFACE This is preliminary information on a new product now in development. Details are subject to change without notice. SOP TSSOP PRODUCT PREVIEW Rev. 1

Figure 1: Block Diagram

Figure 2: Pin Configuration Table 2: Pin Description PlN N° SYMBOL NAME AND FUNCTION

1 CLKDIV1 Control of CLK Frequency

2 CLKDIV2 Control of CLK Frequency

35 V / 3 V VCC selection pin.

4 PGND Power Ground for Step-Up converter

5 C1+ External Cap. for Step-Up converter

6 VDDP Power Supply for Step-Up converter

7 C1- External Cap. Step-Up converter

8 VUP Output of Step-Up converter

9P R E S Card Presence Input (Active Low)

10 PRES Card Presence Input (Active High)

11 I/O Data Line to and from card (C7) (internal 11kΩ pull-up resistor connected to V CC)

12 AUX2 Auxiliary line to and from card (C8) (internal 11k Ω pull-up resistor connected to V CC)

13 AUX1 Auxiliary line to and from card (C4) (internal 11k Ω pull-up resistor connected to V CC)

14 CGND Ground for card signal (C5)

15 CLK Clock to card (C3)

16 RST Card Reset (C2)

CC Supply Voltage for the card (C1)

18 PORADJ Deactivation threshold selector pin (under voltage lock-out)

19 CMDVCC Start activation sequence input (Active Low)

20 RSTIN Card Reset Input from MCU

21 VDD Supply Voltage

22 GND Ground

23 OFF Interrupt to MCU (active Low)

24 XTAL1 Crystal or external clock input

25 XTAL2 Crystal connection (leave this pin open if external clock is used)

26 I/OUC MCU data I/O line (internal 11kΩ pull-up resistor connected to V

DD)

27 AUX1UC Non-inverting Receiver Input (internal 11kΩ pull-up resistor connected to V DD)

28 AUX2UC Non-inverting Receiver Input (internal 11kΩ pull-up resistor connected to V DD)

Table 3: Absolute Maximum Ratings Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Note 1: All card contacts are protected against any short with any other card contact. Note 2: Method 3015 (HBM, 1500 Ω, 100 pF) 3 positive pulses and 3 negative pulses on each pin referenced to ground. Table 4: Thermal Data RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VDD, VDDP Supply Voltage -0.3 7 V Vn1 Voltage on pins XTAL1, XTAL2, 5V/3V, RSTIN, AUX2UC, AUX1UC, I/OUC, CLKDIV1, CLKDIV2, PORADJ, CMDVCC , PRES, PRES and OFF -0.3 VDD + 0.3 V Vn2 Voltage on card contact pins I/O, RST, AUX1, AUX2 and CLK -0.3 VCC + 0.3 V Vn3 Voltage on pins VUP, S1 and S2 9V ESD1 MIL-STD-883 class 3 on card contact pins, PRES and PRES (Note 1, 2) -6 6 kV ESD2 MIL-STD-883 class 2 on µC contact pins and RSTIN (Note 1, 2) -2 2 kV Symbol Parameter Condition Value Unit Rthj-amb Thermal Resistance Junction-ambient Temperature In free air 70 K/W Symbol Parameter Min. Typ. Max. Unit TA Temperature Range -25 85 °C

Table 5: Electrical Characteristics Over Recommended Operating Conditions (VDD = 3.3V, VDDP = 5V , fXTAL = 10MHz, unless otherwise noted. Typical values are to T a = 25°C) Table 6: Step-up Converter (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Supply Voltage 2.7 6.5 V VDDP Supply Voltage for the voltage doubler VCC = 5V; |ICC| < 80 mA 4.0 5 6.5 V VCC = 5V; |ICC| < 20 mA 3.0 6.5 IDD Supply Current Card Inactive 1.2 mA Card Active; fCLK = fXTAL; CL = 30pF 1.5 IDDP DC/DC converter Supply Current Inactive mode 0.1 mA Active mode; fCLK = fXTAL; CL = 30pF; |ICC| = 0 VCC = 5V; |ICC| = 80 mA 200 VCC = 3V; |ICC| = 65 mA 100 Vth2 Falling Threshold Voltage on VDD no external resistors at pin PORADJ; V DD level falling 2.35 2.45 2.55 V VHYS2 Hysteresis of Threshold Voltage Vth2 no external resistors at pin PORADJ 50 100 150 mV Vth(ext)rise External rising Threshold Voltage on VDD external resistor bridge at pin PORADJ; V DD level rising 1.18 1.21 1.24 V Vth(ext)fall External falling Threshold Voltage on VDD external resistor bridge at pin PORADJ; V DD level falling 1.12 1.15 1.18 V VHYS(ext) Hysteresis of Threshold Voltage Vth(ext) external resistor bridge at pin PORADJ 30 60 90 mV ∆VHYS(ext) Hysteresis of Threshold Voltage Vth(ext) variation with temperature external resistor bridge at pin PORADJ 0.25 mV/K tW Width of internal Power-On reset pulse no external resistor at pin PORADJ 4 8 12 ms external resistor bridge at pin PORADJ 8 16 24 IL Leakage current on pin PORADJ VPORADJ < 0.5 V -0.1 4 10 µA VPORADJ > 1.0 V -1 1 PTOT Total power dissipation Continuous operation; T a = -25 to 85°C 0.56 W Symbol Parameter Test Conditions Min. Typ. Max. Unit fCLK Clock Frequency Card active 2.2 3.2 MHz Vth(vd-vf) Threshold voltage for Step-up Converter to change to voltage follower 5 V card 5.2 5.8 6.2 V 3 V card 3.8 4.1 4.4 V UP(av) Output Voltage on pin VUP (average value) VCC = 5 V 5.2 5.7 6.2 V VCC = 3 V; VDDP = 3.3 V 3.5 3.9 4.3

Table 7: Card Supply Voltage Characteristics (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to T a = 25°C) (Note 1) Table 8: Crystal Connection (PINS XTAL1 AND XTAL2) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to T a = 25°C) Table 9: Data Lines (PINS I/O, I/OUC, AUX1, AUX2, AUX1UC AND AUX2UC) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to T a = 25°C) Symbol Parameter Test Conditions Min. Typ. Max. Unit CVCC External Capacitance on pin VCC Notes 2 and 3 80 220 nF VCC Card Supply Voltage (including ripple voltage) Card Inactive; |ICC| = 0 mA 5 and 3V card -0.1 0 0.1 V Card Inactive; |ICC| = 1 mA 5 and 3V card -0.1 0 0.3 Card Active; |ICC| < 80 mA 5 V card 4.75 5 5.25 Card Active; |ICC| < 65 mA 3 V card 2.85 3 3.15 Card Active; single current pulse IP =-100 mA; tp=2 µs 5 V card 4.65 5 5.25 Card Active; single current pulse IP =-100 mA; tp =2 µs 3 V card 2.76 3 3.20 Card active; current pulses, QP = 40 nAs 5 V card 4.65 5 5.25 3 V card 2.76 3 3.20 Card Active; current pulses QP =40 nAs with |ICC| < 200mA, tp < 400 ns 5 V card 4.65 5 5.25 3 V card 2.76 3 3.20 VCC (RIPPLE) (P-P) Ripple voltage on VCC (Peak to Peak value) fRIPPLE = 20 KHz to 200 MHz 350 mV |ICC| Card Supply Current V CC = 0 to 5V 80 mA VCC = 0 to 3V 65 VCC short circuit to GND 90 120 SR Slew Rate Slew up or down 0.08 0.15 0.22 V/µs Symbol Parameter Test Conditions Min. Typ. Max. Unit CXTAL1,2 External capacitance on pins XTAIL1, XTAIL2 Depends on type of crystal or resonator used 15 pF fXTAL Crystal Frequency 2 26 MHz fXTAL1 Frequency applied on pin XTAL1 02 6 M H z VIH High level input voltage on pin XTAIL1 0.7 VDD VDD+0.3 V VIL Low level input voltage on pin XTAIL1 -0.3 +0.3V DD V Symbol Parameter Test Conditions Min. Typ. Max. Unit tD(I/O-I/OUC), tD(I/OUC-I/O) I/O to I/OUC, I/OUC to I/O falling edge delay 200 ns tpu Active pull-up pulse width 100 ns fI/O(MAX) Maximum frequency on data lines 1M H z CI Input capacitance on data lines 10 pF

Table 10: Data Lines To Card Reader (PINS I/O, AUX1 AND AUX2 With Integrated 11 k Ω PULL-UP Resistor To V CC (VDD = 3.3V, VDDP = 5V , fXTAL = 10MHz, unless otherwise noted. Typical values are to T a = 25°C) Table 11: Data Lines To Microcontroller (PINS I/OUC, AUX1UC AND AUX2UC; With Integrated 11 kΩ PULL-UP Resistor To V DD) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Symbol Parameter Test Conditions Min. Typ. Max. Unit VO(inactive) Output Voltage Inactive mode NO LOAD 0 0.1 V IO(inactive)=1mA 0.3 IO(inactive) Output Current Inactive mode; pin grounded -1 mA VOH High Level Output Voltage No DC Load 0.9 V CC VCC+0.1 V 5 and 3 V cards; IOH < - 40µA 0.75 V CC VCC+0.1 |IOH| ≥ 10mA 0 0.4 VOL Low Level Output Voltage I OL = 1 mA 0 0.2 V IOL ≥ 15 mA V CC-0.4 V CC VIH High Level Input Voltage 1.5 V CC+0.3 V VIL Low Level Input Voltage 0.3 0.8 V |ILIH| High Level Input Leakage Current VIH = VCC 10 µA |IIL| Low Level Input Current V IL = 0 V 600 µA RPU Integrated pull-up resistor Pull-up resistor to V CC 91 1 1 3 k Ω tT(DI) Data Input transition time V IL max to VIH min 1.2 µs tT(DO) Data Output transition time V O = 0 to VCC; CL ≤ 80 pF; 10% to 90% 0.1 µs IPU Current when pull-up active V OH = 0.9VCC; CL = 80 pF -1 mA Symbol Parameter Test Conditions Min. Typ. Max. Unit VOH High Level Output Voltage 5 and 3 V card; I OH < − 40µA 0.75 V DD VDD+0.1 V No DC Load 0.9 V DD VDD+0.1 VOL Low Level Output Voltage I OL = 1 mA 0 0.3 V VIH High Level Input Voltage 0.7 V DD VDD+0.3 V VIL Low Level Input Voltage -0.3 0.3 V DD V |ILIH| High Level Input Leakage Current VIH = VDD 10 µA |IL| Low Level Input Current V IL = 0 V 600 µA RPU Internal pull-up resistance to VDD Pull-up resistor to VDD 91 1 1 3 k Ω tT(DI) Data Input transition time V IL(max) to VIH(min) 1.2 µs tT(DO) Data Output transition time V O = 0 to VDD; CL < 30 pF; 10% to 90% 0.1 µs IPU Current when pull-up active V OH = 0.9VDD; CL = 30 pF -1 mA

Table 12: Internal Oscillator (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Table 13: Reset Output To Card Reader (PIN RST) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to T a = 25°C) Table 14: Clock Output To Card Reader (PIN CLK) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to T a = 25°C) Table 15: Control Inputs (PINS CLKDIV1, CLKDIV2, CMDVCC , RSTIN AND 5V/3V (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to T a = 25°C) (Note Symbol Parameter Test Conditions Min. Typ. Max. Unit fOSC(INT) Frequency of internal oscillator Inactive mode 55 140 200 kHz Active mode 2.2 2.7 3.2 MHz Symbol Parameter Test Conditions Min. Typ. Max. Unit VO(inactive) Output Voltage in Inactive Mode IO(inactive) = 1 mA 0 0.3 V No Load 0 0.1 IO(inactive) Output Current Inactive mode; pin grounded 0 -1 mA tD(RSTIN-RST) RSTN to RST Delay RST Enable 2 µs VOL Low Level Output Voltage I OL = 200 µA 0 0.2 V IOL = 20 mA (current limit) V CC-0.4 V CC VOH High Level Output Voltage I OH = -200 µA 0.9V CC VCC V IOH = -20 mA (current limit) 0 0.4 tR, tF Rise and fall time C L = 100 pF; VCC = 5 or 3 V 0.1 µs Symbol Parameter Test Conditions Min. Typ. Max. Unit VO(inactive) Output Voltage in Inactive Mode IO(inactive) = 1 mA 0 0.3 V No Load 0 0.1 IO(inactive) Output Current CLK Inactive mode; pin grounded 0 -1 mA VOL Low Level Output Voltage I OL = 200 µA 0 0.3 V IOL = 70 mA (current limit) V CC-0.4 V CC VOH High Level Output Voltage I OH = -200 µA 0.9V CC VCC V IOH = -70 mA (current limit) 0 0.4 tR, tF Rise and fall time C L = 30 pF (Note 4) 16 ns δ Duty factor (except for fXTALS) CL = 30 pF (Note 4) 45 55 % SR Slew Rate Slew up or down; C L = 30 pF 0.2 V/ns Symbol Parameter Test Conditions Min. Typ. Max. Unit VIL Input Voltage LOW -0.3 0.3V DD V VIH Input Voltage HIGH 0.7V DD VDD V |ILIH| Input Leakage Current HIGH V IH = VDD 1µ A |ILIL| Input Leakage Current LOW V IL = 0 1 µA

Table 16: Card Presence Inputs (PINS PRES AND PRES ) (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to T a = 25°C) (Note Table 17: Interrupt Output (PIN OFF NMOS Drain With Integrated 20 k Ω PULL-UP Resistor To VDD); (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Table 18: Protection And Limitation (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Table 19: Timing (VDD = 3.3V, VDDP = 5V, fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) Note 1: All parameters remain within limits but are tested only statistically for the temperature range. When a parameter is sp ecified as a function of VDD or VCC it means their actual value at the moment of measurement. Note 2: To meet these specifications, pin VCC should be decoupled to CGND using two ceramic multilayer capacitors of low ESR both with values of 100 nF and 100 nF (see Fig.10). Note 3: Permitted capacitor values are 100 + 100 nF, or 220 nF. Note 4: Transition time and duty factor definitions are shown in Fig.3; δ = t 1/(t1+ t2). Note 5: Pin CMDVCC is active LOW; pin RSTIN is active HIGH; for CLKDIV1 and CLKDIV2 functions see Table 20. Note 6: Pin PRES is active LOW; pin PRES is active HIGH see Figs. 8 and 9; PRES has an integrated 1.25 µA current source to GND (PRES to VDD); the card is considered present if at least one of the inputs PRES or PRES is active. Symbol Parameter Test Conditions Min. Typ. Max. Unit VIL Input Voltage LOW -0.3 0.3 V DD V VIH Input Voltage HIGH 0.7 V DD VDD+0.3 V |ILIH| Input Leakage Current HIGH V IH = VDD 5µ A |ILIL| Input Leakage Current LOW V IL = 0 5 µA Symbol Parameter Test Conditions Min. Typ. Max. Unit VOL Low Level Output Voltage I OL = 2 mA 0 0.3 V VOH High Level Output Voltage I OH = -15 µA 0.75 V DD V RPU Integrated pull-up resistor 20k Ω Pull-up resistor to VDD 16 20 24 k Ω Symbol Parameter Test Conditions Min. Typ. Max. Unit |ICC(SD)| Shutdown and limitation current pin VCC 90 120 mA II/O(lim) limitation current pins I/O, AUX1 and AUX2 -15 15 mA ICLK(lim) limitation current pin CLK -70 70 mA IRST(lim) limitation current pin RST -20 20 mA TSD Shut down temperature 150 °C Symbol Parameter Test Conditions Min. Typ. Max. Unit tACT Activation time (See Fig. 5) 50 220 µs tDE Deactivation time (See Fig. 7) 50 80 100 µs t3 Start of the window for sending CLK to the card (See Fig. 6) 50 130 µs t5 End of the window for sending CLK to card (See Fig. 6) 140 220 µs tdebounce Debounce time pins PRES and PRES (See Fig. 8) 5 8 11 ms

Figure 3: Definition of output and input transition times FUNCTIONAL DESCRIPTION Throughout this document it is assumed that the reader is familiar with ISO7816 terminology. POWER SUPPLY The supply pins for the IC are V DD and GND. V DD should be in the range of 2.7 to 6.5 V. All signals interfacing with the system controller are referred to V DD, therefore V DD should also supply the system controller. All card reader contacts remain inactive during power-on or power-off. The internal circuits are maintained in the reset state until VDD reaches Vth2 +Vhys2 and for the duration of the internal Power-on reset pulse, tW (see Fig.4). When VDD falls below Vth2, an automatic deactivation of the contacts is performed. A DC/DC converter is incorporated to generate the 5 or 3 V card supply voltage (V CC). The DC/DC converter should be supplied separately by V DDP and PGND. Due to the possibility of large transient currents, the two 100 nF capacitors of the DC/DC converter should be located as near as possible to the IC and have an ESR less than 100 m Ω. The DC/DC converter functions as a voltage doubler or a voltage follower according to the respective values of VCC and VDDP (both have thresholds with a hysteresis of 100 mV). The DC/DC converter function changes as follows: V CC = 5 V and VDDP > 5.8 V; voltage follower VCC = 5 V and VDDP < 5.7 V; voltage doubler VCC = 3 V and VDDP > 4.1 V; voltage follower VCC = 3 V and VDDP < 4.0 V; voltage doubler. Supply voltages VDD and VDDP may be applied to the IC in any sequence. After powering the device, OFF remains LOW until CMDVCC is set HIGH. During power off, OFF falls LOW when VDD is below the falling threshold voltage. VOLTAGE SUPERVISOR - WITHOUT EXTERNAL DIVIDER ON PIN PORADJ The voltage supervisor surveys the V DD supply. A defined reset pulse of approximately 8ms (t W) is used internally to keep the IC inactive during power-on or power-off of the V DD supply (see Fig.4). As long as V DD is less than V th2 + V hys2, the IC remains inactive whatever the levels on the command lines. This state also lasts for the duration of t W after V DD has reached a level higher than V th2 + Vhys2. When VDD falls below Vth2, a deactivation sequence of the contacts is performed.

Figure 4: Voltage supervisor WITH AN EXTERNAL DIVIDER ON PIN PORADJ If an external resistor bridge is connected to pin PORADJ (R1 and R2 in Fig.1), then the following occurs: - The internal threshold voltage V th2 is overridden by the external voltage and by the hysteresis, therefore: Vth2(ext)(rise) = (1 + R1/R2) x (V bridge + Vhys(ext)/2) Vth2(ext)(fall) = (1 + R1/R2) x (Vbridge - Vhys(ext)/2) where Vbridge = 1.18 V typ. and V hys(ext) = 60 mV typ. - The reset pulse width t W is doubled to approximately 16 ms. Input PORADJ is biased internally with a pull-down current source of 4 µA which is removed when the voltage on pin PORADJ exceeds 1 V. This ensures that after detection of the external bridge by the IC during power-on, the input current on pin PORADJ does not cause inaccuracy of the bridge voltage. The minimum threshold voltage should be higher than 2 V. The maximum threshold voltage may be up to VDD. APPLICATION EXAMPLES The voltage supervisor is used as Power-on reset and as supply dropout detection during a card session. Supply dropout detection is to ensure that a proper deactivation sequence is followed before the voltage is too low. For the internal voltage supervisor to function, the system microcontroller should operate down to 2.35 V to ensure a proper deactivation sequence. If this is not possible, external resistor values can be chosen to overcome the problem. CLOCK CIRCUITRY The card clock signal (CLK) is derived from a clock signal input to pin XTAL1 or from a crystal operating at up to 26 MHz connected between pins XTAL1 and XTAL2. The clock frequency can be f XTAL, 1 /2 x fXTAL, 1 /4 x fXTAL or 1 /8 x f XTAL. Frequency selection is made via inputs CLKDIV1 and CLKDIV2 (see Table 20).

Table 20: Clock frequency selection; (note 1) NOTE 1: The status of pins CLKDIV1 and CLKDIV2 must not be changed simultaneously; a delay of 10 ns minimum between changes is needed; the minimum duration of any state of CLK is eight periods of XTAL1. The frequency change is synchronous, which means that during transition no pulse is shorter than 45% of the smallest period, and that the first and last clock pulses about the instant of change have the correct width. When changing the frequency dynamically, the change is effective for only eight periods of XTAL1 after the command. The duty factor of f XTAL depends on the signal present at pin XTAL1. In order to reach a 45 to 55% duty factor on pin CLK, the input signal on pin XTAL1 should have a duty factor of 48 to 52% and transition times of less than 5% of the input signal period. If a crystal is used, the duty factor on pin CLK may be 45 to 55% depending on the circuit layout and on the crystal characteristics and frequency. In other cases, the duty factor on pin CLK is guaranteed between 45 and 55% of the clock period. The crystal oscillator runs as soon as the IC is powered up. If the crystal oscillator is used, or if the clock pulse on pin XTAL1 is permanent, the clock pulse is applied to the card as shown in the activation sequences shown in Figs 5 and 6. If the signal applied to XTAL1 is controlled by the system microcontroller, the clock pulse will be applied to the card when it is sent by the system microcontroller (after completion of the activation sequence). I/O TRANSCEIVERS The three data lines I/O, AUX1 and AUX2 are identical.The idle state is realized by both I/O and I/OUC lines being pulled HIGH via a 11 k Ω resistor (I/O to V CC and I/OUC to VDD). Pin I/O is referenced to VCC, and pin I/OUC to V DD, thus allowing operation when V CC is not equal to V DD. The first side of the transceiver to receive a falling edge becomes the master. An anti-latch circuit disables the detection of falling edges on the line of the other side, which then becomes a slave. After a time delay t d(edge), an N transistor on the slave side is turned on, thus transmitting the logic 0 present on the master side. When the master side returns to logic 1, a P transistor on the slave side is turned on during the time delay t pu and then both sides return to their idle states. This active pull-up feature ensures fast LOW-to-HIGH transitions; it is able to deliver more than 1 mA at an output voltage of up to 0.9 V CC into an 80 pF load. At the end of the active pull-up pulse, the output voltage depends only on the internal pull-up resistor and the load current. The current to and from the card I/O lines is limited internally to 15 mA and the maximum frequency on these lines is 1 MHz. INACTIVE MODE After a Power-on reset, the circuit enters the inactive mode. A minimum number of circuits are active while waiting for the microcontroller to start a session: - All card contacts are inactive (approximately 200 Ω to GND) - Pins I/OUC, AUX1UC and AUX2UC are in the high-impedance state (11 k Ω pull-up resistor to V DD) - Voltage generators are stopped - XTAL oscillator is running - Voltage supervisor is active - The internal oscillator is running at its low frequency. ACTIVATION SEQUENCE After power-on and after the internal pulse width delay, the system microcontroller can check the presence of a card using the signals OFF and CMDVCC as shown in Table 21. CLKDIV1 CLKDIV2 fCLK 00 fXTAL/8 01 fXTAL/4 11 fXTAL/2 10 fXTAL

If the card is in the reader (this is the case if PRES or PRES is active), the system microcontroller can start a card session by pulling CMDVCC LOW. The following sequence then occurs (see Fig.6): 1. CMDVCC is pulled LOW and the internal oscillator changes to its high frequency (t 0). 2. The voltage doubler is started (between t 0 and t1). 3. VCC rises from 0 to 5 V (or 3 V) with a controlled slope (t 2 = t1 + 1.5 x T) where T is 64 times the period of the internal oscillator (approximately 25 µs). 4. I/O, AUX1 and AUX2 are enabled (t 3 = t1 + 4T) (these were pulled LOW until this moment). 5. CLK is applied to the C3 contact of the card reader (t 4). 6. RST is enabled (t5 = t1 + 7T). The clock may be applied to the card using the following sequence (see Fig.5): 1. Set RSTIN HIGH. 2. Set CMDVCC LOW. 3. Reset RSTIN LOW between t 3 and t5; CLK will start at this moment. 4. RST remains LOW until t5, when RST is enabled to be the copy of RSTIN. 5. After t 5, RSTIN has no further affect on CLK; this allows a precise count of CLK pulses before toggling RST. If the applied clock is not needed, then CMDVCC may be set LOW with RSTIN LOW. In this case, CLK will start at t3 (minimum 200 ns after the transition on I/O), and after t 5, RSTIN may be set HIGH in order to obtain an Answer To Request (ATR) from the card. Activation should not be performed with RSTIN held permanently HIGH. Table 21: Card presence indicator Figure 5: Activation sequence using RSTIN and CMDVCC OFF CMDVCC INDICATION H H card present L H card not present

Figure 6: Activation sequence at t 3 ACTIVE MODE When the activation sequence is completed, the ST8024 will be in its active mode. Data are exchanged between the card and the microcontroller via the I/O lines. The ST8024 is designed for cards without V PP (the voltage required to program or erase the internal non-volatile memory). DEACTIVATION SEQUENCE When a session is completed, the microcontroller sets the CMDVCC line HIGH. The circuit then executes an automatic deactivation sequence by counting the sequencer back and finishing in the inactive mode (see Fig.7): 1. RST goes LOW (t 10). 2. CLK is held LOW (t 12 = t 10 + 0.5 x T) where T is 64 times the period of the internal oscillator (approximately 25 µs). 3. I/O, AUX1 and AUX2 are pulled LOW (t 13 = t10 + T). 4. VCC starts to fall towards zero (t 14 = t10 + 1.5 x T). 5. The deactivation sequence is complete at t de, when VCC reaches its inactive state. 6. VUP falls to zero (t15 = t10 + 5T) and all card contacts become low-impedance to GND; I/OUC, AUX1UC and AUX2UC remain at V DD (pulled-up via a 11 k Ω resistor). 7. The internal oscillator returns to its lower frequency.

Figure 7: Deactivation sequence VCC GENERATOR The VCC generator has a capacity to supply up to 80 mA continuously at 5 V and 65 mA at 3 V. An internal overload detector operates at approximately 120 mA. Current samples to the detector are internally filtered, allowing spurious current pulses up to 200 mA with a duration in the order of µs to be drawn by the card without causing deactivation. The average current must stay below the specified maximum current value. For reasons of V CC voltage accuracy, a 100 nF capacitor with an ESR < 100 m Ω should be tied to CGND near to pin V CC, and 100 nF capacitor with the same ESR should be tied to CGND near card reader contact C1. FAULT DETECTION The following fault conditions are monitored: - Short-circuit or high current on V CC - Removal of a card during a transaction - V DD dropping - DC/DC converter operating out of the specified values (V DDP too low or current from V UP too high) - Overheating. There are two different cases (see Fig.8): - CMDVCC HIGH outside a card session. Output OFF is LOW if a card is not in the card reader, and HIGH if a card is in the reader. A voltage drop on the V DD supply is detected by the supply supervisor, this generates an internal Power-on reset pulse but does not act upon OFF . No short-circuit or overheating is detected because the card is not powered-up. - CMDVCC LOW within a card session. Output OFF goes LOW when a fault condition is detected. As soon as this occurs, an emergency deactivation is performed automatically (see Fig.9). When the system controller resets CMDVCC to HIGH it may sense the OFF level again after completing the deactivation sequence. This distinguishes between a hardware problem or a card extraction (OFF goes HIGH again if a card is present). Depending on the type of card-present switch within the connector (normally-closed or normally-open) and on the mechanical characteristics of the switch, bouncing may occur on the PRES signals at card insertion or withdrawal. There is a debounce feature in the device with an 8 ms typical duration (see Fig.8). When a card is inserted, output OFF goes HIGH only at the end of the debounce time. When the card is extracted, an automatic deactivation sequence of the card is performed on the first true/ false transition on PRES or PRES and output OFF goes LOW.

Figure 10: Application Diagram (1) These capacitors must be of the low ESR-type and be placed near the IC (within 100 mm). (2) ST8024 and the microcontroller must use the same V DD supply. (3) Make short, straight connections between CGND, C5 and the ground connection to the capacitor. (4) Mount one low ESR-type 100 nF capacitor close to pin V CC . (5) Mount one low ESR-type 100 nF capacitor close to C1 contact (less than 100 mm from it). (6) The connection to C3 should be routed as far from C2, C7, C4 and C8 and, if possible, surrounded by grounded tracks. (7) Optional resistor bridge for changing the threshold of VDD . If this bridge is not required pin 18 should be connected to g round.

DIM. mm. inch A 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45˚ (typ.) D 17.70 18.10 0.697 0.713 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 16.51 0.650 F 7.40 7.60 0.291 0.300 L 0.50 1.27 0.020 0.050 S˚ ( m a x . ) SO-28 MECHANICAL DATA 0016023

DIM. mm. inch A 1.2 0.047 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 e 0.65 BSC 0.0256 BSC K0 ˚ 8˚ 0˚ 8˚ TSSOP28 MECHANICAL DATA 0128292B

DIM. mm. inch A 330 12.992 C 12.8 13.2 0.504 0.519 D 20.2 0.795 N 60 2.362 T 30.4 1.197 Ao 10.8 11.0 0.425 0.433 Bo 18.2 18.4 0.716 0.724 Ko 2.9 3.1 0.114 0.122 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 Tape & Reel SO-28 MECHANICAL DATA

DIM. mm. inch A 330 12.992 C 12.8 13.2 0.504 0.519 D 20.2 0.795 N 60 2.362 T 22.4 0.882 Ao 6.8 7 0.268 0.276 Bo 10.1 10.3 0.398 0.406 Ko 1.7 1.9 0.067 0.075 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 Tape & Reel TSSOP28 MECHANICAL DATA

Table 22: Revision History Date Revision Description of Changes 31-Jan-2005 1 First Release.

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