ST8004

ST8004 STMICROELECTRONICS | Alldatasheet

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I 3O R5VS U P P L YF O RT H EI C I STEP-UP CONVERTER FOR V CC GENERATION I 3 SPECIFIC PROTECTED HALF DUPLEX BI-DIRECTIONAL BUFFERED I/O LINES I AUTOMATIC ACTIVATION AND DEACTIVATION SEQUENCES I THERMAL AND SHORT-CIRCUIT PROTECTIONS ON ALL CARD CONTACTS I 26 MHz INTEGRATED CRYSTAL OSCILLATOR I CLOCK GENERATION FOR THE CARD UP TO 20MHz WITH SYNCHRONOUS FREQUENCY CHANGES I ISO7816-3 COMPATIBLE I ENHANCED ESD PROTECTION ON CARD SIDE I SO-28 PACKAGE I UNDER VOLTAGE LOCKOUT PROTECTION SELECTABLE TO 3V OR 2.2V I SUPPLY SUPERVISOR INTEGRATED

DESCRIPTION

The ST8004 is a complete low cost analog interface for asynchronous 3V and 5V smart cards. It can be placed between the card and the microcontroller with few external components to perform all supply protection and control functions. Main applications are: smartcard readers for Set Top Box, IC card readers for banking, identification. ORDERING CODES Type Temperature Range Package Comments ST8004CD 0 to 85 °C SO-28 (Tube) 27 parts per tube / 12 tube per box ST8004CDR 0 to 85 °C SO-28 (Tape & Reel) 1000 parts per reel ST8004 SMARTCARD INTERFACE SOP

PlN N° SYMBOL NAME AND FUNCTION

1 CLKDIV1 Control of CLK Frequency

2 CLKDIV2 Control of CLK Frequency

35 V / 3 V VCC selection pin.

4 PGND Power Ground for Step-Up converter

5 C1+ External Cap. for Step-Up converter

6 VDDP Power Supply for Step-Up converter

7 C1- External Cap. Step-Up converter

8 VUP Output of Step-Up converter

9P R E S Card Presence Input (Active Low)

10 PRES Card Presence Input (Active High)

11 I/O Data Line to and from card (C7) (internal 10kΩ pull-up resistor connected to VCC )

12 AUX2 Auxiliary line to and from card (C8) (internal 10kΩ pull-up resistor connected to VCC )

13 AUX1 Auxiliary line to and from card (C4) (internal 10kΩ pull-up resistor connected to VCC )

14 CGND Ground for card signal (C5)

15 CLK Clock to card (C3)

16 RST Card Reset (C2)

CC Supply Voltage for the card (C1)

18 VTHSEL Deactivation threshold selector pin (under voltage lock-out)

19 CMDV CC Start activation sequence input (Active Low)

20 RSTIN Card Reset Input from MCU

21 VDD Supply Voltage

22 GND Ground

23 OFF Interrupt to MCU (active Low)

24 XTAL1 Crystal or external clock input

25 XTAL2 Crystal connection (leave this pin open if external clock is used)

26 I/OUC Data Line to and from MCU (internal 10kΩ pull-up resistor connected to V

DD )

27 AUX1UC Auxiliary line to and from MCU (internal 10kΩ pull-up resistor connected to VDD )

28 AUX2UC Auxiliary line to and from MCU (internal 10kΩ pull-up resistor connected to VDD )

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Note 1: All card contacts are protected against any short with any other card contact. Note 2: Method 3015 (HBM, 1500Ω , 100 pF) 3 positive pulses and 3 negative pulses on each pin referenced to ground. THERMAL DATA RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING (VDD =3 . 3 V ,VDDP =5 V , fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta =2 5 ° C ) Symbol Parameter Min Max Unit VDD, VDDP Supply Voltage -0.3 7 V Vn1 Voltage on pins XTAL1, XTAL2, 5V/3V,R S T I N ,A U X 2 U C , AUX1UC, I/OUC, CLKDIV1, CLKDIV2, VTHSEL ,C M D VCC ,P R E S, PRES and OFF -0.3 VDD +0 . 3 V Vn2 Voltage on card contact pins I/O, RST, AUX1, AUX2 and CLK -0.3 VCC +0 . 3 V Vn3 Voltage on pins VUP, S1 and S2 9V ESD1 M I L - S T D - 8 8 3c l a s s3o nc a r dc o n t a c tp i n s ,P R E Sand PRES (Note 1, 2) -6 6 KV ESD2 MIL-STD-883 class 2 on µC contact pins and RSTIN (Note 1, 2) -2 2 KV Symbol Parameter Condition Value Unit Rthj-amb Thermal Resistance Junction-ambient Temperature In free air 70 °K/W Symbol Parameter Test Conditions Min. Typ. Max. Unit TA Temperature Range -25 85 °C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Supply Voltage V THSEL =V DD or floating 2.7 6.5 V VTHSEL =G N D 3 . 1 5 0 6 . 5 VDDP Supply Voltage for the voltage doubler 4.5 5 6.5 V To comply with VI(RIPPLE)(P-P)specifications 4.75 5.25 VO(VUP) O u t p u tV o l t a g eo np i nVUP from step-up converter 5.5 V VI(VUP) Input Voltage to be applied on VUP in order to block the step-up converter 79 V IDD Supply Current Inactive mode 1.2 mA Active mode; fCLK =fXTAL ;C L =3 0 p F 1 . 5 IP Supply Current for Step-Up converter Inactive mode 0.1 mA Active mode; fCLK =fXTAL ; C L = 30pF ICC =0 1 8 ICC = 65 mA 150 Vth2 Threshold Voltage on VDD VTHSEL =V DD or floating 2.2 2.4 V Vth3 Threshold Voltage on VDD VTHSEL = GND 2.95 3.05 V VHYS(th2) Hysteresis on Vth2 VTHSEL =V DD or floating 50 150 mV VHYS(th3) Hysteresis on Vth3 VTHSEL =G N D 0 m V tW Pulse width of the internal Alarm pulse 62 0 m s ∆ THFIL Delay of Internal filter VTHSEL =G N D 5 5 0 µ s

CARD SUPPLY VOLTAGE CHARACTERISTICS (VDD =3 . 3 V ,VDDP =5 V ,fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) (Note 1) CRYSTAL CONNECTION (PINS XTAL1 AND XTAL2) (VDD =3 . 3 V ,VDDP =5 V ,fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta =2 5 ° C ) DATA LINES (PINS I/O, AUX1, AUX2, AUX1UC AND AUX2UC) (VDD =3 . 3 V ,VDDP =5 V ,fXTAL =1 0 M H z , unless otherwise noted. Typical values are to Ta =2 5 ° C ) Symbol Parameter Test Conditions Min. Typ. Max. Unit VCC Output Voltage including ripple Inactive Mode -0.1 0.1 V Inactive Mode; ICC = 1 mA -0.1 0.4 Active Mode; VDDP =5 V±5 % |ICC |<6 5m AD C 5 V card 4.75 5.25 3 V card 2.85 3.15 Active Mode; single current pulse of 100 mA; 2 µs 5 V card 4.65 5.25 3 V card 2.85 3.15 Active Mode; current pulse of 40 nAs with |ICC |<200mA t < 400 ns 5 V card 4.65 5.25 3 V card 2.76 3.15 VI(RIPPLE) (P-P) Peak to Peak ripple voltage on VCC

20 KHz to 200 MHz

V DDP =5 V±5 % 350 mV |ICC | Output Current From 0 to 5V or to 3V 65 mA VCC short circuit to GND 150 SR Slew Rate Up to down 0.11 0.22 V/µs Symbol Parameter Test Conditions Min. Typ. Max. Unit C EXT External capacitors on pins XTAIL1, XTAIL2 Depending on specification of crystal or resonator used 15 pF fI(XTAL) Crystal Input Frequency 2 26 MHz VIH(XTAL) High level input voltage on XTAIL1

0.7 VDD VDD V

VIL(XTAL) Low level input voltage on XTAIL1 00 . 3 V DD V Symbol Parameter Test Conditions Min. Typ. Max. Unit tD(EDGE) Delay between falling edge on pin I/O and I/OUC and width of active pull-up pulse 200 ns fI/O(MAX) Maximum frequency of data lines 1M H z C I Input capacitance on data lines 10 pF

DATA LINES (PINS I/O, AUX1 AND AUX2 WITH 10 kΩ PULL-UP RESISTOR CONNECTED TO V CC INTERNALLY (VDD =3 . 3 V ,VDDP =5 V ,fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) DATA LINES (PINS I/OUC, AUX1UC AND AUX2UC WITH 10 k Ω PULL-UP RESISTOR CONNECTED TO V DD INTERNALLY (VDD =3 . 3 V ,VDDP =5 V ,fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta =2 5 ° C ) Symbol Parameter Test Conditions Min. Typ. Max. Unit VOH High Level Output Voltage on data lines IOH = - 40µA 0.75 V CC VCC V No Load 0.9 V CC VCC +0.3 VOL Low Level Output Voltage on data lines IOL =1m A 3 0 0 m V VIH High Level Input Voltage on data lines

1.8 V CC V

VIL Low Level Input Voltage on data lines -0.3 0.8 V VINACTIVE Voltage on data lines when inactive No Load 0.1 V II/O=1m A 0 . 3 IEDGE Current from data lines when active pull-up is active VOH =0 . 7xVCC ;C O =8 0p F - 1 m A |IIH| Input Leakage Current when high VIH =V CC 10 µA IIL Low Level Input Current V IL=0 6 0 0 µA R PU(INT) Internal pull-up resistance to VCC 91 3 K Ω tT(DI) Input transition times From V ILmax to VIH min 1 µs tT(DO) Output transition times C O = 80 pF, no DC load;

0.4 V to 70% from 0 to VCC

0.1 µs C I Input capacitance 10 pF Symbol Parameter Test Conditions Min. Typ. Max. Unit VOH High Level Output Voltage IOH = - 40µA 0.75 V DD VDD V No Load 0.9 V DD VOL Low Level Output Voltage IOL = 1 mA 0 300 mV VIH High Level Input Voltage 0.7 V DD VDD V VIL Low Level Input Voltage 0 0.3 V DD V |ILIH| Input Leakage Current when high VIH =V DD 10 µA IIL Input Leakage Current when low VIL=0 6 0 0 µA R PU(INT) Internal pull-up resistance to VDD 91 1 1 3 K Ω tT(DI) Input transition times From V ILmax to VIH min 1 µs tT(DO) Output transition times C O = 30 pF, no DC load; 10% to 90% from 0 to VDD 0.1 µs C I Input capacitance 10 pF

INTERNAL OSCILLATOR (VDD =3 . 3 V ,VDDP =5 V ,fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta =2 5 ° C ) RESET OUTPUT TO THE CARD (PIN RST) (VDD =3 . 3 V ,VDDP =5 V ,fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) CLOCK OUTPUT TO THE CARD (PIN CLK) (VDD =3 . 3 V ,VDDP =5 V ,fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) LOGIC INPUTS (PINS CLKDIV1, CLKDIV2, PRES, PRES ,C M D VCC , RSTIN AND 5V/3V, VTHSEL (VDD =3 . 3 V ,VDDP =5 V ,fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) (Note 3) Symbol Parameter Test Conditions Min. Typ. Max. Unit fOSC(INT) Frequency of internal oscillator 2.2 3.2 MHz Symbol Parameter Test Conditions Min. Typ. Max. Unit VO(INACTIVE) Output Voltage in Inactive Mode IO =1m A 0 0 . 3 V No Load 0 0.1 tD(RSTIN-RST) Delay between pins RSTN and RST RST Enable 2 µs VOL Low Level Output Voltage IOL = 200 µA 0 0.2 V VOH High Level Output Voltage IOH =- 2 0 0µ A 0 . 9V CC VCC V tR, tF Rise and fall time (10% to 90% of VCC ) C O = 250 pF 0.1 µs Symbol Parameter Test Conditions Min. Typ. Max. Unit VO(INACTIVE) Output Voltage in Inactive Mode IO =1m A 0 0 . 3 V No Load 0 0.1 VOL Low Level Output Voltage IOL = 200 µA 0 0.3 V VOH High Level Output Voltage IOH =- 2 0 0µ A 0 . 9V CC VCC V tR, tF Rise and fall time (10% to 90% of VCC ) C O =3 5p F( N o t e2 ) 8 n s δ Duty cycle factor (except for fXTALS )( S e eN o t e4 ) C O = 35 pF (Note 2) 45 55 % SR Slew Rate (rise and fall edge) CO =3 5p F 0 . 2 V / n s Symbol Parameter Test Conditions Min. Typ. Max. Unit VIL Low Level Input Voltage 0 0.3 V DD V VIH High Level Input Voltage 0.7 V DD VDD V |ILIH| Input Leakage Current when high VIL=0t oV DD 5µ A |ILIL| Input Leakage Current when low VIH =0t oV DD 5 µA

OFF OUTPUTS (PIN OFF IS AN OPEN DRAIN WITH AN INTERNAL 20 k Ω PULL-UP RESISTOR TO VDD );(see note 5) (VDD =3 . 3 V ,VDDP =5 V ,fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) PROTECTION (VDD =3 . 3 V ,VDDP =5 V ,fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta = 25°C) TIMING (VDD =3 . 3 V ,VDDP =5 V ,fXTAL = 10MHz, unless otherwise noted. Typical values are to Ta =2 5 ° C ) Note 1: To meet these specifications VCC should be decoupled to CGND using two ceramic multiplier capacitors of low ESR with values of 100nF. N o t e2 :T h et r a n s i t i o nt i m ea n dd u t yc y c l ef a c t o ra r es h o w ni nf i g u r e7 ;d=t 1 / ( t 1 + t 2 ) . Note 3: PRESand CMDVCC are active Low; RSTIN and PRES are active High Note 4: Referred to the paragraph "CLOCK CIRCUITRY" Note 5: See paragraph "FAULT DETECTION". Figure 1 :Alarm as a function of VDD (tW =1 0m s ) ,VTHSEL =V DD or floating Symbol Parameter Test Conditions Min. Typ. Max. Unit VOL Low Level Output Voltage IOL =2m A 0 . 4 V VOH High Level Output Voltage IOH = -15 µA 0.75 V DD V Symbol Parameter Test Conditions Min. Typ. Max. Unit TSD Shut down temperature 135 °C ICC(SD) Shut down current at VCC 150 mA Symbol Parameter Test Conditions Min. Typ. Max. Unit tACT Activation sequence duration (See Fig. 3) 180 220 µs tDE Deactivation sequence duration (See Fig. 4) 60 80 100 µs t3 Start of the windows to send CLK to card (See Fig. 3) 130 µs t5 End of the windows to send CLK to card (See Fig. 3) 140 µs

be tied to pin VUP , thus blocking the step-up converter. In this case, VDDP must be tied to VDD and the capacitor between pins S1 and S2 may be omitted. VOLTAGE SUPERVISOR (FOR V THSEL =V DD OR FLOATING) This block surveys the VDD supply. A defined reset pulse of approximately 10 ms (tW ) is used internally for maintaining the IC in the inactive mode during powering up or powering down of VDD (see Fig.1). As long as VDD is less than Vth2+V hys(th2), the IC will remain inactive whatever the levels on the command lines. This also lasts for the duration of tW after VDD has reached a level higher than Vth2+V hys(th2).The system controller should not attempt to start an activation sequence during this time. When VDD falls below Vth2, a deactivation sequence of the contacts is performed. VOLTAGE SUPERVISOR (FOR V THSEL = GND) This block surveys the VDD supply. A defined reset pulse of approximately 10 ms (tW ) is used internally for maintaining the IC in the inactive mode during powering up or powering down of VDD (see Fig.2). If VDD is less than Vth3during a time, longer than∆ THFIL (max 150µs), the IC will remain inactive whatever the levels on the command lines. The IC remain inactive also for the duration of tw after VDD has reached a level higher than Vth3. The system controller should not attempt to start an activation sequence during this time. When VDD falls below Vth3during time more than∆ THFIL, a deactivation sequence of the contacts is performed. CLOCK CIRCUITRY The clock signal (CLK) to the card is either derived from a clock signal input on the pin XTAL1 or from a crystal up to 26 MHz connected between pins XTAL1 and XTAL2. The frequency may be chosen at fXTAL ,1/2 fXTAL ,1/4 fXTAL or 1/8 fXTAL via pins CLKDIV1 and CLKDIV2 (see Table 1). The frequency change is synchronous, which means that during transition, no pulse is shorter than 45% of the smallest period and that the first and last clock pulse around the change has the correct width. I nt h ec a s eo ff XTAL , the duty factors depend on the signal at XTAL1. In order to reach a 45% to 55% duty factor on the pin CLK the input signal on XTAL1 should have a duty factor of 48% to 52% and transition times of less than 5% of the input signal period.If a crystal is used with fXTAL , the duty factor on pin CLK may be 45% to 55% depending on the layout and on the crystal characteristics and frequency. In the other cases, it is guaranteed between 45% and 55% of the period. The crystal oscillator runs as soon as the IC is powered-up. If the crystal oscillator is used, or if the clock pulse on XTAL1 is permanent, then the clock pulse will be applied to the card according to the timing diagram of the activation sequence. If the signal applied to XTAL1 is controlled by the micro-controller, then the clock pulse will be applied to the card by the microcontroller after completion of the activation sequence. TABLE 1 I/O CIRCUITRY The three data lines I/O, AUX1 and AUX2 are identical. The Idle state is realized by data lines I/O and I/ OUC being pulled HIGH via a 10k resistor (I/O to V CC and I/OUC to VDD ). I/O is referenced to VCC ,a n d I/OUC to VDD , thus allowing operation with VCC ≠ VDD . The first line on which a falling edge occurs becomes the master. An anti-latch circuit disables the detection of falling edges on the other line, which then becomes the slave. After a time delay td (edge) (approximately 200 ns), the N transistor on the slave line is turned on, thus transmitting the logic 0 present on the master line.When the master line returns to logic 1, the P transistor on the slave line is turned on during the time delay td (edge) and then both lines return to their idle state. This active pull-up feature ensures fast LOW-to-HIGH transitions; it is able to deliver more than 1 mA up to an output voltage of 0.9 V CC on a 80pF load. At the end of the active pull-up CLKDIV1 CLKDIV2 CLK 00 1/8 fXTAL 01 1/4 fXTAL 11 1/2 fXTAL 10 fXTAL

pulse, the output voltage only depends on the internal pull-up resistor, and on the load current. The maximum frequency on these lines is 1MHz. INACTIVE STATE After power-on reset, the circuit enters the inactive state. A minimum number of circuits are active while waiting for the microcontroller to start a session.  All card contacts are inactive (approximately 200Ω to GND); I/OUC, AUX1UC and AUX2UC are high impedance (10 kΩ pull-up resistor connected to VDD )  Voltage generators are stopped  XTAL oscillator is running  Voltage supervisor is active. ACTIVATION SEQUENCE After power-on and, after the internal pulse width delay, the microcontroller may check the presence of the card with the signal OFF (OFF = HIGH while CMDVCC is High means that the card is present; OFF=L O W while CMDVCC is HIGH means that no card is present). If the card is in the reader (which is the case if PRESor PRES is true), the microcontroller may start a card session by pulling CMDVCC LOW. The following sequence then occurs (see Fig.3): C M D VCC is pulled LOW (t0)  The voltage doubler is started (t1~t0) V CC r i s e sf r o m0t o5o r3 Vw i t hac o n t r o l l e ds l o p e( t 2=t 1+ ½ 3 T ) ( I / O ,A U X 1a n dA U X 2f o l l o wVCC with a slight delay); T is 64 times the period of the internal oscillator, approximately 25µs  I/O, AUX1 and AUX2 are enabled (t3 = t1 +4T)  CLK is applied to the C3 contact (t4)  RST is enabled (t5 = t1 +7T). The clock may be applied to the card in the following way: set RSTIN High before setting CMDV CC Low, and reset it Low between t3 and t5; CLK will start at this moment. RST will remain LOW until t5, where RST is enabled to be the copy of RSTIN. After t5, RSTIN has no further action on CLK. This is to allow a precise count of CLK pulses before toggling RST. If this feature is not needed, then CMDV CC may be set LOW with RSTIN Low. In this case, CLK will start at t3, and after t5, RSTIN may be set High in order to get the Answer To Request (ATR) from the card. ACTIVE STATE When the activation sequence is completed, the ST8004 will be in the active state. Data are exchanged between the card and the microcontroller via the I/O lines. The ST8004 is designed for cards without V PP (this is the voltage required to program or erase the internal non-volatile memory). Depending on the layout and on the application test conditions (for example with an additional 1pF cross capacitance between C2/C3 and C2/C7) it is possible that C2 is polluted with high frequency noise from C3. In this case, it will be necessary to connect a 220pF capacitor between C2 and CGND. It is recommended to: 1. Keep track C3 as far as possible from other tracks 2. Have straight connection between CGND and C5 (the 2 capacitors on C1 should be connected to this ground track) 3. Avoid ground loops between CGND,PGND and GND 4. Decoupled V DDP and VDD separately; if the 2 supplies are the same in the application, then they should be connected in star on the main track. With all these layout precautions, noise should be at an acceptable level, and jitter on C3 should be less than 100ps. DEACTIVATION SEQUENCE When a session is completed, the microcontroller sets the CMDV CC line to the HIGH state. The circuit then executes an automatic deactivation sequence by counting the sequencer back and ends in the inactive state (see Fig.4):  RST goes LOW → (t11 = t10)  CLK is stopped LOW→ (t12 = t11 +½T) where T is approximately 25 µs  I/O, AUX1 and AUX2 are output into high-impedance state→ (t13 = t11 +T)(10 kΩ pull-up resistor connected to VCC )

V CC falls to zero→ (t14 = t11 +½3T); the deactivation sequence is completed when VCC reaches its inactive state V UP falls to zero→ (t15 = t11 +5T) and all card contacts become low-impedance to GND;  I/OUC, AUX1UC and AUX2UC remain pulled up to VDD via a 10 kΩ resistor. FAULT DETECTION The following fault conditions are monitored by the circuit: Short-circuit or high current on VCC Removing card during transaction V DD dropping Overheating. There are two different cases (Fig. 5) 1. CMDV CC HIGH: (outside a card session) then, OFFis LOW if the card is not in the reader, and HIGH i ft h ec a r di si nt h er e a d e r .As u p p l yv o l t a g ed r o po nVDD is detected by the supply supervisor, which generates an internal power-on reset pulse, but does not act upon OFF. The card is not powered-up, so no short-circuit or overheating is detected. 2. CMDV CC LOW: (within a card session) then, OFFfalls LOW if the card is extracted, or if a short-circuit h a so c c u r r e do nVCC , or if the temperature on the IC has become too high. As soon as the fault is detected, an emergency deactivation is automatically performed (see Fig.6). When the system controller sets CMDV CC back to HIGH, it may sense OFFagain in order to distinguish between a hardware problem or a card extraction. If a supply voltage drop on VDD is detected while the card is activated, then an emergency deactivation will be performed and OFFgoes LOW. When OFF level falls low, the system controller must wait not less than 160µs before setting high again the CMDV CC command. Depending on the type of card presence switch within the connector (normally closed or normal open), and on the mechanical characteristics of the switch, a bouncing may occur on presence signals at card insertion or withdrawal. There is no debounce feature in the device, so the software has to take it into account; however, the detection of card take off during active phase, which initiates an automatic deactivation sequence is done on the first True/False transition on PRES or PRES, and is memorized until the system controller sets CMDVCC High. So, the software may take some time waiting for presence switches to be stabilized without causing any delay on the necessary fast and normalized deactivation sequence.

CHANGE_OFF LOCK_OFF_HIGH LOCK_OFF_LOW OFF = PRES or (not PRES_NEG) OFF=0OFF=1 CMDVCC=0 OFF_temp = 0 Removing Card after the Activation Sequence OFF_temp = PRES or (not PRES_NEG) CMDVCC=0 OFF_temp = 1 CMDVCC=0 OFF_temp = 0 CMDVCC CMDVCC=1 Deactivation Sequence Dea ctivation S eq uence Activation Sequence Card isn’t in t he re ader and CM DVCC is pulled low

DIM. mm. inch A 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 C 0.5 0.020 c1 45˚ (typ.) D 17.70 18.10 0.697 0.713 E 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 16.51 0.650 F 7.40 7.60 0.291 0.300 L 0.50 1.27 0.020 0.050 S˚ ( m a x . ) SO-28 MECHANICAL DATA 0016023

DIM. mm. inch A 330 12.992 C 12.8 13.2 0.504 0.519 D 20.2 0.795 N 60 2.362 T 30.4 1.197 Ao 10.8 11.0 0.425 0.433 Bo 18.2 18.4 0.716 0.724 Ko 2.9 3.1 0.114 0.122 Po 3.9 4.1 0.153 0.161 P 11.9 12.1 0.468 0.476 Tape & Reel SO-28 MECHANICAL DATA

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