ST7PLITE05Y0B6TR

ST7LITE0XY0 STMICROELECTRONICS | Alldatasheet

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ST7LITE0xY0, ST7LITESxY0 8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI ■ Memories – 1K or 1.5 Kbytes single voltage Flash Pro- gram memory with read-out protection, In-Cir- cuit and In-Application Programming (ICP and IAP). 10 K write/erase cycles guaranteed, data retention: 20 years at 55 °C. – 128 bytes RAM. – 128 bytes data EEPROM with read-out pro- tection. 300K write/erase cycles guaranteed, data retention: 20 years at 55 °C. ■ Clock, Reset and Supply Management – 3-level low voltage supervisor (LVD) and aux- iliary voltage detector (AVD) for safe power- on/off procedures – Clock sources: internal 1MHz RC 1% oscilla- tor or external clock – PLL x4 or x8 for 4 or 8 MHz internal clock – Four Power Saving Modes: Halt, Active-Halt, Wait and Slow ■ Interrupt Management – 10 interrupt vectors plus TRAP and RESET – 4 external interrupt lines (on 4 vectors) ■ I/O Ports – 13 multifunctional bidirectional I/O lines – 9 alternate function lines – 6 high sink outputs ■ 2 Timers – One 8-bit Lite Timer (LT) with prescaler in- cluding: watchdog, 1 realtime base and 1 in- put capture. – One 12-bit Auto-reload Timer (AT) with output compare function and PWM ■ 1 Communication Interface – SPI synchronous serial interface ■ A/D Converter – 8-bit resolution for 0 to VDD – Fixed gain Op-amp for 11-bit resolution in 0 to 250 mV range (@ 5V VDD) – 5 input channels ■ Instruction Set – 8-bit data manipulation – 63 basic instructions with illegal opcode de- tection – 17 main addressing modes – 8 x 8 unsigned multiply instruction ■ Development Tools – Full hardware/software development package Device Summary DIP16 SO16 150” QFN20 Features ST7LITESxY0 (ST7SUPERLITE) ST7LITE0xY0 ST7LITES2Y0 ST7LITES5Y0 ST7LITE02Y0 ST7LITE05Y0 ST7LITE09Y0 Program memory - bytes 1K 1K 1.5K 1.5K 1.5K RAM (stack) - bytes 128 (64) 128 (64) 128 (64) 128 (64) 128 (64) D a t a E E P R O M - b y t e s ---- 1 2 8 Peripherals LT Timer w/ Wdg, AT Timer w/ 1 PWM, SPI LT Timer w/ Wdg, AT Timer w/ 1 PWM, SPI, 8-bit ADC LT Timer w/ Wdg, AT Timer w/ 1 PWM, SPI LT Timer w/ Wdg, AT Timer w/ 1 PWM, SPI, 8-bit ADC w/ Op-Amp Operating Supply 2.4V to 5.5V CPU Frequency 1MHz RC 1% + PLLx4/8MHz Operating Temperature -40°C to +85°C

16.2 IN-CIRCUIT PROGRAMMING OF DEVICES PREVIOUSLY PROGRAMMED WITH HARD-

To obtain the most recent version of this datasheet, please check at www.st.com Please also pay special attention to the Section “KNOWN LIMITATIONS” on page 121.

1 DESCRIPTION

tion when the application is in idle or standby state. Figure 1. General Block Diagram

2 PIN DESCRIPTION

Figure 2. 20-Pin QFN Package Pinout Figure 3. 16-Pin SO and DIP Package Pinout

16 PA1 (HS)e0e3

Table 1. Device Pin Description

ST7LITE0xY0, ST7LITESxY0 Note: In the interrupt input column, “eix” defines the associated external interrupt vector. If the weak pull-up col- umn (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 15 14 PA2/ATPWM0 I/O C T HS X XX X Port A2 Auto-Reload Timer PWM0 16 15 PA1 I/O C T HS X XX X Port A1 17 16 PA0/LTIC I/O C T HS X ei0 X X Port A0 Lite Timer Input Capture Pin n° Pin Name Type Level Port / Control Main Function (after reset) Alternate Function QFN20 SO16/DIP16 Input Output Input Output float wpu int ana OD PP

3 REGISTER & MEMORY MAP

Figure 4. Memory Map (ST7LITE0x)

64 Bytes Stack

1 Kbytes

0.5 Kbytes

Figure 5. Memory Map (ST7SUPERLITE)

Table 2. Hardware Register Map

ST7LITE0xY0, ST7LITESxY0 Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits associated with unavailable pins must always keep their reset value. 003Ah SI SICSR System Integrity C ontrol/Status Register 0xh R/W 003Bh to 007Fh Reserved area (69 bytes) Address Block Register Label Register Name Reset Status Remarks

ST7LITE0xY0, ST7LITESxY0

4 FLASH PROGRAM MEMORY

4.1 Introduction

The ST7 single voltage extended Flash (XFlash) is a non-volatile memory that can be electrically erased and programmed either on a byte-by-byte basis or up to 32 bytes in parallel. The XFlash devices can be programmed off-board (plugged in a programming tool) or on-board using In-Circuit Programming or In-Application Program- ming. The array matrix organisation allows each sector to be erased and reprogrammed without affecting other sectors.

4.2 Main Features

■ ICP (In-Circuit Programming) ■ IAP (In-Application Programming) ■ ICT (In-Circuit Testing) for downloading and executing user application test patterns in RAM ■ Sector 0 size configurable by option byte ■ Read-out and write protection

4.3 PROGRAMMING MODES

The ST7 can be programmed in three different ways: – Insertion in a programming tool. In this mode, FLASH sectors 0 and 1, option byte row and data EEPROM can be programmed or erased. – In-Circuit Programming. In this mode, FLASH sectors 0 and 1, option byte row and data EEPROM can be programmed or erased with- out removing the device from the application board. – In-Application Programming. In this mode, sector 1 and data EEPROM can be pro- grammed or erased without removing the de- vice from the application board and while the application is running.

4.3.1 In-Circuit Programming (ICP)

ICP uses a protocol called ICC (In-Circuit Commu- nication) which allows an ST7 plugged on a print- ed circuit board (PCB) to communicate with an ex- ternal programming device connected via cable. ICP is performed in three steps: Switch the ST7 to ICC mode (In-Circuit Communi- cations). This is done by driving a specific signal sequence on the ICCCLK/DATA pins while the RESET pin is pulled low. When the ST7 enters ICC mode, it fetches a specific RESET vector which points to the ST7 System Memory contain- ing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. – Download ICP Driver code in RAM from the ICCDATA pin – Execute ICP Driver code in RAM to program the FLASH memory Depending on the ICP Driver code downloaded in RAM, FLASH memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading).

4.3.2 In Application Programming (IAP)

This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode). This mode is fully controlled by user software. This allows it to be adapted to the user application, (us- er-defined strategy for entering programming mode, choice of communications protocol used to fetch the data to be stored etc.) IAP mode can be used to program any memory ar- eas except Sector 0, which is write/erase protect- ed to allow recovery in case errors occur during the programming operation.

4.4 ICC interface

1. If the ICCCLK or ICCDATA pins are only used
2. During the ICP session, the programming tool

high level (push pull output or pull-up resistor<1K). sistor>1K, no additional components are needed.

1. The use of Pin 7 of the ICC connector depends
2. Pin 9 has to be connected to the CLKIN pin of

Figure 6. Typical ICC Interface

4.5 Memory Protection

tion which can be applied individually.

4.5.1 Read out Protection

tion and against write access to Flash memory. of protection for a general purpose microcontroller. erased, and the device can be reprogrammed. through the FMP_R bit in the option byte. specified in the Option List.

4.5.2 Flash Write/Erase Protection

is no longer reprogrammable. FMP_W bit in the option byte.

4.6 Related Documentation

4.7 Register Description

Table 3. FLASH Register Map and Reset Values

00000 O P T L A T P G M

5 DATA EEPROM

5.1 INTRODUCTION

basic access protocol described in this chapter.

5.2 MAIN FEATURES

Figure 7. EEPROM Block Diagram

0 E2LAT00 0 0 0 E2PGM

5.3 MEMORY ACCESS

set by software (the E2PGM bit remains cleared). Significant Bits of the address can change. LAT bits are cleared simultaneously. It is not possible to read the latched data. This note is illustrated by the Figure 10. Figure 8. Data EEPROM Programming Flowchart

Figure 9. Data E2PROM Write Operation

5.4 POWER SAVING MODES

function in progress, and data may be corrupted.

5.5 ACCESS ERROR HANDLING

data bus will not be driven. data on the bus will not be latched.

5.6 DATA EEPROM READ-OUT PROTECTION

tion bit (see option byte section). against read-out (including a re-write protection). are protected using the same option bit. Figure 10. Data EEPROM Programming Cycle

5.7 REGISTER DESCRIPTION

Bits 7:2 = Reserved, forced by hardware to 0. Table 4. DATA EEPROM Register Map and Reset Values

000000 E 2 L A T E 2 P G M

6 CENTRAL PROCESSING UNIT

6.1 INTRODUCTION

6.2 MAIN FEATURES

6.3 CPU REGISTERS

temporary storage areas for data manipulation. (Program Counter High which is the MSB). Figure 11. CPU Registers

ST7LITE0xY0, ST7LITESxY0 CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in- structions. These bits can be individually tested and/or con- trolled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested usin g the JRH or JRNH instruc- tion. The H bit is useful in BCD arithmetic subrou- tines. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET in- structions and is tested by the JRM and JRNM in- structions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptible because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. Bit 2 = N Negative. This bit is set and cleared by hardware. It is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7 th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (that is, the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instruc- tions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and soft- ware. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. 111HINZC

ways pointing to the next free location in the stack. popped from the stack (see Figure 12). mented and the context is pushed on the stack. and the context is popped from the stack. terrupt five locations in the stack area. Figure 12. Stack Manipulation Example

ST7LITE0xY0, ST7LITESxY0

7 SUPPLY, RESET AND CLOCK MANAGEMENT

The device includes a ran ge of utility features for securing the application in critical situations (for example in case of a power brown-out), and re- ducing the number of external components. Main features ■ Clock Management – 1 MHz internal RC oscillator (enabled by op- tion byte) – External Clock Input (enabled by option byte) – PLL for multiplying the frequency by 4 or 8 (enabled by option byte) ■ Reset Sequence Manager (RSM) ■ System Integrity Management (SI) – Main supply Low voltage detection (LVD) with reset generation (enabled by option byte) – Auxiliary Voltage detector (AVD) with interrupt capability for monitoring the main supply (en- abled by option byte)

7.1 INTERNAL RC OSCILLATOR ADJUSTMENT

The ST7 contains an internal RC oscillator with an accuracy of 1% for a given device, temperature and voltage. It must be calibrated to obtain the fre- quency required in the application. This is done by software writing a calibra tion value in the RCCR (RC Control Register). Whenever the microcontroller is reset, the RCCR returns to its default value (FFh), i.e. each time the device is reset, the calibration value must be load- ed in the RCCR. Predefined calibration values are stored in EEPROM for 3.0 and 5V V DD supply volt- ages at 25°C, as shown in the following table. Notes: – See “ELECTRICAL CHARACTERISTICS” on page 81. for more information on the frequency and accuracy of the RC oscillator. – To improve clock stability and frequency accura- cy, it is recommended to place a decoupling ca- pacitor, typically 100nF, between the V DD and VSS pins as close as possible to the ST7 device. – These two bytes are systematically programmed by ST, including on FASTROM devices. Conse- quently, customers intending to us e FASTROM service must not use these two bytes. – RCCR0 and RCCR1 calibration values will be erased if the read-out protection bit is reset after it has been set. See “Read out Protection” on page 15. Caution: If the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. Refer to application note AN1324 for information on how to calibrate the RC frequency using an ex- ternal reference signal.

7.2 PHASE LOCKED LOOP

The PLL can be used to multiply a 1MHz frequen- cy from the RC oscillator or the external clock by 4 or 8 to obtain f OSC of 4 or 8 MHz. The PLL is ena- bled and the multiplication factor of 4 or 8 is select- ed by 2 option bits. – The x4 PLL is intended for operation with VDD in the 2.4V to 3.3V range – The x8 PLL is intended for operation with VDD in the 3.3V to 5.5V range Refer to Section 15.1 for the option byte descrip- tion. If the PLL is disabled and the RC oscillator is ena- bled, then fOSC = 1MHz. If both the RC oscillator and the PLL are disabled, fOSC is driven by the external clock. RCCR Conditions ST7FLITE09 Address ST7FLITE05/ ST7FLITES5 Address RCCR0 VDD=5V TA=25°C fRC=1MHz 1000h and FFDEh FFDEh RCCR1 VDD=3.0V TA=25°C fRC=700KHz 1001h and- FFDFh FFDFh

Figure 13. PLL Output Frequency Timing

13.3.4 Internal RC Oscillator and PLL)

of the LOCKED bit in the SICSR register.

7.3 REGISTER DESCRIPTION

Bits 7:2 = Reserved, must be kept cleared. and write it to this register at start-up. Table 5. Clock Register Map and Reset Values

000000 MCO SMS

Figure 14. Clock Management Block Diagram

7.4 RESET SEQUENCE MANAGER (RSM)

7.4.1 Introduction

fer to section 11.2.1 on page 53 for further details. ways kept low during the delay phase. dresses FFFEh-FFFFh in the ST7 memory map. en place from the Reset state. Figure 15. RESET Sequence Phases

256 CLOCK CYCLES

Note 1: See “Illegal Opcode Reset” on page 78. for more details on illegal opcode reset conditions.

7.4.2 Asynchronous External RESET pin

output with integrated R ON weak pull-up resistor. Electrical Characteristic section for more details. can enter reset state even in HALT mode.

7.4.3 External Power-On RESET

level specified for the selected fOSC frequency. work connected to the RESET pin.

7.4.4 Internal Low Voltage Detector (LVD)

VDD<VIT- (falling edge) as shown in Figure 17.

7.4.5 Internal Watchdog RESET

Watchdog counter overflow is shown in Figure 17. low during at least tw(RSTL)out. Figure 17. RESET Sequences

ST7LITE0xY0, ST7LITESxY0

8 INTERRUPTS

The ST7 core may be interrupted by one of two dif- ferent methods: Maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 18. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: – Normal processing is suspended at the end of the current instruction execution. – The PC, X, A and CC registers are saved onto the stack. – The I bit of the CC register is set to prevent addi- tional interrupts. – The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector address- es). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit is cleared and the main program resumes. Priority Management By default, a servicing interrupt cannot be inter- rupted because the I bit is set by hardware enter- ing in interrupt routine. In the case when several interrupts are simultane- ously pending, an hardware priority defines which one will be serviced first (see the Interrupt Map- ping Table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifi- cally mentioned interrupts allow the processor to leave the HALT low power mode (refer to the “Exit from HALT” column in th e Interrupt Mapping Ta- ble).

8.1 NON MASKABLE SOFTWARE INTERRUPT

This interrupt is entered when the TRAP instruc- tion is executed regardless of the state of the I bit. It is serviced according to the flowchart in Figure 18.

8.2 EXTERNAL INTERRUPTS

External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to le ave the HALT low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt tr iggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. Caution: The type of sensitivity defined in the Mis- cellaneous or Interrupt register (if available) ap- plies to the ei source. In case of a NANDed source (as described in the I/O ports section), a low level on an I/O pin, configured as input with interrupt, masks the interrupt request even in case of rising- edge sensitivity.

8.3 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: – The I bit of the CC register is cleared. – The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: – Writing “0” to the corresponding bit in the status register or – Access to the status register while the flag is set followed by a read or write of an associated reg- ister. Note: The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for being enabled) will therefore be lost if the clear se- quence is executed.

Figure 18. Interrupt Processing Flowchart Table 6. Interrupt Mapping

0 Not used FFFAh-FFFBh

5 Not used FFF0h-FFF1h

6 Not used FFEEh-FFEFh

7 SI AVD interrupt SICSR no FFECh-FFEDh

8 AT TIMER AT TIMER Output Compare Interrupt PWM0CSR no FFEAh-FFEBh

9 AT TIMER Overflow Interrupt ATCSR yes FFE8h-FFE9h

10 LITE TIMER LITE TIMER Input Capture Interrupt LTCSR no FFE6h-FFE7h

11 LITE TIMER RTC Interrupt LTCSR yes FFE4h-FFE5h

12 SPI SPI Peripheral Interrupts SPICSR yes FFE2h-FFE3h

13 Not used FFE0h-FFE1h

(Port B0) according to Table 7. (Port B3) according to Table 7. (Port A7) according to Table 7. (Port A0) according to Table 7.

1. These 8 bits can be written only when the I bit in
2. Changing the sensitivity of a particular external

to section “External interrupt function” on page 42. Table 7. Interrupt Sensitivity Bits

8.4 SYSTEM INTEGRITY MANAGEMENT (SI)

fer to section 12.2.1 on page 78 for further details.

8.4.1 Low Voltage Detector (LVD)

The LVD function is illustrated in Figure 19. used to ensure a proper power-on reset. will clear the watchdog flag. Figure 19. Low Voltage Detector vs Reset

Figure 20. Reset and Supply Management Block Diagram

00 LOC

8.4.2 Auxiliary Voltage Detector (AVD)

asitic detection (hysteresis). abled through the option byte.

8.4.2.1 Monitoring the VDD Main Supply

(see section 15.1 on page 112). VIT-(AVD) threshold (AVDF bit is set). Figure 21. Using the AVD to Monitor VDD

ST7LITE0xY0, ST7LITESxY0 SYSTEM INTEGRITY MANAGEMENT (Cont’d)

8.4.3 Low Power Modes

8.4.3.1 Interrupts

The AVD interrupt event generates an interrupt if the corresponding Enable Control Bit (AVDIE) is set and the interrupt mask in the CC register is re- set (RIM instruction). Mode Description WAIT No effect on SI. AVD interrupts cause the device to exit from Wait mode. HALT The SICSR register is frozen. The AVD remains active but the AVD inter- rupt cannot be used to exit from Halt mode. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt AVD event AVDF AVDIE Yes No

8.4.4 Register Description

Bit 7:4 = Reserved, must be kept cleared. PLL reaches its operating frequency. BYTE, the LVDRF bit value is undefined. This read-only bit is set and cleared by hardware. software while an external reset can not. Table 8. System Integrity Register Map and Reset Values

0000 LOCK

9 POWER SAVING MODES

9.1 INTRODUCTION

Figure 22. Power Saving Mode Transitions

9.2 SLOW MODE

the available supply voltage.

1. The CPU and peripherals are clocked at this

Figure 23. SLOW Mode Clock Transition

9.3 WAIT MODE

sumption mode by stopping the CPU. the interrupt or Reset service routine. or an Interrupt occurs, causing it to wake up. Figure 24. WAIT Mode Flow-chart

1. Before servicing an interrupt, the CC register is

256 CPU CLOCK CYCLE

9.4 ACTIVE-HALT AND HALT MODES

ister status as shown in the following table:.

9.4.1 ACTIVE-HALT MODE

struction when active halt mode is enabled. the CC register is cleared to enable interrupts. ternal or auxiliary oscillator). than a defined delay in this power saving mode. Figure 25. ACTIVE-HALT Timing Overview Figure 26. ACTIVE-HALT Mode Flow-chart

1. This delay occurs only if the MCU exits ACTIVE-

HALT mode by means of a RESET.

1. Peripherals clocked with an external clock
2. Only the Lite Timer RTC and AT Timer interrupts

can exit the MCU from ACTIVE-HALT mode.

1. Before servicing an interrupt, the CC register is

9.4.2 HALT MODE

CPU cycle delay is used to stabilize the oscillator. set vector which woke it up (see Figure 28). cluding the operation of the on-chip peripherals. tion 15.1 on page 112 for more details). Figure 27. HALT Timing Overview Figure 28. HALT Mode Flow-chart

1. WDGHALT is an option bit. See option byte sec-
2. Peripheral clocked with an external clock source
3. Only some specific interrupts can exit the MCU
4. Before servicing an interrupt, the CC register is
5. If the PLL is enabled by option byte, it outputs

ST7LITE0xY0, ST7LITESxY0 POWER SAVING MODES (Cont’d)

9.4.2.1 HALT Mode Recommendations

– Make sure that an external event is available to wake up the microcontroller from Halt mode. – When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to ex- ternal interference or by an unforeseen logical condition. – For the same reason, reinitialize the level sensi- tiveness of each external interrupt as a precau- tionary measure. – The opcode for the HALT instruction is 0x8E. To avoid an unexpected HALT instruction due to a program counter failure, it is advised to clear all occurrences of the data value 0x8E from memo- ry. For example, avoid defining a constant in ROM with the value 0x8E. – As the HALT instruction clears the I bit in the CC register to allow interrupts, the user may choose to clear all pending interrupt bits before execut- ing the HALT instruction. This avoids entering other peripheral interrupt routines after executing the external interrupt routine corresponding to the wake-up event (reset or external interrupt).

ST7LITE0xY0, ST7LITESxY0

10 I/O PORTS

10.1 INTRODUCTION

The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.

10.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers: – Data Register (DR) – Data Direction Register (DDR) and one optional register: – Option Register (OR) Each I/O pin may be programmed using the corre- sponding register bits in the DDR and OR regis- ters: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not pro- vide this register refer to the I/O Port Implementa- tion section). The generic I/O block diagram is shown in Figure 29

10.2.1 Input Modes

The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Note: Writing the DR register modifies the latch value but does not affect the pin status. External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external inter- rupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the EICR register. Each external interrupt vector is linked to a dedi- cated group of I/O port pins (see pinout description and interrupt section). If several input pins are se- lected simultaneously as interrupt source, these are logically ANDed. For this reason if one of the interrupt pins is tied low, it may mask the others. External interrupts are hardware interrupts. Fetch- ing the corresponding interrupt vector automatical- ly clears the request latch. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Spurious interrupts When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spu- rious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector input which is switched to '1' when the external interrupt is disa- bled by the OR register. To avoid this unwanted interrupt, a "safe" edge sensitivity (rising edge for enabling and falling edge for disabling) has to be selected before changing the OR register bit and configuring the appropriate sensitivity again. Caution: In case a pin level change occurs during these operations (asynchro nous signal input), as interrupts are generated according to the current sensitivity, it is advised to disable all interrupts be- fore and to reenable them after the complete pre- vious sequence in order to avoid an external inter- rupt occurring on the unwanted edge. This corresponds to the following steps: 1. To enable an external interrupt: – set the interrupt mask with the SIM instruction (in cases where a pin level change could oc- cur) – select rising edge – enable the external interrupt through the OR register – select the desired sensitivity if different from rising edge – reset the interrupt ma sk with the RIM instruc- tion (in cases where a pin level change could occur) 2. To disable an external interrupt: – set the interrupt mask with the SIM instruction SIM (in cases where a pin level change could occur) – select falling edge – disable the external interrupt through the OR register – select rising edge

ST7LITE0xY0, ST7LITESxY0 – reset the interrupt ma sk with the RIM instruc- tion (in cases where a pin level change could occur) Output Modes The output configuration is selected by setting the corresponding DDR register bit. In this case, writ- ing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR reg- ister returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status: Note: When switching from input to output mode, the DR register has to be written first to drive the correct level on the pin as soon as the port is con- figured as an output.

10.2.2 Alternate Functions

When an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. This alternate function takes priority over the standard I/O programming under the following conditions: – When the signal is coming from an on-chip pe- ripheral, the I/O pin is automatically configured in output mode (push-pull or open drain according to the peripheral). – When the signal is going to an on-chip peripher- al, the I/O pin must be configured in floating input mode. In this case, the pin state is also digitally readable by addressing the DR register. Notes: – Input pull-up configuration can cause unexpect- ed value at the input of the alternate peripheral input. – When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode. DR Push-pull Open-drain 0V SS Vss 1V DD Floating

Figure 29. I/O Port General Block Diagram Table 9. I/O Port Mode Options

Table 10. I/O Port Configurations

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,

reading the DR register will read the alternate function output status.

1. When the I/O port is in output configuration and the associated alternate function is enabled as an input,

the alternate function reads the pin status given by the DR register content.

10.3 UNUSED I/O PINS

age levels. Refer to Section 13.8.

10.4 LOW POWER MODES

10.5 INTERRUPTS

the CC register is not active (RIM instruction).

10.6 I/O PORT IMPLEMENTATION

such as spurious interrupt generation. Figure 30. Interrupt I/O Port State Transitions Table 11. Port Configuration cause the device to exit from WAIT mode. cause the device to exit from HALT mode.

Table 12. I/O Port Register Map and Reset Values

11 ON-CHIP PERIPHERALS

11.1 LITE TIMER (LT)

11.1.1 Introduction

11.1.2 Main Features

Figure 31. Lite Timer Block Diagram

ST7LITE0xY0, ST7LITESxY0 LITE TIMER (Cont’d)

11.1.3 Functional Description

The value of the 8-bit counter cannot be read or written by software. After an MCU reset, it starts incrementing from 0 at a frequency of f OSC/32. A counter overflow event occurs when the counter rolls over from F9h to 00h. If f OSC = 8 MHz, then the time period between two counter overflow events is 1 ms. This period can be doubled by set- ting the TB bit in the LTCSR register. When the timer overflows, the TBF bit is set by hardware and an interrupt request is generated if the TBIE is set. The TBF bit is cleared by software reading the LTCSR register.

11.1.3.1 Watchdog

The watchdog is enabled using the WDGE bit. The normal Watchdog timeout is 2ms (@ = 8 MHz f OSC), after which it then generates a reset. To prevent this watchdog reset occuring, software must set the WDGD bit. The WDGD bit is cleared by hardware after t WDG. This means that software must write to the WDGD bit at regular intervals to prevent a watchdog reset occurring. Refer to Fig- ure 32. If the watchdog is not enabled immediately after reset, the first watchd og timeout will be shorter than 2ms, because this period is counted starting from reset. Moreover, if a 2ms period has already elapsed after the last MCU reset, the watchdog re- set will take place as soon as the WDGE bit is set. For these reasons, it is recommended to enable the Watchdog immediately after reset or else to set the WDGD bit before the WGDE bit so a watchdog reset will not occur for at least 2ms. A Watchdog reset can be forced at any time by setting the WDGRF bit. To generate a forced watchdog reset, first watchdog has to be activated by setting the WDGE bit and then the WDGRF bit has to be set. The WDGRF bit also acts as a flag, indicating that the Watchdog was the source of the reset. It is au- tomatically cleared after it has been read. Caution: When the WDGRF bit is set, software must clear it, otherwise the next time the watchdog is enabled (by hardware or software), the micro- controller will be immediately reset. Hardware Watchdog Option If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGE bit in the LTCSR is not used. Refer to the Option Byte description in the "device configuration and ordering information" section. Using Halt Mode with the Watchdog (option) If the Watchdog reset on HALT option is not se- lected by option byte, the Halt mode can be used when the watchdog is enabled. In this case, the HALT instruction stops the oscilla- tor. When the oscillator is stopped, the Lite Timer stops counting and is no longer able to generate a Watchdog reset until the microcontroller receives an external interrupt or a reset. If an external interrupt is received, the WDG re- starts counting after 256 CPU clocks. If a reset is generated, the Watchdog is disabled (reset state). If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT instruction), it is recommended before executing the HALT instruc- tion to refresh the WDG counter, to avoid an unex- pected WDG reset immediately after waking up the microcontroller.

Figure 32. Watchdog Timing Diagram

contains the value of the free-running upcounter. ICF bit is cleared by reading the LTICR register. capture is inhibited if the ICF bit is set.

11.1.4 Low Power Modes

11.1.5 Interrupts

Figure 33. Input Capture Timing Diagram

11.1.6 Register Description

This bit is set and cleared by software. does not change the bit value. This bit is set and cleared by software. This bit is set and cleared by software. after a read access to the LTCSR register. 0: No watchdog reset occurred. This bit is set and cleared by software. Table 13. Lite Timer Register Map and Reset Values

11.2.1 Introduction

11.2.2 Main Features

Figure 34. Block Diagram

11.2.3 Functional Description

PWM0CSR description on page 57). the counter period and the ATR register value. At reset, the counter starts counting from 0. DCRx value the PWM0 signals is set to a low level. Figure 35. PWM Function

Figure 36. PWM Signal Example out waiting for an OVF event). ble for DCRx values other than 0 (reset value).

11.2.4 Low Power Modes

11.2.5 Interrupts

1. The interrupt events are connected to separate

interrupt vectors (see Interrupts chapter). CC register is reset (RIM instruction).

ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d)

11.2.6 Register Description

TIMER CONTROL STATUS REGISTER (ATC- SR) Read / Write Reset Value: 0000 0000 (00h) Bit 7:5 = Reserved, must be kept cleared. Bit 4:3 = CK[1:0] Counter Clock Selection. These bits are set and cleared by software and cleared by hardware after a reset. They select the clock frequency of the counter. Bit 2 = OVF Overflow Flag. This bit is set by hardware and cleared by software by reading the ATCSR register. It indicates the transition of the counter from FFFh to ATR value. 0: No counter overflow occurred 1: Counter overflow occurred Caution: When set, the OVF bit stays high for 1 f COUNTER cycle, (up to 1ms depending on the clock selec- tion). Bit 1 = OVFIE Overflow Interrupt Enable. This bit is read/write by software and cleared by hardware after a reset. 0: OVF interrupt disabled 1: OVF interrupt enabled Bit 0 = CMPIE Compare Interrupt Enable. This bit is read/write by software and clear by hardware after a reset. It allows to mask the inter- rupt generation when CMPF bit is set. 0: CMPF interrupt disabled 1: CMPF interrupt enabled COUNTER REGISTER HIGH (CNTRH) Read only Reset Value: 0000 0000 (00h) COUNTER REGISTER LOW (CNTRL) Read only Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved, must be kept cleared. Bits 11:0 = CNTR[11:0] Counter Value. This 12-bit register is read by software and cleared by hardware after a reset. The counter is incre- mented continuously as soon as a counter clock is selected. To obtain the 12-bit value, software should read the counter value in two consecutive read operations. The CNTRH register can be in- cremented between the two reads, and in order to be accurate when f TIMER=fCPU, the software should take this into account when CNTRL and CNTRH are read. If CNTRL is close to its highest value, CNTRH could be incremented before it is read. When a counter overflow occurs, the counter re- starts from the value specified in the ATR register. 0 0 0 CK1 CK0 OVF OVFIE CMPIE Counter Clock Selection CK1 CK0 OFF 0 0 fLTIMER (1 ms timebase @ 8 MHz) 0 1 fCPU 10 Reserved 1 1 15 8 0 0 0 0 CN11 CN10 CN9 CN8 CN7 CN6 CN5 CN4 CN3 CN2 CN1 CN0

ST7LITE0xY0, ST7LITESxY0 12-BIT AUTORELOAD TIMER (Cont’d) AUTO RELOAD REGISTER (ATRH) Read / Write Reset Value: 0000 0000 (00h) AUTO RELOAD REGISTER (ATRL) Read / Write Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved, must be kept cleared. Bits 11:0 = ATR[11:0] Autoreload Register. This is a 12-bit register which is written by soft- ware. The ATR register value is automatically loaded into the upcounter when an overflow oc- curs. The register value is used to set the PWM frequency. PWM0 DUTY CYCLE REGISTER HIGH (DCR0H) Read / Write Reset Value: 0000 0000 (00h) PWM0 DUTY CYCLE REGISTER LOW (DCR0L) Read / Write Reset Value: 0000 0000 (00h) Bits 15:12 = Reserved, must be kept cleared. Bits 11:0 = DCR[11:0] PWMx Duty Cycle Value This 12-bit value is written by software. The high register must be written first. In PWM mode (OE0=1 in the PWMCR register) the DCR[11:0] bits define the duty cycle of the PWM0 output signal (see Figure 35 ). In Output Compare mode, (OE0=0 in the PWMCR register) they define the value to be compared with the 12- bit upcounter value. PWM0 CONTROL/STATUS REGISTER (PWM0CSR) Read / Write Reset Value: 0000 0000 (00h) Bit 7:2= Reserved, must be kept cleared. Bit 1 = OP0 PWM0 Output Polarity. This bit is read/write by software and cleared by hardware after a reset. This bit selects the polarity of the PWM0 signal. 0: The PWM0 signal is not inverted. 1: The PWM0 signal is inverted. Bit 0 = CMPF0 PWM0 Compare Flag. This bit is set by hardware and cleared by software by reading the PWM0CSR register. It indicates that the upcounter value matches the DCR0 regis- ter value. 0: Upcounter value does not match DCR value. 1: Upcounter value matches DCR value. 15 8 0 0 0 0 ATR11 ATR10 ATR9 ATR8 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 15 8 0 0 0 0 DCR11 DCR10 DCR9 DCR8 DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0

000000 O P 0 C M P F 0

Bits 7:1 = Reserved, must be kept cleared. Bit 0 = OE0 PWM0 Output enable. This bit is set and cleared by software. Table 14. Register Map and Reset Values

0000000 O E 0

10 ATRH

11 ATRL

12 PWMCR

13 PWM0CSR

17 DCR0H

18 DCR0L

11.3 SERIAL PERIPHERAL INTERFACE (SPI)

11.3.1 Introduction

11.3.2 Main Features

initiate the next transmission sequence.

11.3.3 General Description

ard I/O ports on the master MCU. Figure 37. Serial Peripheral Interface Block Diagram

11.3.3.1 Functional Description

slave (most significant bit first). the master device via the SCK pin). simplex communication is possible). must be programmed with the same timing mode. Figure 38. Single Master/ Single Slave Application

11.3.3.2 Slave Select Management

shift register (see Section 11.3.5.3). Figure 39. Generic SS Timing Diagram Figure 40. Hardware/Software Slave Select Management

ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d)

11.3.3.3 Master Mode Operation

In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). Note: The idle state of SCK must correspond to the polarity selected in the SPICSR register (by pulling up SCK if CPOL=1 or pulling down SCK if CPOL=0). How to operate the SPI in master mode To operate the SPI in master mode, perform the following steps in order: 1. Write to the SPICR register: – Select the clock frequency by configuring the SPR[2:0] bits. – Select the clock polarity and clock phase by configuring the CPOL and CPHA bits. Figure 41 shows the four possible configurations. Note: The slave must have the same CPOL and CPHA settings as the master. 2. Write to the SPICSR register: – Either set the SSM bit and set the SSI bit or clear the SSM bit and tie the SS pin high for the complete byte transmit sequence. 3. Write to the SPICR register: – Set the MSTR and SPE bits Note: MSTR and SPE bits remain set only if SS is high. Important note: if the SPICSR register is not writ- ten first, the SPICR register setting (MSTR bit) may be not taken into account. The transmit sequence begins when software writes a byte in the SPIDR register.

11.3.3.4 Master Mode Transmit Sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MOSI pin most sig- nificant bit first. When data transfer is complete: – The SPIF bit is set by hardware – An interrupt request is generated if the SPIE bit is set and the interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICSR register while the SPIF bit is set 2. A read to the SPIDR register. Note: While the SPIF bit is se t, all writes to the SPIDR register are inhibited until the SPICSR reg- ister is read.

11.3.3.5 Slave Mode Operation

In slave mode, the serial clock is received on the SCK pin from the master device. To operate the SPI in slave mode: 1. Write to the SPICSR register to perform the fol- lowing actions: – Select the clock polarity and clock phase by configuring the CPOL and CPHA bits (see Figure 41). Note: The slave must have the same CPOL and CPHA settings as the master. – Manage the SS pin as described in Section 11.3.3.2 and Figure 39. If CPHA=1 SS must be held low continuously. If CPHA=0 SS must be held low during byte transmission and pulled up between each byte to let the slave write in the shift register. 2. Write to the SPICR register to clear the MSTR bit and set the SPE bit to enable the SPI I/O functions.

11.3.3.6 Slave Mode Transmit Sequence

When software writes to the SPIDR register, the data byte is loaded into the 8-bit shift register and then shifted out serially to the MISO pin most sig- nificant bit first. The transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its MOSI pin. When data transfer is complete: – The SPIF bit is set by hardware – An interrupt request is generated if SPIE bit is set and interrupt mask in the CCR register is cleared. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SPICS R register while the SPIF bit is set. 2. A write or a read to the SPIDR register. Notes: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR reg- ister is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see Section 11.3.5.2).

11.3.4 Clock Phase and Clock Polarity

master and the slave device. Figure 41. Data Clock Timing Diagram Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.

11.3.5 Error Flags

11.3.5.1 Master Mode Fault (MODF)

quest is generated if the SPIE bit is set.

1. A read access to the SPICSR register while the
2. A write to the SPICR register.

inal state during or after this clearing sequence. the MODF bit clearing sequence.

11.3.5.2 Overrun Condition (OVR)

generated if the SPIE bit is set.

11.3.5.3 Write Collision Error (WCOL)

and the software write will be unsuccessful. is set (the WCOL bit is a status flag only). Figure 42. Clearing the WCOL bit (Write Collision Flag) Software Sequence

11.3.5.4 Single Master Systems

that time, thus disabling the slave devices. Figure 43. Single Master / Multiple Slave Configuration

ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d)

11.3.6 Low Power Modes

11.3.6.1 Using the SPI to wakeup the MCU from

In slave configuration, the SPI is able to wakeup the ST7 device from HALT mode through a SPIF interrupt. The data received is subsequently read from the SPIDR register when the software is run- ning (interrupt vector fetch). If multiple data trans- fers have been performed before software clears the SPIF bit, then the OVR bit is set by hardware. Note: When waking up from Halt mode, if the SPI remains in Slave mode, it is recommended to per- form an extra communications cycle to bring the SPI from Halt mode state to normal state. If the SPI exits from Slave mode, it returns to normal state immediately. Caution: The SPI can wake up the ST7 from Halt mode only if the Slave Select signal (external SS pin or the SSI bit in the SPICSR register) is low when the ST7 enters Halt mode. So if Slave selec- tion is configured as external (see Section 11.3.3.2), make sure the master drives a low level on the SS pin when the slave enters Halt mode.

11.3.7 Interrupts

Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). Mode Description WAIT No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. HALT SPI registers are frozen. In HALT mode, the SPI is inactive. SPI oper- ation resumes when the MCU is woken up by an interrupt with “exit from HALT mode” ca- pability. The data received is subsequently read from the SPIDR register when the soft- ware is running (interrupt vector fetching). If several data are received before the wake- up event, then an overrun error is generated. This error can be detected after the fetch of the interrupt routine that woke up the device. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt SPI End of Trans- fer Event SPIF SPIE Yes Yes Master Mode Fault Event MODF Yes No Overrun Error OVR Yes No

11.3.8 Register Description

Bit 7 = SPIE Serial Peripheral Interrupt Enable. This bit is set and cleared by software. Bit 6 = SPE Serial Peripheral Output Enable. Bit 5 = SPR2 Divider Enable. Note: This bit has no effect in slave mode. tions of the MISO and MOSI pins are reversed. Bit 3 = CPOL Clock Polarity. This bit is set and cleared by software. CPHA settings as the master. Bits 1:0 = SPR[1:0] Serial Clock Frequency. Note: These 2 bits have no effect in slave mode. Table 15. SPI Master mode SCK Frequency

ST7LITE0xY0, ST7LITESxY0 SERIAL PERIPHERAL INTERFACE (Cont’d) CONTROL/STATUS REGISTER (SPICSR) Read/Write (some bits Read Only) Reset Value: 0000 0000 (00h) Bit 7 = SPIF Serial Peripheral Data Transfer Flag (Read only). This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the SPICR register. It is cleared by a software sequence (an access to the SPICSR register followed by a write or a read to the SPIDR register). 0: Data transfer is in progress or the flag has been cleared. 1: Data transfer between the device and an exter- nal device has been completed. Note: While the SPIF bit is se t, all writes to the SPIDR register are inhibited until the SPICSR reg- ister is read. Bit 6 = WCOL Write Collision status (Read only). This bit is set by hardware when a write to the SPIDR register is done during a transmit se- quence. It is cleared by a software sequence (see Figure 42). 0: No write collision occurred 1: A write collision has been detected Bit 5 = OVR SPI Overrun error (Read only). This bit is set by hardware when the byte currently being received in the shift register is ready to be transferred into the SPIDR register while SPIF = 1 (See Section 11.3.5.2). An interrupt is generated if SPIE = 1 in the SPICR register. The OVR bit is cleared by software reading the SPICSR register. 0: No overrun error 1: Overrun error detected Bit 4 = MODF Mode Fault flag (Read only). This bit is set by hardware when the SS pin is pulled low in master mode (see Section 11.3.5.1 Master Mode Fault (MODF)). An SPI interrupt can be generated if SPIE=1 in the SPICR register. This bit is cleared by a software sequence (An access to the SPICSR register while MODF=1 followed by a write to the SPICR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bit 3 = Reserved, must be kept cleared. Bit 2 = SOD SPI Output Disable. This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode) 0: SPI output enabled (if SPE=1) 1: SPI output disabled Bit 1 = SSM SS Management. This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS pin and uses the SSI bit value instead. See Section 11.3.3.2 Slave Select Management. 0: Hardware management (SS managed by exter- nal pin) 1: Software management (internal SS signal con- trolled by SSI bit. External SS pin free for gener- al-purpose I/O) Bit 0 = SSI SS Internal Mode. This bit is set and cleared by software. It acts as a ‘chip select’ by controlling the level of the SS slave select signal when the SSM bit is set. 0 : Slave selected 1 : Slave deselected DATA I/O REGISTER (SPIDR) Read/Write Reset Value: Undefined The SPIDR register is used to transmit and receive data on the serial bus. In a master device, a write to this register will init iate transmission/reception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. Warning: A write to the SPIDR register places data directly into the shift register for transmission. A read to the SPIDR register returns the value lo- cated in the buffer and not the content of the shift register (see Figure 37). SPIF WCOL OVR MODF - SOD SSM SSI D7 D6 D5 D4 D3 D2 D1 D0

Table 16. SPI Register Map and Reset Values

31 SPIDR

32 SPICR

33 SPICSR

ST7LITE0xY0, ST7LITESxY0 11.4 8-BIT A/D CONVERTER (ADC)

11.4.1 Introduction

The on-chip Analog to Digital Converter (ADC) pe- ripheral is a 8-bit, succ essive approximation con- verter with internal sample and hold circuitry. This peripheral has up to 5 multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from up to 5 different sources. The result of the conversion is stored in a 8-bit Data Register. The A/D converter is controlled through a Control/Status Register.

11.4.2 Main Features

■ 8-bit conversion ■ Up to 5 channels with multiplexed input ■ Linear successive approximation ■ Dual input range –0 t o VDD or – 0V to 250mV ■ Data register (DR) which contains the results ■ Conversion complete status flag ■ On/off bit (to reduce consumption) ■ Fixed gain operational amplifier (x8) (not available on ST7LITES5 devices)

11.4.3 Functional Description

11.4.3.1 Analog Power Supply

The block diagram is shown in Figure 44. VDD and VSS are the high and low level reference voltage pins. Conversion accuracy may therefore be impacted by voltage drops and noise in the event of heavily loaded or badly decoupled power supply lines. For more details, refer to the Electrical character- istics section.

11.4.3.2 Input Voltage Amplifier

The input voltage can be amplified by a factor of 8 by enabling the AMPSEL bit in the ADAMP regis- ter. When the amplifier is enabled, the input range is 0V to 250 mV. For example, if V DD = 5V, then the ADC can con- vert voltages in the range 0V to 250mV with an ideal resolution of 2.4mV (equivalent to 11-bit res- olution with reference to a V SS to VDD range). For more details, refer to the Electrical character- istics section. Note: The amplifier is switched on by the ADON bit in the ADCCSR register, so no additional start- up time is required when the amplifier is selected by the AMPSEL bit.

Figure 44. ADC Block Diagram

11.4.3.3 Digital A/D Conversion Result

and never increases if the analog input does not. scale) without overflow indication. version result in the DR register is 00h. the conversion is stored in the ADCDR register.

11.4.3.4 A/D Conversion Phases

analog to digital conversion accuracy. pin in case of single input channel measurement.

11.4.3.5 Software Procedure

tions and to Figure 45 for the timings. sion of the selected channel. – The EOC bit is set by hardware. – No interrupt is generated. valid until the next conversion has ended. and starts a new conversion. Figure 45. ADC Conversion Timings

11.4.4 Low Power Modes

and between single shot conversions.

11.4.5 Interrupts

curate conversions can be performed.

ST7LITE0xY0, ST7LITESxY0 8-BIT A/D CONVERTER (ADC) (Cont’d)

11.4.6 Register Description

CONTROL/STATUS REGISTER (ADCCSR) Read/Write Reset Value: 0000 0000 (00h) Bit 7 = EOC Conversion Complete This bit is set by hardware. It is cleared by soft- ware reading the result in the DR register or writing to the CSR register. 0: Conversion is not complete 1: Conversion can be read from the DR register Bit 6 = SPEED ADC clock selection This bit is set and cleared by software. It is used together with the SLOW bit to configure the ADC clock speed. Refer to the table in the SLOW bit de- scription. Bit 5 = ADON A/D Converter and Amplifier On This bit is set and cleared by software. 0: A/D converter and amplifier are switched off 1: A/D converter and amplifier are switched on Note: Amplifier not available on ST7LITES5 devices Bits 4:3 = Reserved. must always be cleared. Bits 2:0 = CH[2:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert. Notes: 1. The number of pins AND the channel selection varies according to the device. Refer to the device pinout. 2. A write to the ADCCSR register (with ADON set) aborts the current conversion, resets the EOC bit and starts a new conversion. DATA REGISTER (ADCDR) Read Only Reset Value: 0000 0000 (00h) Bits 7:0 = D[7:0] Analog Converted Value This register contains the converted analog value in the range 00h to FFh. Note: Reading this register reset the EOC flag. AMPLIFIER CONTROL REGISTER (ADCAMP) Read/Write Reset Value: 0000 0000 (00h) Bit 7:4 = Reserved. Forced by hardware to 0. Bit 3 = SLOW Slow mode This bit is set and cleared by software. It is used together with the SPEED bit to configure the ADC clock speed as shown on the table below. Bit 2 = AMPSEL Amplifier Selection Bit This bit is set and cleared by software. For ST7LITES5 devices, this bit must be kept at its re- set value (0). 0: Amplifier is not selected 1: Amplifier is selected Note: When AMPSEL=1 it is mandatory that f ADC be less than or equal to 2 MHz. Bits 1:0 = Reserved. Forced by hardware to 0. Note: If ADC settings are changed by writing the ADCAMP register while the ADC is running, a dummy conversion is needed before obtaining re- sults with the new settings. EOC SPEED ADON 0 0 CH2 CH1 CH0 Channel Pin1 CH2 CH1 CH0 AIN0 0 0 0 AIN1 0 0 1 AIN2 0 1 0 AIN3 0 1 1 AIN4 1 0 0 D7 D6 D5 D4 D3 D2 D1 D0

0000 S L O W AMP-

Table 17. ADC Register Map and Reset Values

12 INSTRUCTION SET

12.1 ST7 ADDRESSING MODES

Table 18. ST7 Addressing Mode Overview

1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx.

ST7LITE0xY0, ST7LITESxY0 ST7 ADDRESSING MODES (cont’d)

12.1.1 Inherent

All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation.

12.1.2 Immediate

Immediate instructions have 2 bytes, the first byte contains the opcode, the second byte contains the operand value.

12.1.3 Direct

In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two sub- modes: Direct (Short) The address is a byte, thus requires only 1 byte af- ter the opcode, but only allows 00 - FF addressing space. Direct (Long) The address is a word, thus allowing 64 Kbyte ad- dressing space, but requires 2 bytes after the op- code.

12.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three submodes: Indexed (No Offset) There is no offset (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE addressing space. Indexed (Long) The offset is a word, thus allowing 64 Kbyte ad- dressing space and requires 2 bytes after the op- code.

12.1.5 Indirect (Short, Long)

The required data byte to do the operation is found by its memory address, located in memory (point- er). The pointer address follows the opcode. The indi- rect addressing mode consists of two submodes: Indirect (Short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (Long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Inherent Instruction Function NOP No operation TRAP S/W Interrupt WFI Wait For Interrupt (Low Power Mode) HALT Halt Oscillator (Lowest Power Mode) RET Subroutine Return IRET Interrupt Subroutine Return SIM Set Interrupt Mask RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement MUL Byte Multiplication SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles Immediate Instruction Function LD Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations

12.1.6 Indirect Indexed (Short, Long)

er address follows the opcode. and requires 1 byte after the opcode. and requires 1 byte after the opcode. Table 19. Instructions Supporting Direct,

12.1.7 Relative Mode (Direct, Indirect)

register value by adding an 8-bit signed offset to it. The offset follows the opcode.

ST7LITE0xY0, ST7LITESxY0

12.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Using a prebyte The instructions are described with 1 to 4 bytes. In order to extend the number of available op- codes for an 8-bit CPU (256 opcodes), three differ- ent prebyte opcodes are defined. These prebytes modify the meaning of the instruction they pre- cede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, di- rect bit or direct relative addressing mode to an instruction using the corre- sponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruc- tion using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one.

12.2.1 Illegal Opcode Reset

In order to provide enhanced robustness to the de- vice against unexpected behavior, a system of ille- gal opcode detection is implemented. If a code to be executed does not correspond to any opcode or prebyte value, a reset is generated. This, com- bined with the Watchdog, allows the detection and recovery from an unexpected fault or interference. Note: A valid prebyte associated with a valid op- code forming an unauthorized combination does not generate a reset. Load and Transfer LD CLR Stack operation PUSH POP RSP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Condition Code Flag modification SIM RIM SCF RCF

ST7LITE0xY0, ST7LITESxY0 INSTRUCTION GROUPS (cont’d) Mnemo Description Function/Example Dst Src H I N Z C ADC Add with Carry A = A + M + C A M H N Z C ADD Addition A = A + M A M H N Z C AND Logical And A = A . M A M N Z BCP Bit compare A, Memory tst (A . M) A M N Z BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call subroutine CALLR Call subroutine relative CLR Clear reg, M 0 1 CP Arithmetic Compare tst(Reg - M) reg M N Z C CPL One Complement A = FFH-A reg, M N Z 1 DEC Decrement dec Y reg, M N Z HALT Halt 0 IRET Interrupt routine return Pop CC, A, X, PC H I N Z C INC Increment inc X reg, M N Z JRA Jump relative always JRT Jump relative JRF Never jump jrf * JRIH Jump if ext. interrupt = 1 JRIL Jump if ext. interrupt = 0 JRH Jump if H = 1 H = 1 ? JRNH Jump if H = 0 H = 0 ? JRM Jump if I = 1 I = 1 ? JRNM Jump if I = 0 I = 0 ? JRMI Jump if N = 1 (minus) N = 1 ? JRPL Jump if N = 0 (plus) N = 0 ? JREQ Jump if Z = 1 (equal) Z = 1 ? JRNE Jump if Z = 0 (not equal) Z = 0 ? JRC Jump if C = 1 C = 1 ? JRNC Jump if C = 0 C = 0 ? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= JRUGT Jump if (C + Z = 0) Unsigned >

ST7LITE0xY0, ST7LITESxY0 INSTRUCTION GROUPS (cont’d) Mnemo Description Function/Example Dst Src H I N Z C JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg N Z MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0 NEG Negate (2's compl) neg $10 reg, M N Z C NOP No Operation OR OR operation A = A + M A M N Z POP Pop from the Stack pop reg reg M pop CC CC M H I N Z C PUSH Push onto the Stack push Y M reg, CC RCF Reset carry flag C = 0 0 RET Subroutine Return RIM Enable Interrupts I = 0 0 RLC Rotate left true C C <= Dst <= C reg, M N Z C RRC Rotate right true C C => Dst => C reg, M N Z C RSP Reset Stack Pointer S = Max allowed SBC Subtract with Carry A = A - M - C A M N Z C SCF Set carry flag C = 1 1 SIM Disable Interrupts I = 1 1 SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C SLL Shift left Logic C <= Dst <= 0 reg, M N Z C SRL Shift right Logic 0 => Dst => C reg, M 0 Z C SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C SUB Subtraction A = A - M A M N Z C SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z TNZ Test for Neg & Zero tnz lbl1 N Z TRAP S/W trap S/W interrupt 1 WFI Wait for Interrupt 0 XOR Exclusive OR A = A XOR M A M N Z

13 ELECTRICAL CHARACTERISTICS

13.1 PARAMETER CONDITIONS

13.1.1 Minimum and Maximum values

times the standard deviation (mean±3Σ).

13.1.2 Typical values

as design guidelines and are not tested.

13.1.3 Typical curves

given only as design guidelines and are not tested.

13.1.4 Loading capacitor

measurement are shown in Figure 46. Figure 46. Pin loading conditions

13.1.5 Pin input voltage

vice is described in Figure 47. Figure 47. Pin input voltage

ST7LITE0xY0, ST7LITESxY0

13.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

13.2.1 Voltage Characteristics

13.2.2 Current Characteristics

13.2.3 Thermal Characteristics

Notes: 1. Directly connecting the I/O pins to VDD or VSS could damage the device if an unexpected change of the I/O configura- tion occurs (for example, due to a co rrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration. For reset pin, please refer to Figure 80. 2. IINJ(PIN) must never be exceeded. This is implicitly insured if V IN maximum is respected. If V IN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. 3. All power (VDD) and ground (VSS) lines must always be connected to the external supply. 4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken: - Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage is lower than the specified limits) - Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as far as possible from the analog input pins. 5. No negative current injection allowed on PB1 pin. 6. When several inputs are submitted to a current injection, the maximum ΣI INJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maxi- mum current injection on four I/O port pins of the device. Symbol Ratings Maximum value Unit VDD - VSS Supply voltage 7.0 V VIN Input voltage on any pin 1) & 2) VSS-0.3 to VDD+0.3 VESD(HBM) Electrostatic discharge voltage (Human Body Model) see section 13.7.2 on page 93 Symbol Ratings Maximum value Unit IVDD Total current into VDD power lines (source) 3) 75 mA IVSS Total current out of VSS ground lines (sink) 3) 150 IIO Output current sunk by any standard I/O and control pin 20 Output current sunk by any high sink I/O pin 40 Output current source by any I/Os and control pin - 25 IINJ(PIN) 2) & 4) Injected current on RESET pin ± 5 Injected current on PB1 pin 5) +5 Injected current on any other pin 6) ± 5 ΣIINJ(PIN) 2) Total injected current (sum of all I/O and control pins) 6) ± 20 Symbol Ratings Value Unit TSTG Storage temperature range -65 to +150 °C TJ Maximum junction temperature (see Section 14.2 THERMAL CHARACTERISTICS)

13.3 OPERATING CONDITIONS

13.3.1 General Operating Conditions: Suffix 6 Devices

TA = -40 to +85°C unless otherwise specified. Figure 48. fCLKIN Maximum Operating Frequency Versus VDD Supply Voltage

ST7LITE0xY0, ST7LITESxY0

13.3.2 Operating Conditions with Low Voltage Detector (LVD)

TA = -40 to 85°C, unless otherwise specified Notes: 1. Not tested in production. 2. Not tested in production. The VDD rise time rate condition is needed to ensure a correct device power-on and LVD reset. When the VDD slope is outside these values, the LVD may not ensure a proper reset of the MCU.

13.3.3 Auxiliary Voltage Detector (AVD) Thresholds

TA = -40 to 85°C, unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit VIT+(LVD) Reset release threshold (VDD rise) High Threshold Med. Threshold Low Threshold 4.00 3.40 1) 2.65 1) 4.25 3.60 2.90 4.50 3.80 3.15 V V IT-(LVD) Reset generation threshold (VDD fall) High Threshold Med. Threshold Low Threshold 3.80 3.20 2.40 4.05 3.40 2.70 4.30 3.65 1) 2.90 1) Vhys LVD voltage threshold hysteresis V IT+(LVD)-VIT-(LVD) 200 mV VtPOR VDD rise time rate 2) 20 20000 µs/V tg(VDD) Filtered glitch delay on VDD Not detected by the LVD 150 ns IDD(LVD) LVD/AVD current consumption 220 µA Symbol Parameter Conditions Min Typ Max Unit VIT+(AVD) 1=>0 AVDF flag toggle threshold (VDD rise) High Threshold Med. Threshold Low Threshold 4.40 3.90 3.20 4.70 4.10 3.40 5.00 4.30 3.60 V V IT-(AVD) 0=>1 AVDF flag toggle threshold (VDD fall) High Threshold Med. Threshold Low Threshold 4.30 3.70 2.90 4.60 3.90 3.20 4.90 4.10 3.40 Vhys AVD voltage threshold hysteresis V IT+(AVD)-VIT-(AVD) 150 mV ∆VIT- Voltage drop between AVD flag set and LVD reset activation VDD fall 0.45 V

ST7LITE0xY0, ST7LITESxY0

13.3.4 Internal RC Oscillator and PLL

The ST7 internal clock can be supplied by an internal RC oscillator and PLL (selectable by option byte). The RC oscillator and PLL characteristics are temperature-dependent and are grouped in two tables. Notes: 1. If the RC oscillator clock is select ed, to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. 2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 24 3. Data based on characterization results, not tested in production 4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy 5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 13 on page 25. 6. Guaranteed by design. Symbol Parameter Conditions Min Typ Max Unit VDD(RC) Internal RC Oscillator operating voltage 2.4 5.5 VVDD(x4PLL) x4 PLL operating voltage 2.4 3.3 VDD(x8PLL) x8 PLL operating voltage 3.3 5.5 tSTARTUP PLL Startup time 60 PLL input clock (fPLL) cycles Symbol Parameter Conditions Min Typ Max Unit fRC 1) Internal RC oscillator fre- quency RCCR = FF (reset value), TA=25°C, VDD=5V 760 kHzRCCR = RCCR02 ),TA=25°C, VDD=5V 1000 ACCRC Accuracy of Internal RC oscillator with RCCR=RCCR0 TA=25°C,VDD=4.5 to 5.5V -1 +1% TA=-40 to +85°C, VDD=5V -5 +2 % TA=0 to +85°C, VDD=4.5 to 5.5V -2 3) +23) % IDD(RC) RC oscillator current con- sumption TA=25°C,VDD=5V 970 3) µA tsu(RC) RC oscillator setup time T A=25°C,VDD=5V 10 2) µs fPLL x8 PLL input clock 1 3) MHz tLOCK PLL Lock time5) 2m s tSTAB PLL Stabilization time5) 4m s ACCPLL x8 PLL Accuracy fRC = 1MHz@TA=25°C, VDD=4.5 to 5.5V 0.1 4) % fRC = 1MHz@TA=-40 to +85°C, VDD=5V 0.1 4) % tw(JIT) PLL jitter period f RC = 1MHz 8 6) kHz JITPLL PLL jitter (∆fCPU/fCPU)1 6) % IDD(PLL) PLL current consumption T A=25°C 600 3) µA

ST7LITE0xY0, ST7LITESxY0 OPERATING CONDITIONS (Cont’d) Notes: 1. If the RC oscillator clock is select ed, to improve clock stability and frequency accuracy, it is recommended to place a decoupling capacitor, typically 100nF, between the VDD and VSS pins as close as possible to the ST7 device. 2. See “INTERNAL RC OSCILLATOR ADJUSTMENT” on page 24. 3. Data based on characterization results, not tested in production 4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy 5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 13 on page 25. 6. Guaranteed by design. Symbol Parameter Conditions Min Typ Max Unit fRC 1) Internal RC oscillator fre- quency RCCR = FF (reset value), TA=25°C, VDD= 3.0V 560 kHzRCCR=RCCR12) ,TA=25°C, VDD= 3V 700 ACCRC Accuracy of Internal RC oscillator when calibrated with RCCR=RCCR12)3) TA=25°C,VDD=3V -2 +2 % TA=25°C,VDD=2.7 to 3.3V -25 +25 % TA=-40 to +85°C, VDD=3V -15 15 % IDD(RC) RC oscillator current con- sumption TA=25°C,VDD=3V 700 3) µA tsu(RC) RC oscillator setup time T A=25°C,VDD=3V 10 2) µs fPLL x4 PLL input clock 0.7 3) MHz tLOCK PLL Lock time5) 2m s tSTAB PLL Stabilization time5) 4m s ACCPLL x4 PLL Accuracy fRC = 1MHz@TA=25°C, VDD=2.7 to 3.3V 0.1 4) % fRC = 1MHz@TA=40 to +85°C, VDD= 3V 0.1 4) % tw(JIT) PLL jitter period f RC = 1MHz 8 6) kHz JITPLL PLL jitter (∆fCPU/fCPU)1 6) % IDD(PLL) PLL current consumption T A=25°C 190 3) µA

13.4 SUPPLY CURRENT CHARACTERISTICS

13.4.1 Supply Current

1. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals

in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

1. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)

driven by external square wave, LVD disabled.

1. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in i nput mode with a static value at V DD or

VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

1. SLOW-WAIT mode selected with f CPU based on f OSC divided by 32. All I/O pins in input mode with a static value at

VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.

1. All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results,

tested in production at VDD max and fCPU max. Figure 56. Typical IDD in RUN vs. fCPU Figure 57. Typical IDD in SLOW vs. fCPU

Figure 58. Typical IDD in WAIT vs. fCPU Figure 59. Typical IDD in SLOW-WAIT vs. fCPU Figure 60. Typical IDD vs. Temperature

13.4.2 On-chip peripherals

1. Data based on a differential IDD measurement between reset configuration (timer stopped) and a timer running in PWM
2. Data based on a differential IDD measurement between reset configuration and a permanent SPI master communica-

tion (data sent equal to 55h).

1. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions with am-

13.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for VDD, fOSC, and TA.

13.5.1 General Timings

13.5.2 External Clock Source

1. Guaranteed by Design. Not tested in production.
2. Data based on typical application software.
3. Time measured between interrupt event and interrupt vector fetch. ∆tc(INST) is the number of tCPU cycles needed to fin-

ish the current instruction execution.

1. Data based on design simulation and/or technology characteristics, not tested in production.

Figure 61. Typical Application with an External Clock Source

ST7LITE0xY0, ST7LITESxY0

13.6 MEMORY CHARACTERISTICS

TA = -40°C to 105°C, unless otherwise specified

13.6.1 RAM and Hardware Registers

13.6.2 FLASH Program Memory

13.6.3 EEPROM Data Memory

Notes: 1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg- isters (only in HALT mode). Guaranteed by construction, not tested in production. 2. Up to 32 bytes can be programmed at a time. 3. The data retention time increases when the TA decreases. 4. Data based on reliability test results and monitored in production. 5. Data based on characterization results, not tested in production. 6. Guaranteed by Design. Not tested in production. 7. Design target value pending full product characterization. Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode 1) HALT mode (or RESET) 1.6 V Symbol Parameter Conditions Min Typ Max Unit VDD Operating voltage for Flash write/erase 2.4 5.5 V tprog Programming time for 1~32 bytes 2) TA=−40 to +105°C 5 10 ms Programming time for 1.5 kBytes TA=+25°C 0.24 0.48 s tRET Data retention 4) TA=+55°C3) 20 years NRW Write erase cycles TA=+25°C 10K 7) cycles IDD Supply current Read / Write / Erase modes fCPU = 8MHz, VDD = 5.5V 2.6 6) mA No Read/No Write Mode 100 µA Power down mode / HALT 0 0.1 µA Symbol Parameter Conditions Min Typ Max Unit VDD Operating voltage for EEPROM write/erase 2.4 5.5 V tprog Programming time for 1~32 bytes TA=−40 to +105°C 5 10 ms tret Data retention 4) TA=+55°C 3) 20 years NRW Write erase cycles TA=+25°C 300K 7) cycles

ST7LITE0xY0, ST7LITESxY0

13.7 EMC (ELECTROMAGNETIC COMPATIBILITY) CHARACTERISTICS

Susceptibility tests are performed on a sample ba- sis during product characterization.

13.7.1 Functional EMS (Electro Magnetic

Susceptibility) Based on a simple running application on the product (toggling two -+LEDs through I/O ports), the product is stressed by two electro magnetic events until a failure occurs (indicated by the LEDs). ■ ESD: Electro-Static Discharge (positive and negative) is applied on all pins of the device until a functional disturba nce occurs. This test conforms with the IEC 1000-4-2 standard. ■ FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 1000-4- 4 standard. A device reset allows normal operations to be re- sumed. The test results are given in the table be- low based on the EMS levels and classes defined in application note AN1709.

13.7.1.1 Designing hardened software to avoid

EMC characterization and optimization are per- formed at component level with a typical applica- tion environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations: The software flowchart must include the manage- ment of runaway conditions such as: – Corrupted program counter – Unexpected reset – Critical Data corruption (control registers...) Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be repro- duced by manually forcing a low state on the RE- SET pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be ap- plied directly on the device, over the range of specification values. When unexpected behaviour is detected, the software can be hardened to pre- vent unrecoverable errors occurring (see applica- tion note AN1015).

13.7.2 EMI (Electromagnetic interference)

Based on a simple application running on the product (toggling two LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. Note: 1. Data based on characterization results, not tested in production. Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD=5V, TA=+25°C, fOSC=8MHz conforms to IEC 1000-4-2 2B VFFTB Fast transient voltage burst limits to be applied through 100pF on VDD and VDD pins to induce a func- tional disturbance VDD=5V, TA=+25°C, fOSC=8MHz conforms to IEC 1000-4-4 3B Table 20: EMI emissions Symbol Parameter Conditions Monitored Frequency Band Max vs. [fOSC/fCPU] Unit 1/4MHz 1/8MHz SEMI Peak level VDD=5V, TA=+25°C, SO16 package, conforming to SAE J 1752/3 0.1MHz to 30MHz 8 14 dBµV30MHz to 130MHz 27 32 130MHz to 1GHz 26 28 SAE EMI Level 3.5 4 -

ST7LITE0xY0, ST7LITESxY0 EMC CHARACTERISTICS (Cont’d)

13.7.3 Absolute Maximum Ratings (Electrical

Sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity.

13.7.3.1 Electro-Static Discharge (ESD)

Electro-Static Discharges (a positive then a nega- tive pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test conforms to the JESD22- A114A standard. ESD absolute maximum ratings Notes: 1. Data based on characterization results, not tested in production.

13.7.3.2 Static Latch-Up

■ LU: Two complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/ O pin) are performed on each sample. These test are compliant with the EIA/JESD 78 IC latch-up standard. Electrical Sensitivities Note: 1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec- ifications, that means when a device belongs to Class A it exceeds the JEDEC standar d. B Class strictly covers all the JEDEC criteria (international standard). Symbol Ratings Conditions Maximum value 1) Unit VESD(HBM) Electro-static discharge voltage (Human Body Model) TA=+25°C conforming to JESD22-A114 4000 V Symbol Parameter Conditions Class 1) LU Static latch-up class TA=+25°C conforming to JESD78A II level A

13.8 I/O PORT PIN CHARACTERISTICS

13.8.1 General Characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

1. Data based on characterization results, not tested in production.
2. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
3. The R PU pull-up equivalent resistor is based on a resistive transistor (corresponding I PU current characteristics de-
4. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

Figure 62. Two typical applications with unused I/O pin configured as input Figure 63. Typical IPU vs. VDD with VIN=VSSl (external pull-up of 10k mandatory in This is to avoid entering ICC mode unexpectedly during a reset. noisy environment).

ST7LITE0xY0, ST7LITESxY0 I/O PORT PIN CHARACTERISTICS (Cont’d)

13.8.2 Output Driving Current

Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Notes: 1. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 3. Not tested in production, based on characterization results. Symbol Parameter Conditions Min Max Unit VOL Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 65) VDD=5V IIO=+5mA T A≤85°C TA≥85°C 1.0 1.2 V IIO=+2mA T A≤85°C TA≥85°C 0.4 0.5 Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time (see Figure 66) I IO=+20mA,TA≤85°C TA≥85°C 1.3 1.5 IIO=+8mA T A≤85°C TA≥85°C 0.75 0.85 VOH Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 72) IIO=-5mA, T A≤85°C TA≥85°C VDD-1.5 VDD-1.6 IIO=-2mA T A≤85°C TA≥85°C VDD-0.8 VDD-1.0 VOL 1)3) Output low level voltage for a standard I/O pin when 8 pins are sunk at same time (see Figure 64) VDD=3.3V IIO=+2mA T A≤85°C TA≥85°C 0.5 0.6 Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time IIO=+8mA T A≤85°C TA≥85°C 0.5 0.6 VOH 2)3) Output high level voltage for an I/O pin when 4 pins are sourced at same time IIO=-2mA T A≤85°C TA≥85°C VDD-0.8 VDD-1.0 VOL 1)3) Output low level voltage for a standard I/O pin when 8 pins are sunk at same time VDD=2.7V IIO=+2mA T A≤85°C TA≥85°C 0.6 0.7 Output low level voltage for a high sink I/O pin when 4 pins are sunk at same time IIO=+8mA T A≤85°C TA≥85°C 0.6 0.7 VOH 2)3) Output high level voltage for an I/O pin when 4 pins are sourced at same time (see Figure 69) IIO=-2mA T A≤85°C TA≥85°C VDD-0.9 VDD-1.0

ST7LITE0xY0, ST7LITESxY0

13.9 CONTROL PIN CHARACTERISTICS

13.9.1 Asynchronous RESET Pin

TA = -40°C to 105°C, unless otherwise specified Notes: 1. Data based on characterization results, not tested in production. 2. The IIO current sunk must always respect the absolute maximum rating specified in section 13.2.2 on page 82 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 3. The RON pull-up equivalent resistor is based on a resistiv e transistor. Specified for voltages on RESET pin between VILmax and VDD 4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on RESET pin with a duration below th(RSTL)in can be ignored. Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage V SS - 0.3 0.3xVDD VVIH Input high level voltage 0.7xV DD VDD + 0.3 Vhys Schmitt trigger voltage hysteresis 1) 2V VOL Output low level voltage 2) VDD=5V IIO=+5mA TA≤85°C TA≤105°C 0.5 1.0

1.2 VIIO=+2mA TA≤85°C

TA≤105°C 0.2 0.4 0.5 RON Pull-up equivalent resistor 3) 1) VDD=5V 20 40 80 k Ω tw(RSTL)out Generated reset pulse duration Internal reset sources 30 µs th(RSTL)in External reset pulse hold time 4) 20 µs tg(RSTL)in Filtered glitch duration 200 ns

13.10 COMMUNICATION INTERFACE CHARACTERISTICS

13.10.1 SPI - Serial Peripheral Interface

fOSC, and TA unless otherwise specified. Figure 78. SPI Slave Timing Diagram with CPHA=0 3)

1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has

its alternate function capability released. In this case, the pin status depends on the I/O port configuration.

1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD.
2. Depends on fCPU. For example, if fCPU=8MHz, then TCPU = 1/fCPU =125ns and tsu(SS)=175ns

1. Unless otherwise specified, typical data are based on TA=25°C and VDD-VSS=5V. They are given only as design guide-
2. Data based on characterization results, not tested in production.
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ). Data

based on characterization results, not tested in production.

1. The stabilization time of the AD converter is masked by the first t LOAD. The first conversion after the enable is then

Figure 81. Typical Application with ADC

Figure 82. RAIN max. vs fADC with CAIN=0pF1) Figure 83. Recommended CAIN/RAIN values2)

1. CPARASITIC represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad ca-

pacitance (3pF). A high CPARASITIC value will downgrade conversion accuracy. To remedy this, fADC should be reduced.

1. This graph shows that depending on the input signal variation (fAIN), CAIN can be increased for stabilization and to allow

the use of a larger serial resistor (RAIN). It is valid for all fADC frequencies ≤ 4MHz.

13.11.1 General PCB Design Guidelines

same I/O port as the A/D input being converted.

4 MHz

2 MHz

1 MHz

ST7LITE0xY0, ST7LITESxY0 ADC CHARACTERISTICS (Cont’d) ADC Accuracy with VDD=5.0V TA = -40°C to 85°C, unless otherwise specified Notes: 1. Data based on characterization results over the whole temperature range, monitored in production. 2. Injecting negative current on any of the analog input pins significantly reduces the accuracy of any conversion being performed on any analog input. Analog pins can be protected against negative injection by adding a Schottky di ode (pin to ground). Injecting negative current on digital input pins degrades ADC accuracy especially if performed on a pin close to the analog input pins. Any positive injection current within the limits specified for I INJ(PIN) and ΣIINJ(PIN) in Section 13.8 does not affect the ADC accuracy. Symbol Parameter Conditions Typ Max Unit ET Total unadjusted error 2) fCPU=4MHz, fADC=2MHz ,VDD=5.0V LSB EO Offset error 2) -0.5 / +1 EG Gain Error 2) ±1 ED Differential linearity error 2) ±11) EL Integral linearity error 2) ±11) ET Total unadjusted error 2) fCPU=8MHz, fADC=4MHz ,VDD=5.0V LSB EO Offset error 2) -0.5 / 3.5 EG Gain Error 2) -2 / 0 ED Differential linearity error 2) ±11) EL Integral linearity error 2) ±11)

ST7LITE0xY0, ST7LITESxY0 ADC CHARACTERISTICS (Cont’d) Notes: 1. Data based on characterization results over the whole temperature range, not tested in production. 2. For precise conversion results it is recommended to calibrate the amplifier at the following two points: – offset at V INmin = 0V – gain at full scale (for example V IN=250mV) 3. Monotonicity guaranteed if VIN increases or decreases in steps of min. 5mV. Symbol Parameter Conditions Min Typ Max Unit VDD(AMP) Amplifier operating voltage 4.5 5.5 V VIN Amplifier input voltage V DD=5V 0 250 mV VOFFSET Amplifier offset voltage 200 mV VSTEP Step size for monotonicity3) 5m V Linearity Output Voltage Response Linear Gain factor Amplified Analog input Gain 2) 71) 89 1) Vmax Output Linearity Max Voltage VINmax = 250mV, VDD=5V 2.2 2.4 V Vmin Output Linearity Min Voltage 200 mV Vin Vout (ADC input) Vmax Vmin 250mV0V Noise (OPAMP input)

14 PACKAGE CHARACTERISTICS

offers these devices in ECOPACK® packages. fications are available at: www.st.com.

14.1 PACKAGE MECHANICAL DATA

Figure 86. 20-Lead Very thin Fine pitch Quad Flat No-Lead Package and rounded to 4 decimal digits.

ST7LITE0xY0, ST7LITESxY0

14.2 THERMAL CHARACTERISTICS

Notes: 1. The maximum chip-junction temperature is based on technology characteristics. 2. The maximum power dissipation is obtained from the formula PD = (TJ -TA) / RthJA. The power dissipation of an application can be defined by the user with the formula: P D=PINT+PPORT where PINT is the chip internal power (IDDxVDD) and PPORT is the port power dissipation depending on the ports used in the application. Symbol Ratings Value Unit RthJA (junction to ambient) DIP16 TBD °C/W TJmax Maximum junction temperature 1) 150 °C PDmax Power dissipation 2) 500 mW

ST7LITE0xY0, ST7LITESxY0

15 DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for production in user pro- grammable versions (FLASH) as well as in factory coded versions (FASTROM). ST7PLITE0x and ST7PLITES2/S5 devices are Factory Advanced Service Technique ROM (FAS- TROM) versions: they are factory-programmed XFlash devices. ST7FLITE0x and ST7FLITES2/S5 XFlash devices are shipped to customers with a default program memory content (FFh). The OSC option bit is pro- grammed to 0 by default. The FASTROM factory coded parts contain the code supplied by the customer. This implies that FLASH devices have to be configured by the cus- tomer using the Option Bytes while the FASTROM devices are factory-configured.

15.1 OPTION BYTES

The two option bytes allow the hardware configu- ration of the microcontroller to be selected. The option bytes can be accessed only in pro- gramming mode (for example using a standard ST7 programming tool). OPTION BYTE 0 Bits 7:4 = Reserved, must always be 1. Bits 3:2 = SEC[1:0] Sector 0 size definition These option bits indicate the size of sector 0 ac- cording to the following table. Note 1: Configuration available for ST7LITE0x de- vices only. Bit 1 = FMP_R Read-out protection Readout protection, when selected provides a pro- tection against program memory content extrac- tion and against write access to Flash memory. Erasing the option bytes when the FMP_R option is selected will cause the whole memory to be erased first, and the device can be reprogrammed. Refer to Section 4.5 and the ST7 Flash Program- ming Reference Manual for more details. 0: Read-out protection off 1: Read-out protection on Bit 0 = FMP_W FLASH write protection This option indicates if the FLASH program mem- ory is write protected. Warning: When this option is selected, the pro- gram memory (and the option bit itself) can never be erased or programmed again. 0: Write protection off 1: Write protection on Sector 0 Size SEC1 SEC0 0.5k 00 1k 01 1.5k 1) 1x

Bit 7 = PLLx4x8 PLL Factor selection. Bit 5 = Reserved, must always be 1. close as possible to the ST7 device. Table 21. List of valid option combinations lected threshold as shown in Table 22. Table 22. LVD Threshold Configuration This option bit selects the watchdog type.

ST7LITE0xY0, ST7LITESxY0

15.2 DEVICE ORDERING INFORMATION AND TRANSFER OF CUSTOMER CODE

Customer code is made up of the FASTROM con- tents and the list of the selected options (if any). The FASTROM contents are to be sent on dis- kette, or by electronic means, with the S19 hexa- decimal file generated by the development tool. All unused bytes must be set to FFh. The selected op- tions are communicated to STMicroelectronics us- ing the correctly completed OPTION LIST append- ed. Refer to application note AN1635 for information on the counter listing returned by ST after code has been transferred. The STMicroelectronics Sales Organization will be pleased to provide detailed information on con- tractual points.

Figure 89. Ordering information scheme further information on any aspect of this device, please contact the ST Sales Office nearest to you.

ST7LITE0xY0, ST7LITESxY0 ST7LITE0xY0 AND ST7LITESxY0 FASTROM MICROCONTROLLER OPTION LIST (Last update: November 2007) *FASTROM code name is assigned by STMicroelectronics. FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. Warning: Addresses 1000h, 1001h, FFDEh and FFDFh are reserved areas for ST to program RCCR0 and RCCR1 (see section 7.1 on page 24). Conditioning (check only one option): Special Marking: [ ] No [ ] Yes Authorized characters are letters, digits, '.', '-', '/' and spaces only. Maximum character count: PDIP16 (15 char. max) : _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Sector 0 size: [ ] 0.5K [ ] 1K [ ] 1.5K Readout Protection: [ ] Disabled [ ] Enabled FLASH write Protection: [ ] Disabled [ ] Enabled Clock Source Selection: [ ] In ternal RC [ ] External Clock PLL [ ] Disabled [ ] PLLx4 [ ] PLLx8 LVD Reset [ ] Disabled [ ] Highest threshold [ ] Medium threshold [ ] Lowest threshold Watchdog Selection: [ ] Software Ac tivation [ ] Hard ware Activation Watchdog Reset on Halt: [ ] Disabled [ ] Enabled Important note: Not all configurations are available. See Table 21 on page 113 for authorized option byte combinations and “Ordering information scheme” on page 115. Please download the latest version of this option list from: Memory size (check only one option): [ ] 1 K [ ] 1.5 K Device type (check only one option): [ ] ST7PLITES2Y0 [ ] ST7PLITES5Y0 [ ] ST7PLITE02Y0 [ ] ST7PLITE05Y0 [ ] ST7PLITE09Y0 PDIP16 [ ] Tube SO16 [ ] Tape & Reel [ ] Tube QFN20 [ ] Tape & Reel [ ] Tray

15.3 DEVELOPMENT TOOLS

program your microcontrollers.

15.3.1 Starter kits

15.3.2 Development and debugging tools

grated programming interface.

15.3.3 Programming tools

15.3.4 Order Codes for Development and

15.3.5 Order codes for ST7LITE0/ST7LITES development tools

Table 23. Development tool order codes for the ST7LITE0/ST7LITES family

1. Available from ST or from Raisonance, www.raisonance.com
2. Includes connection kit for DIP16/SO16 only. See “How to order an EMU or DVP” in ST product and tool selection guide
3. Add suffix /EU, /UK or /US for the power supply for your region
4. Parallel port connection to PC

15.4 ST7 APPLICATION NOTES

Table 24. ST7 Application Notes

ST7LITE0xY0, ST7LITESxY0

16 KNOWN LIMITATIONS

16.1 Execution of BTJX Instruction

Description

Executing a BTJx instruction jumps to a random address in the following conditions: the jump goes to a lower address (jump backward) and the test is performed on a data located at the address 00FFh.

16.2 In-Circuit Programming of devices

previously programmed with Hardware Watchdog option In-Circuit Programming of devices configured with Hardware Watchdog (WDGSW bit in option byte 1 programmed to 0) requires certain precautions (see below). In-Circuit Programming uses ICC mode. In this mode, the Hardware Watchdog is not automatical- ly deactivated as one might expect. As a conse- quence, internal resets are generated every 2 ms by the watchdog, thus preventing programming. The device factory configuration is Software Watchdog so this issue is not seen with devices that are programmed for the first time. For the same reason, devices programmed by the user with the Software Watchdog option are not impact- ed. The only devices impacted are those that have previously been programmed with the Hardware Watchdog option. Workaround Devices configured with Hardware Watchdog must be programmed using a specific program- ming mode that ignores the option byte settings. In this mode, an external clock, normally provided by the programming tool, has to be used. In ST tools, this mode is called "ICP OPTIONS DISABLED". Sockets on ST programming tools (such as ST7MDT10-EPB) are controlled using "ICP OP- TIONS DISABLED" mode. Devices can therefore be reprogrammed by plugging them in the ST Pro- gramming Board socket, whatever the watchdog configuration. When using third-party tools, please refer the manufacturer's documentation to check how to ac- cess specific programming modes. If a tool does not have a mode that ignores the option byte set- tings, devices programmed with the Hardware watchdog option cannot be reprogrammed using this tool.

16.3 In-Circuit Debugging with Hardware

In Circuit Debugging is impacted in the same way as In Circuit Programming by the activation of the hardware watchdog in ICC mode. Please refer to Section 16.2.

16.4 Recommendations when LVD is enabled

When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-down capacitor is required to filter noise on the reset line.

16.5 Clearing Active Interrupts Outside

When an active interrupt request occurs at the same time as the related flag or interrupt mask is being cleared, the CC register may be corrupted. Concurrent interrupt context The symptom does not occur when the interrupts are handled normally, i.e. when: – The interrupt request is cleared (flag reset or in- terrupt mask) within its own interrupt routine – The interrupt request is cleared (flag reset or in- terrupt mask) within any interrupt routine – The interrupt request is cleared (flag reset or in- terrupt mask) in any part of the code while this in- terrupt is disabled If these conditions are not met, the symptom can be avoided by implementing the following se- quence: Perform SIM and RIM operation before and after resetting an active interrupt request Ex: SIM reset flag or interrupt mask RIM

17 REVISION HISTORY

Table 25. Revision History Revision History continued overleaf ...

ST7LITE0xY0, ST7LITESxY0 09-Oct-06 5 Removed QFN20 pinout and mechanical data. Modified text in External Interrupt Function section in section 10.2.1 on page 42 Modified Table 24 on page 116 (and QFN20 rows in grey). Added “External Clock Source” on page 91 and Figure 61 on page 91 Modified description of CNTR[11:0] bits in section 11.2.6 on page 56 Updated option list on page 116 Changed section 15.3 on page 117 19-Nov-07 6 Title of the document modified Modified LOCKED bit description in section 8.4.4 on page 36 In Table 1 on page 7 and section 13.2.2 on page 82, note “negative injection not allowed on PB0 and PB1 pins” replaced by “negative injection not allowed on PB1 pin” Added QFN20 package pinout (with new QFN20 mechanical data): Figure 2 on page 6 and Figure 86 on page 109 Modified section 8.4.4 on page 36 Removed one note in section 11.1.3.1 on page 49 Modified section 13.7 on page 93 Modified “PACKAGE MECHANICAL DATA” on page 109 (values in inches rounded to 4 dec- imal digits) Modified section 15.2 on page 114 (“Ordering information scheme” on page 115 added and table removed) and option list on page 116 Removed “soldering information” section Modified section 15.3.5 on page 117